drm/amd/display: fix code to control 48mhz refclk
authorEric Yang <Eric.Yang2@amd.com>
Thu, 18 Jul 2019 17:56:59 +0000 (13:56 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 11 Oct 2019 00:33:15 +0000 (19:33 -0500)
[Why]
The SMU message to enable this feature looks at argument. Previous code
didn't send right argument. This change will allow the feature to be
be enabled.

[How]
Fixed one issue where SMU message to enable the feature was sent without
setting the parameter.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

index c0e58434be39f2016447501764ffd37cae61fcbc..a2a4c7ddc856215cd1882676fbe32acadb1f9b72 100644 (file)
@@ -649,8 +649,9 @@ void rn_clk_mgr_construct(
                        pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
        }
 
-       /* enable powerfeatures when displaycount goes to 0 */
-       if (!debug->disable_48mhz_pwrdwn)
-               rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr);
+       if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+               /* enable powerfeatures when displaycount goes to 0 */
+               rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
+       }
 }
 
index fd919b82e9020ea246843ba872cb6d167864c028..8e860f567d5c984bfa11b27bed4ca9ec6d83e16f 100644 (file)
@@ -190,12 +190,12 @@ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum
                disp_count);
 }
 
-void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr)
+void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
 {
        rn_vbios_smu_send_msg_with_param(
                        clk_mgr,
                        VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
-                       0);
+                       enable);
 }
 
 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
index fe2986a2c7a2d42c9cbf2744c1f6b01f348402b0..ccc01879c9d4a627b3b7fd24bc866cf0ee73967a 100644 (file)
@@ -34,7 +34,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int
 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
-void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr);
+void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
 
 #endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */
index de182185fe1f558ff83f00b6b2c7e917941525bb..be864bfd579788f143437446d99a49fba390b04b 100644 (file)
@@ -804,7 +804,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                .disable_pplib_wm_range = false,
                .scl_reset_length10 = true,
                .sanity_checks = true,
-               .disable_48mhz_pwrdwn = true,
+               .disable_48mhz_pwrdwn = false,
 };
 
 static const struct dc_debug_options debug_defaults_diags = {