ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE

With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.

Let's also add a comment for the clocksel clock that matches the
documentation.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
index 06466d36caa9f27b8782b47ab42c1bd8a11fda71..10f452152b0c85c93c076b7b110d82cc8c68d1b4 100644 (file)
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -285,13 +285,21 @@
                ti,invert-autoidle-bit;
        };
 
-       dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clock-output-names = "dpll_core_byp_mux";
-               clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
-               ti,bit-shift = <23>;
-               reg = <0x012c>;
+       /* CM_CLKSEL_DPLL_CORE */
+       clock@12c {
+               compatible = "ti,clksel";
+               reg = <0x12c>;
+               #clock-cells = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               dpll_core_byp_mux: clock@23 {
+                       reg = <23>;
+                       compatible = "ti,mux-clock";
+                       clock-output-names = "dpll_core_byp_mux";
+                       clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                       #clock-cells = <0>;
+               };
        };
 
        dpll_core_ck: clock@120 {