drm/radeon: add get_allowed_info_register for SI
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Oct 2014 14:03:31 +0000 (10:03 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 19 Mar 2015 16:26:40 +0000 (12:26 -0400)
Registers that can be fetched from the info ioctl.

Tested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/si.c
drivers/gpu/drm/radeon/sid.h

index 37d7cd7c6c463cabb9cf95925f027f56c52292e8..21e5fe64f3621d8b75cfa74fae870f82fe9209cb 100644 (file)
@@ -1908,6 +1908,7 @@ static struct radeon_asic si_asic = {
        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
        .get_xclk = &si_get_xclk,
        .get_gpu_clock_counter = &si_get_gpu_clock_counter,
+       .get_allowed_info_register = si_get_allowed_info_register,
        .gart = {
                .tlb_flush = &si_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
index dca6bc89bc1cdc05006568b1825fb4c1d0d0310e..f650bff863cdbde37dce05884a368d59dadfac2f 100644 (file)
@@ -746,6 +746,8 @@ u32 si_get_xclk(struct radeon_device *rdev);
 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 int si_get_temp(struct radeon_device *rdev);
+int si_get_allowed_info_register(struct radeon_device *rdev,
+                                u32 reg, u32 *val);
 int si_dpm_init(struct radeon_device *rdev);
 void si_dpm_setup_asic(struct radeon_device *rdev);
 int si_dpm_enable(struct radeon_device *rdev);
index e088e5558da0117c1d3a85cac06bcf129a8a78c2..0d2295fd28443675a015c24c414be6c8e4227364 100644 (file)
@@ -1264,6 +1264,36 @@ static void si_init_golden_registers(struct radeon_device *rdev)
        }
 }
 
+/**
+ * si_get_allowed_info_register - fetch the register for the info ioctl
+ *
+ * @rdev: radeon_device pointer
+ * @reg: register offset in bytes
+ * @val: register value
+ *
+ * Returns 0 for success or -EINVAL for an invalid register
+ *
+ */
+int si_get_allowed_info_register(struct radeon_device *rdev,
+                                u32 reg, u32 *val)
+{
+       switch (reg) {
+       case GRBM_STATUS:
+       case GRBM_STATUS2:
+       case GRBM_STATUS_SE0:
+       case GRBM_STATUS_SE1:
+       case SRBM_STATUS:
+       case SRBM_STATUS2:
+       case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
+       case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
+       case UVD_STATUS:
+               *val = RREG32(reg);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 #define PCIE_BUS_CLK                10000
 #define TCLK                        (PCIE_BUS_CLK / 10)
 
index 99a9835c9f615919c063af1ce0ca0e596aed8c15..3afac301398388315f78d6cb7cb62e84e7314581 100644 (file)
 #define UVD_UDEC_DBW_ADDR_CONFIG                       0xEF54
 #define UVD_RBC_RB_RPTR                                        0xF690
 #define UVD_RBC_RB_WPTR                                        0xF694
+#define UVD_STATUS                                     0xf6bc
 
 #define        UVD_CGC_CTRL                                    0xF4B0
 #      define DCM                                      (1 << 0)