Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 1 Aug 2016 22:36:01 +0000 (18:36 -0400)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 1 Aug 2016 22:36:01 +0000 (18:36 -0400)
Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for ARM SoCs.

  A slew of changes this release cycle.  The reset driver tree, that we
  merge through arm-soc for historical reasons, is also sizable this
  time around.

  Among the changes:

   - clps711x: Treewide changes to compatible strings, merged here for simplicity.
   - Qualcomm: SCM firmware driver cleanups, move to platform driver
   - ux500: Major cleanups, removal of old mach-specific infrastructure.
   - Atmel external bus memory driver
   - Move of brcmstb platform to the rest of bcm
   - PMC driver updates for tegra, various fixes and improvements
   - Samsung platform driver updates to support 64-bit Exynos platforms
   - Reset controller cleanups moving to devm_reset_controller_register() APIs
   - Reset controller driver for Amlogic Meson
   - Reset controller driver for Hisilicon hi6220
   - ARM SCPI power domain support"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits)
  ARM: ux500: consolidate base platform files
  ARM: ux500: move soc_id driver to drivers/soc
  ARM: ux500: call ux500_setup_id later
  ARM: ux500: consolidate soc_device code in id.c
  ARM: ux500: remove cpu_is_u* helpers
  ARM: ux500: use CLK_OF_DECLARE()
  ARM: ux500: move l2x0 init to .init_irq
  mfd: db8500 stop passing around platform data
  ASoC: ab8500-codec: remove platform data based probe
  ARM: ux500: move ab8500_regulator_plat_data into driver
  ARM: ux500: remove unused regulator data
  soc: raspberrypi-power: add CONFIG_OF dependency
  firmware: scpi: add CONFIG_OF dependency
  video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip
  input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip
  pwm: clps711x: Changing the compatibility string to match with the smallest supported chip
  serial: clps711x: Changing the compatibility string to match with the smallest supported chip
  irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip
  clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip
  clk: clps711x: Changing the compatibility string to match with the smallest supported chip
  ...

12 files changed:
1  2 
Documentation/driver-model/devres.txt
MAINTAINERS
arch/arm/boot/dts/exynos5420-peach-pit.dts
arch/arm/mach-exynos/Kconfig
arch/arm/mach-exynos/exynos.c
arch/arm/mach-omap2/pdata-quirks.c
drivers/clocksource/clps711x-timer.c
drivers/cpufreq/s5pv210-cpufreq.c
drivers/memory/omap-gpmc.c
drivers/power/reset/Kconfig
drivers/power/reset/Makefile
drivers/soc/samsung/pm_domains.c

Simple merge
diff --cc MAINTAINERS
Simple merge
index ecf139f31c4c7995e5bef7d46bd48ab6d6acf283,58b334f5f1d6d44f1bb0be455201c2310131b43a..8f820de890b43559e55e475a9b51f8975f32e346
@@@ -18,7 -19,7 +18,8 @@@ menuconfig ARCH_EXYNO
        select EXYNOS_THERMAL
        select EXYNOS_PMU
        select EXYNOS_SROM
+       select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
 +      select GPIOLIB
        select HAVE_ARM_SCU if SMP
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
index ecbfa5dd3c543ad8ab7b34823e830c3387ab1e6b,a8620c6eb723aa2e89f7a1b5d77a01c3de85b4d6..acabf0bffc5dbf2bc7bd2effa800c3002cc9d2c7
  #include <asm/mach/map.h>
  
  #include <mach/map.h>
 +#include <plat/cpu.h>
  
  #include "common.h"
- #include "mfc.h"
  
  static struct map_desc exynos4_iodesc[] __initdata = {
        {
Simple merge
index 84aed78261e46e6cf6427298fdc78a16790bf8d1,7c65f9e1d347912d225602e520c8d7cb4266d298..24db6d605549cec0a4f0e611be0de44161b98b84
@@@ -112,12 -112,14 +112,12 @@@ static int __init clps711x_timer_init(s
  
        switch (of_alias_get_id(np, "timer")) {
        case CLPS711X_CLKSRC_CLOCKSOURCE:
 -              BUG_ON(_clps711x_clksrc_init(clock, base));
 -              break;
 +              return _clps711x_clksrc_init(clock, base);
        case CLPS711X_CLKSRC_CLOCKEVENT:
 -              BUG_ON(_clps711x_clkevt_init(clock, base, irq));
 -              break;
 +              return _clps711x_clkevt_init(clock, base, irq);
        default:
 -              break;
 +              return -EINVAL;
        }
  }
- CLOCKSOURCE_OF_DECLARE(clps711x, "cirrus,clps711x-timer", clps711x_timer_init);
+ CLOCKSOURCE_OF_DECLARE(clps711x, "cirrus,ep7209-timer", clps711x_timer_init);
  #endif
Simple merge
Simple merge
Simple merge
Simple merge
index 0000000000000000000000000000000000000000,f60515eefb660378e02d01e2f304785acccdbf94..4822346aadc6c8766e3d9cee67b57afea74f76d0
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,245 +1,245 @@@
 -      __raw_writel(pwr, base);
+ /*
+  * Exynos Generic power domain support.
+  *
+  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+  *            http://www.samsung.com
+  *
+  * Implementation of Exynos specific power domain control which is used in
+  * conjunction with runtime-pm. Support for both device-tree and non-device-tree
+  * based power domain support is included.
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+  * published by the Free Software Foundation.
+ */
+ #include <linux/io.h>
+ #include <linux/err.h>
+ #include <linux/slab.h>
+ #include <linux/pm_domain.h>
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
+ #include <linux/sched.h>
+ #define MAX_CLK_PER_DOMAIN    4
+ struct exynos_pm_domain_config {
+       /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */
+       u32 local_pwr_cfg;
+ };
+ /*
+  * Exynos specific wrapper around the generic power domain
+  */
+ struct exynos_pm_domain {
+       void __iomem *base;
+       char const *name;
+       bool is_off;
+       struct generic_pm_domain pd;
+       struct clk *oscclk;
+       struct clk *clk[MAX_CLK_PER_DOMAIN];
+       struct clk *pclk[MAX_CLK_PER_DOMAIN];
+       struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
+       u32 local_pwr_cfg;
+ };
+ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
+ {
+       struct exynos_pm_domain *pd;
+       void __iomem *base;
+       u32 timeout, pwr;
+       char *op;
+       int i;
+       pd = container_of(domain, struct exynos_pm_domain, pd);
+       base = pd->base;
+       for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+               if (IS_ERR(pd->asb_clk[i]))
+                       break;
+               clk_prepare_enable(pd->asb_clk[i]);
+       }
+       /* Set oscclk before powering off a domain*/
+       if (!power_on) {
+               for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                       if (IS_ERR(pd->clk[i]))
+                               break;
+                       pd->pclk[i] = clk_get_parent(pd->clk[i]);
+                       if (clk_set_parent(pd->clk[i], pd->oscclk))
+                               pr_err("%s: error setting oscclk as parent to clock %d\n",
+                                               pd->name, i);
+               }
+       }
+       pwr = power_on ? pd->local_pwr_cfg : 0;
 -      while ((__raw_readl(base + 0x4) & pd->local_pwr_cfg) != pwr) {
++      writel_relaxed(pwr, base);
+       /* Wait max 1ms */
+       timeout = 10;
 -              on = __raw_readl(pd->base + 0x4) & pd->local_pwr_cfg;
++      while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) != pwr) {
+               if (!timeout) {
+                       op = (power_on) ? "enable" : "disable";
+                       pr_err("Power domain %s %s failed\n", domain->name, op);
+                       return -ETIMEDOUT;
+               }
+               timeout--;
+               cpu_relax();
+               usleep_range(80, 100);
+       }
+       /* Restore clocks after powering on a domain*/
+       if (power_on) {
+               for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                       if (IS_ERR(pd->clk[i]))
+                               break;
+                       if (IS_ERR(pd->pclk[i]))
+                               continue; /* Skip on first power up */
+                       if (clk_set_parent(pd->clk[i], pd->pclk[i]))
+                               pr_err("%s: error setting parent to clock%d\n",
+                                               pd->name, i);
+               }
+       }
+       for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+               if (IS_ERR(pd->asb_clk[i]))
+                       break;
+               clk_disable_unprepare(pd->asb_clk[i]);
+       }
+       return 0;
+ }
+ static int exynos_pd_power_on(struct generic_pm_domain *domain)
+ {
+       return exynos_pd_power(domain, true);
+ }
+ static int exynos_pd_power_off(struct generic_pm_domain *domain)
+ {
+       return exynos_pd_power(domain, false);
+ }
+ static const struct exynos_pm_domain_config exynos4210_cfg __initconst = {
+       .local_pwr_cfg          = 0x7,
+ };
+ static const struct of_device_id exynos_pm_domain_of_match[] __initconst = {
+       {
+               .compatible = "samsung,exynos4210-pd",
+               .data = &exynos4210_cfg,
+       },
+       { },
+ };
+ static __init int exynos4_pm_init_power_domain(void)
+ {
+       struct device_node *np;
+       const struct of_device_id *match;
+       for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) {
+               const struct exynos_pm_domain_config *pm_domain_cfg;
+               struct exynos_pm_domain *pd;
+               int on, i;
+               pm_domain_cfg = match->data;
+               pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+               if (!pd) {
+                       pr_err("%s: failed to allocate memory for domain\n",
+                                       __func__);
+                       of_node_put(np);
+                       return -ENOMEM;
+               }
+               pd->pd.name = kstrdup_const(strrchr(np->full_name, '/') + 1,
+                                           GFP_KERNEL);
+               if (!pd->pd.name) {
+                       kfree(pd);
+                       of_node_put(np);
+                       return -ENOMEM;
+               }
+               pd->name = pd->pd.name;
+               pd->base = of_iomap(np, 0);
+               if (!pd->base) {
+                       pr_warn("%s: failed to map memory\n", __func__);
+                       kfree_const(pd->pd.name);
+                       kfree(pd);
+                       continue;
+               }
+               pd->pd.power_off = exynos_pd_power_off;
+               pd->pd.power_on = exynos_pd_power_on;
+               pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
+               for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                       char clk_name[8];
+                       snprintf(clk_name, sizeof(clk_name), "asb%d", i);
+                       pd->asb_clk[i] = of_clk_get_by_name(np, clk_name);
+                       if (IS_ERR(pd->asb_clk[i]))
+                               break;
+               }
+               pd->oscclk = of_clk_get_by_name(np, "oscclk");
+               if (IS_ERR(pd->oscclk))
+                       goto no_clk;
+               for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+                       char clk_name[8];
+                       snprintf(clk_name, sizeof(clk_name), "clk%d", i);
+                       pd->clk[i] = of_clk_get_by_name(np, clk_name);
+                       if (IS_ERR(pd->clk[i]))
+                               break;
+                       /*
+                        * Skip setting parent on first power up.
+                        * The parent at this time may not be useful at all.
+                        */
+                       pd->pclk[i] = ERR_PTR(-EINVAL);
+               }
+               if (IS_ERR(pd->clk[0]))
+                       clk_put(pd->oscclk);
+ no_clk:
++              on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
+               pm_genpd_init(&pd->pd, NULL, !on);
+               of_genpd_add_provider_simple(np, &pd->pd);
+       }
+       /* Assign the child power domains to their parents */
+       for_each_matching_node(np, exynos_pm_domain_of_match) {
+               struct generic_pm_domain *child_domain, *parent_domain;
+               struct of_phandle_args args;
+               args.np = np;
+               args.args_count = 0;
+               child_domain = of_genpd_get_from_provider(&args);
+               if (IS_ERR(child_domain))
+                       continue;
+               if (of_parse_phandle_with_args(np, "power-domains",
+                                        "#power-domain-cells", 0, &args) != 0)
+                       continue;
+               parent_domain = of_genpd_get_from_provider(&args);
+               if (IS_ERR(parent_domain))
+                       continue;
+               if (pm_genpd_add_subdomain(parent_domain, child_domain))
+                       pr_warn("%s failed to add subdomain: %s\n",
+                               parent_domain->name, child_domain->name);
+               else
+                       pr_info("%s has as child subdomain: %s.\n",
+                               parent_domain->name, child_domain->name);
+       }
+       return 0;
+ }
+ core_initcall(exynos4_pm_init_power_domain);