drm/amdgpu: add common gfx_ras_fini function
authorTao Zhou <tao.zhou1@amd.com>
Thu, 12 Sep 2019 09:44:49 +0000 (17:44 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 3 Oct 2019 14:11:02 +0000 (09:11 -0500)
gfx_ras_fini can be shared among all generations of gfx

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

index ed45d7ce5886426a782688dde76f8048bae8b1c2..aaa86a8fb6b685f2944d4d016cb3f9dfd2e2f5eb 100644 (file)
@@ -619,6 +619,21 @@ free:
        return r;
 }
 
+void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
+{
+       if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
+                       adev->gfx.ras_if) {
+               struct ras_common_if *ras_if = adev->gfx.ras_if;
+               struct ras_ih_if ih_info = {
+                       .head = *ras_if,
+                       .cb = amdgpu_gfx_process_ras_data_cb,
+               };
+
+               amdgpu_ras_late_fini(adev, ras_if, &ih_info);
+               kfree(ras_if);
+       }
+}
+
 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
                void *err_data,
                struct amdgpu_iv_entry *entry)
index 179dd4e980b7c276c22eed28c36a8855900791e3..70a940911724e5f7cddc8de5b7922063d1eb87d8 100644 (file)
@@ -360,6 +360,7 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
                             void *ras_ih_info);
+void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
                void *err_data,
                struct amdgpu_iv_entry *entry);
index 920e9cd724d2225d3cbd4aee9a439e03cd332b2e..d9a593bc493220c70256cfc639f4b55f49a8030a 100644 (file)
@@ -2133,19 +2133,7 @@ static int gfx_v9_0_sw_fini(void *handle)
        int i;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
-                       adev->gfx.ras_if) {
-               struct ras_common_if *ras_if = adev->gfx.ras_if;
-               struct ras_ih_if ih_info = {
-                       .head = *ras_if,
-               };
-
-               amdgpu_ras_debugfs_remove(adev, ras_if);
-               amdgpu_ras_sysfs_remove(adev, ras_if);
-               amdgpu_ras_interrupt_remove_handler(adev,  &ih_info);
-               amdgpu_ras_feature_enable(adev, ras_if, 0);
-               kfree(ras_if);
-       }
+       amdgpu_gfx_ras_fini(adev);
 
        for (i = 0; i < adev->gfx.num_gfx_rings; i++)
                amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);