ARM64: zynqmp: Add CANs node for platform
authorMichal Simek <michal.simek@xilinx.com>
Mon, 27 Jul 2015 09:15:38 +0000 (11:15 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 31 Jul 2015 08:46:26 +0000 (10:46 +0200)
Also enable can0 for ep108.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
arch/arm64/boot/dts/xilinx/zynqmp.dtsi

index 53a9e5baa5b82e8d36d5ae45436f68a9e8faf343..b36a2fccf7fcf38afb3736357165770622896212 100644 (file)
        };
 };
 
+&can0 {
+       status = "okay";
+};
+
 &gem0 {
        status = "okay";
        phy-handle = <&phy0>;
index 104f50c2f823e49688001a158d37a899074e30b0..7ff829c1d4bf7d84f20026e2d29f81758db5f61f 100644 (file)
                #size-cells = <1>;
                ranges;
 
+               can0: can@ff060000 {
+                       compatible = "xlnx,zynq-can-1.0";
+                       status = "disabled";
+                       clocks = <&misc_clk &misc_clk>;
+                       clock-names = "can_clk", "pclk";
+                       reg = <0x0 0xff060000 0x1000>;
+                       interrupts = <0 23 4>;
+                       interrupt-parent = <&gic>;
+                       tx-fifo-depth = <0x40>;
+                       rx-fifo-depth = <0x40>;
+               };
+
+               can1: can@ff070000 {
+                       compatible = "xlnx,zynq-can-1.0";
+                       status = "disabled";
+                       clocks = <&misc_clk &misc_clk>;
+                       clock-names = "can_clk", "pclk";
+                       reg = <0x0 0xff070000 0x1000>;
+                       interrupts = <0 24 4>;
+                       interrupt-parent = <&gic>;
+                       tx-fifo-depth = <0x40>;
+                       rx-fifo-depth = <0x40>;
+               };
+
                misc_clk: misc_clk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;