ARM: mx5: Set the DBGEN bit in ARM_GPC register

On i.MX51/i.MX53 it is necessary to set the DBGEN bit in
ARM_GPC register in order to turn on the debug clocks.

The DBGEN bit of ARM_GPC register has the following description
in the i.MX53 Reference Manual:

"This allows the user to manually activate clocks within the debug
system. This register bit directly controls the platform's dbgen_out
output signal which connects to the DAP_SYS to enable all debug clocks.
Once enabled, the clocks cannot be disabled except by asserting the
disable_trace input of the DAP_SYS."

Based on a previous patch from Sebastian Reichel.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 93225db759f899ae17e07004021b21ae8e26d060..423dd76bb6b812e408f106e2367386820b13a8a4 100644 (file)
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -62,6 +62,7 @@ void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
 void imx25_pm_init(void);
 void imx27_pm_init(void);
+void imx5_pmu_init(void);
 
 enum mxc_cpu_pwr_mode {
        WAIT_CLOCKED,           /* wfi only */

diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 4f2d1c772f8559d789b71ca1f83568148153e466..e210bac18840016223fd29c613cdc711de62dcdf 100644 (file)
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -117,3 +117,48 @@ int mx53_revision(void)
        return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx53_revision);
+
+#define ARM_GPC                0x4
+#define DBGEN          BIT(16)
+
+/*
+ * This enables the DBGEN bit in ARM_GPC register, which is
+ * required for accessing some performance counter features.
+ * Technically it is only required while perf is used, but to
+ * keep the source code simple we just enable it all the time
+ * when the kernel configuration allows using the feature.
+ */
+void __init imx5_pmu_init(void)
+{
+       void __iomem *tigerp_base;
+       struct device_node *np;
+       u32 gpc;
+
+       if (!IS_ENABLED(CONFIG_ARM_PMU))
+               return;
+
+       np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
+       if (!np)
+               return;
+
+       if (!of_property_read_bool(np, "secure-reg-access"))
+               goto exit;
+
+       of_node_put(np);
+
+       np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp");
+       if (!np)
+               return;
+
+       tigerp_base = of_iomap(np, 0);
+       if (!tigerp_base)
+               goto exit;
+
+       gpc = readl_relaxed(tigerp_base + ARM_GPC);
+       gpc |= DBGEN;
+       writel_relaxed(gpc, tigerp_base + ARM_GPC);
+       iounmap(tigerp_base);
+exit:
+       of_node_put(np);
+
+}

diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c
index 9d5895ea64f1808bcb2460fcf32b75e4d3f28036..c7169c2f94c4fd8cc018caa790c7b170e778eaf3 100644 (file)
--- a/arch/arm/mach-imx/mach-imx51.c
+++ b/arch/arm/mach-imx/mach-imx51.c
@@ -80,6 +80,7 @@ static void __init imx51_dt_init(void)
        imx51_ipu_mipi_setup();
        imx_src_init();
        imx51_m4if_setup();
+       imx5_pmu_init();
        imx_aips_allow_unprivileged_access("fsl,imx51-aipstz");
 }
 

diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 07c2e8dca494b6b1451b59900e35e00d93c63372..5ec7100737e806269a766b2697eeb2a1f5a4bba4 100644 (file)
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -31,7 +31,7 @@ static void __init imx53_init_early(void)
 static void __init imx53_dt_init(void)
 {
        imx_src_init();
-
+       imx5_pmu_init();
        imx_aips_allow_unprivileged_access("fsl,imx53-aipstz");
 }