x86/PCI: amd: factor out MMCONFIG discovery

This factors out the AMD native MMCONFIG discovery so we can use it
outside amd_bus.c.

amd_bus.c reads AMD MSRs so it can remove the MMCONFIG area from the
PCI resources.  We may also need the MMCONFIG information to work
around BIOS defects in the ACPI MCFG table.

Cc: Borislav Petkov <borislav.petkov@amd.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: stable@kernel.org       # 2.6.34+
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 8e41071704a5b84ec57c6d261410de9f3ffcb5fe..49ad773f4b9f5f4631e4e5bed590c8d6356e4e0f 100644 (file)
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -1,6 +1,7 @@
 #ifndef _ASM_X86_AMD_NB_H
 #define _ASM_X86_AMD_NB_H
 
+#include <linux/ioport.h>
 #include <linux/pci.h>
 
 struct amd_nb_bus_dev_range {
@@ -13,6 +14,7 @@ extern const struct pci_device_id amd_nb_misc_ids[];
 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
 
 extern bool early_is_amd_nb(u32 value);
+extern struct resource *amd_get_mmconfig_range(struct resource *res);
 extern int amd_cache_northbridges(void);
 extern void amd_flush_garts(void);
 extern int amd_numa_init(void);

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 4c39baa8facc25529c7018e53b38de43eab823d9..bae1efe6d515e2c7fc79f1ab10c60a8489afc11f 100644 (file)
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -119,6 +119,37 @@ bool __init early_is_amd_nb(u32 device)
        return false;
 }
 
+struct resource *amd_get_mmconfig_range(struct resource *res)
+{
+       u32 address;
+       u64 base, msr;
+       unsigned segn_busn_bits;
+
+       if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+               return NULL;
+
+       /* assume all cpus from fam10h have mmconfig */
+        if (boot_cpu_data.x86 < 0x10)
+               return NULL;
+
+       address = MSR_FAM10H_MMIO_CONF_BASE;
+       rdmsrl(address, msr);
+
+       /* mmconfig is not enabled */
+       if (!(msr & FAM10H_MMIO_CONF_ENABLE))
+               return NULL;
+
+       base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
+
+       segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
+                        FAM10H_MMIO_CONF_BUSRANGE_MASK;
+
+       res->flags = IORESOURCE_MEM;
+       res->start = base;
+       res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
+       return res;
+}
+
 int amd_get_subcaches(int cpu)
 {
        struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;

diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 7b7a89712d50025b61baa252714e3afcc13d1c43..0567df3890e18932ae53fbb67c118e401ccb278f 100644 (file)
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -30,34 +30,6 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = {
        { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
 };
 
-static u64 __initdata fam10h_mmconf_start;
-static u64 __initdata fam10h_mmconf_end;
-static void __init get_pci_mmcfg_amd_fam10h_range(void)
-{
-       u32 address;
-       u64 base, msr;
-       unsigned segn_busn_bits;
-
-       /* assume all cpus from fam10h have mmconf */
-        if (boot_cpu_data.x86 < 0x10)
-               return;
-
-       address = MSR_FAM10H_MMIO_CONF_BASE;
-       rdmsrl(address, msr);
-
-       /* mmconfig is not enable */
-       if (!(msr & FAM10H_MMIO_CONF_ENABLE))
-               return;
-
-       base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
-
-       segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
-                        FAM10H_MMIO_CONF_BUSRANGE_MASK;
-
-       fam10h_mmconf_start = base;
-       fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
-}
-
 #define RANGE_NUM 16
 
 /**
@@ -85,6 +57,9 @@ static int __init early_fill_mp_bus_info(void)
        u64 val;
        u32 address;
        bool found;
+       struct resource fam10h_mmconf_res, *fam10h_mmconf;
+       u64 fam10h_mmconf_start;
+       u64 fam10h_mmconf_end;
 
        if (!early_pci_allowed())
                return -1;
@@ -211,12 +186,17 @@ static int __init early_fill_mp_bus_info(void)
                subtract_range(range, RANGE_NUM, 0, end);
 
        /* get mmconfig */
-       get_pci_mmcfg_amd_fam10h_range();
+       fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
        /* need to take out mmconf range */
-       if (fam10h_mmconf_end) {
-               printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
+       if (fam10h_mmconf) {
+               printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
+               fam10h_mmconf_start = fam10h_mmconf->start;
+               fam10h_mmconf_end = fam10h_mmconf->end;
                subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
                                 fam10h_mmconf_end + 1);
+       } else {
+               fam10h_mmconf_start = 0;
+               fam10h_mmconf_end = 0;
        }
 
        /* mmio resource */