i2c: designware: add MSCC Ocelot support

The Microsemi Ocelot I2C controller is a designware IP. It also has a
second set of registers to allow tweaking SDA hold time and spike
filtering.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[wsa: made one function static]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index f6cad20a86ffbbed8ddbe4bfa8903feddd713460..5b550ab9a009aec40d34f1ce3f2d4ca3620bb907 100644 (file)
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -225,6 +225,7 @@
 struct dw_i2c_dev {
        struct device           *dev;
        void __iomem            *base;
+       void __iomem            *ext;
        struct completion       cmd_complete;
        struct clk              *clk;
        struct reset_control    *rst;
@@ -279,6 +280,8 @@ struct dw_i2c_dev {
 #define ACCESS_INTR_MASK       0x00000004
 
 #define MODEL_CHERRYTRAIL      0x00000100
+#define MODEL_MSCC_OCELOT      0x00000200
+#define MODEL_MASK             0x00000f00
 
 u32 dw_readl(struct dw_i2c_dev *dev, int offset);
 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);

diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 723892820e2bd793d36d3c339dbc92a61c961e86..a56af235e9a60319595f554fc2db6d5252f30327 100644 (file)
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -157,11 +157,48 @@ static inline int dw_i2c_acpi_configure(struct platform_device *pdev)
 #endif
 
 #ifdef CONFIG_OF
+#define MSCC_ICPU_CFG_TWI_DELAY                0x0
+#define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0)
+#define MSCC_ICPU_CFG_TWI_SPIKE_FILTER 0x4
+
+static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev)
+{
+       writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE,
+              dev->ext + MSCC_ICPU_CFG_TWI_DELAY);
+
+       return 0;
+}
+
+static int dw_i2c_of_configure(struct platform_device *pdev)
+{
+       struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
+       struct resource *mem;
+
+       switch (dev->flags & MODEL_MASK) {
+       case MODEL_MSCC_OCELOT:
+               mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+               dev->ext = devm_ioremap_resource(&pdev->dev, mem);
+               if (!IS_ERR(dev->ext))
+                       dev->set_sda_hold_time = mscc_twi_set_sda_hold_time;
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
 static const struct of_device_id dw_i2c_of_match[] = {
        { .compatible = "snps,designware-i2c", },
+       { .compatible = "mscc,ocelot-i2c", .data = (void *)MODEL_MSCC_OCELOT },
        {},
 };
 MODULE_DEVICE_TABLE(of, dw_i2c_of_match);
+#else
+static inline int dw_i2c_of_configure(struct platform_device *pdev)
+{
+       return -ENODEV;
+}
 #endif
 
 static void i2c_dw_configure_master(struct dw_i2c_dev *dev)
@@ -296,6 +333,9 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
 
        dev->flags |= (uintptr_t)device_get_match_data(&pdev->dev);
 
+       if (pdev->dev.of_node)
+               dw_i2c_of_configure(pdev);
+
        if (has_acpi_companion(&pdev->dev))
                dw_i2c_acpi_configure(pdev);