drm/amdgpu: move umc ras fini to umc block
authorTao Zhou <tao.zhou1@amd.com>
Wed, 18 Sep 2019 09:46:42 +0000 (17:46 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 3 Oct 2019 14:11:02 +0000 (09:11 -0500)
it's more suitable to put umc ras fini in umc block

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

index 17027f771908e755eefd3d44ffd4c41f988bbc57..32687f4c21dc36f4f3a996005b215063127c274e 100644 (file)
@@ -309,17 +309,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
 
 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
 {
-       if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
-                       adev->umc.ras_if) {
-               struct ras_common_if *ras_if = adev->umc.ras_if;
-               struct ras_ih_if ih_info = {
-                       .head = *ras_if,
-                       .cb = amdgpu_umc_process_ras_data_cb,
-               };
-
-               amdgpu_ras_late_fini(adev, ras_if, &ih_info);
-               kfree(ras_if);
-       }
+       amdgpu_umc_ras_fini(adev);
 
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
                        adev->mmhub.ras_if) {
index 08037f086d28743b601698fb3274275417cd6960..7744de1499492ea86cb18012627db22b70717007 100644 (file)
@@ -74,6 +74,21 @@ free:
        return r;
 }
 
+void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
+{
+       if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
+                       adev->umc.ras_if) {
+               struct ras_common_if *ras_if = adev->umc.ras_if;
+               struct ras_ih_if ih_info = {
+                       .head = *ras_if,
+                       .cb = amdgpu_umc_process_ras_data_cb,
+               };
+
+               amdgpu_ras_late_fini(adev, ras_if, &ih_info);
+               kfree(ras_if);
+       }
+}
+
 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
                void *ras_error_status,
                struct amdgpu_iv_entry *entry)
index 8cc9852e99e6af46519be77122d966bfb7cf1b25..3283032a78e50baa7d4febb9d626296116efcf87 100644 (file)
@@ -83,6 +83,7 @@ struct amdgpu_umc {
 };
 
 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
+void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
                void *ras_error_status,
                struct amdgpu_iv_entry *entry);