clk: qcom: msm8960: Fix ce3_src register offset

The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.

Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 63ecd97f379327a2db6f973e4500e0e2d7b38f72..0a0c1f53324903441c45869d05e69eff3263bbd1 100644 (file)
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2753,7 +2753,7 @@ static struct clk_rcg ce3_src = {
        },
        .freq_tbl = clk_tbl_ce3,
        .clkr = {
-               .enable_reg = 0x2c08,
+               .enable_reg = 0x36c0,
                .enable_mask = BIT(7),
                .hw.init = &(struct clk_init_data){
                        .name = "ce3_src",