ARM: dts: dm814x: dra62x: Fix NAND device nodes
authorRoger Quadros <rogerq@ti.com>
Tue, 1 Mar 2016 13:44:47 +0000 (15:44 +0200)
committerTony Lindgren <tony@atomide.com>
Tue, 1 Mar 2016 17:58:09 +0000 (09:58 -0800)
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/dm8148-evm.dts
arch/arm/boot/dts/dm814x.dtsi
arch/arm/boot/dts/dra62x-j5eco-evm.dts

index 862977f5a22a07511f1e2375253992a2a0395c7b..be56c8fc323c40790d87d0a5f51ef0b3cfc03a9b 100644 (file)
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "dm814x.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        model = "DM8148 EVM";
        ranges = <0 0 0x04000000 0x01000000>;   /* CS0: 16MB for NAND */
 
        nand@0,0 {
-               linux,mtd-name= "micron,mt29f2g16aadwp";
+               compatible = "ti,omap2-nand";
                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
+               linux,mtd-name= "micron,mt29f2g16aadwp";
                #address-cells = <1>;
                #size-cells = <1>;
                ti,nand-ecc-opt = "bch8";
index f752ac1d976a517814b40cbc1d4725a3a2372131..4a6ce8c8bf8f857ca09feba084439602bc44b8ff 100644 (file)
                        gpmc,num-waitpins = <2>;
                        #address-cells = <2>;
                        #size-cells = <1>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
                };
        };
 };
index 3937a589d3315765320c8869f96675f403e53966..b0c8144a6e9e781e8034ef88ab90effa3cd2f918 100644 (file)
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "dra62x.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        model = "DRA62x J5 Eco EVM";
        ranges = <0 0 0x04000000 0x01000000>;   /* CS0: 16MB for NAND */
 
        nand@0,0 {
-               linux,mtd-name= "micron,mt29f2g16aadwp";
+               compatible = "ti,omap2-nand";
                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
+               linux,mtd-name= "micron,mt29f2g16aadwp";
                #address-cells = <1>;
                #size-cells = <1>;
                ti,nand-ecc-opt = "bch8";