perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere
authorAndi Kleen <ak@linux.intel.com>
Tue, 1 Mar 2016 22:25:24 +0000 (14:25 -0800)
committerIngo Molnar <mingo@kernel.org>
Tue, 8 Mar 2016 11:19:13 +0000 (12:19 +0100)
commite17dc65328057c00db7e1bfea249c8771a78b30b
tree23522861f78f27380ec062c839d91ee354fc6896
parentb3e6246336a4a329644418a1c66e2c6bed44ef81
perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere

Jiri reported some time ago that some entries in the PEBS data source table
in perf do not agree with the SDM. We investigated and the bits
changed for Sandy Bridge, but the SDM was not updated.

perf already implements the bits correctly for Sandy Bridge
and later. This patch patches it up for Nehalem and Westmere.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: <stable@vger.kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: jolsa@kernel.org
Link: http://lkml.kernel.org/r/1456871124-15985-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/events/intel/core.c
arch/x86/events/intel/ds.c
arch/x86/events/perf_event.h