drm/i915/hsw: Fix workaround for server AUX channel clock divisor
authorJim Bride <jim.bride@linux.intel.com>
Wed, 27 May 2015 17:21:48 +0000 (10:21 -0700)
committerJani Nikula <jani.nikula@intel.com>
Mon, 1 Jun 2015 07:55:51 +0000 (10:55 +0300)
commite058c945e03a629c99606452a6931f632dd28903
tree8634b8c8419493e9c0861b364ecb2403da91c668
parentc65b99f046843d2455aa231747b5a07a999a9f3d
drm/i915/hsw: Fix workaround for server AUX channel clock divisor

According to the HSW b-spec we need to try clock divisors of 63
and 72, each 3 or more times, when attempting DP AUX channel
communication on a server chipset.  This actually wasn't happening
due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit
in status rather than checking that the operation was done and
that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.

[v2] Implemented alternate solution suggested by Jani Nikula.

Cc: stable@vger.kernel.org
Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_dp.c