MIPS: Octeon: Make Octeon GPIO IRQ chip CPU hotplug-aware
authorAlexander Sverdlin <alexander.sverdlin@nsn.com>
Thu, 23 Oct 2014 13:55:04 +0000 (15:55 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 27 Oct 2014 00:43:57 +0000 (01:43 +0100)
commitcf355704d681ce7043c732e732b0a23c27d158a8
treed5a846e4543ada9fb27f3b8adcd911ed3d201e96
parentcac7f2429872d3733dc3f9915857b1691da2eb2f
MIPS: Octeon: Make Octeon GPIO IRQ chip CPU hotplug-aware

Make Octeon GPIO IRQ chip CPU hotplug-aware

Seems that irq_cpu_offline callbacks were forgotten in v1 and v2 CIU
GPIO chips. There is such a callback for octeon_irq_chip_ciu2_gpio,
covering CIU2 chips. Without this callback GPIO IRQs are not being migrated
during core offlining. Patch is tested on Octeon II.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nsn.com>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8201/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/cavium-octeon/octeon-irq.c