KVM: MIPS/T&E: Implement CP0_EBase register
authorJames Hogan <james.hogan@imgtec.com>
Mon, 14 Nov 2016 23:59:27 +0000 (23:59 +0000)
committerJames Hogan <james.hogan@imgtec.com>
Fri, 3 Feb 2017 15:21:30 +0000 (15:21 +0000)
commit7801bbe1bd907a8f8b136fc184583260508febb6
tree657af8c96b0d433c9fe1297756fa2c80bfddb321
parent654229a02456a9af372defb13d1911345360074d
KVM: MIPS/T&E: Implement CP0_EBase register

The CP0_EBase register is a standard feature of MIPS32r2, so we should
always have been implementing it properly. However the register value
was ignored and wasn't exposed to userland.

Fix the emulation of exceptions and interrupts to use the value stored
in guest CP0_EBase, and fix the masks so that the top 3 bits (rather
than the standard 2) are fixed, so that it is always in the guest KSeg0
segment.

Also add CP0_EBASE to the KVM one_reg interface so it can be accessed by
userland, also allowing the CPU number field to be written (which isn't
permitted by the guest).

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Documentation/virtual/kvm/api.txt
arch/mips/include/asm/kvm_host.h
arch/mips/kvm/emulate.c
arch/mips/kvm/interrupt.c
arch/mips/kvm/trap_emul.c