irqchip/gic-v3-its: Add missing cache flushes
authorMarc Zyngier <marc.zyngier@arm.com>
Sun, 13 Sep 2015 11:14:32 +0000 (12:14 +0100)
committerThomas Gleixner <tglx@linutronix.de>
Tue, 15 Sep 2015 15:06:29 +0000 (17:06 +0200)
commit5a9a8915c8888b615521b17d70a4342187eae60b
treec07f12f39a4e6ad2cabacc50d6d6e548406b1ab3
parent12e14066f4835f5ee1ca795f0309415b54c067a9
irqchip/gic-v3-its: Add missing cache flushes

When the ITS is configured for non-cacheable transactions, make sure
that the allocated, zeroed memory is flushed to the Point of
Coherency, allowing the ITS to observe the zeros instead of random
garbage (or even get its own data overwritten by zeros being evicted
from the cache...).

Fixes: 241a386c7dbb "irqchip: gicv3-its: Use non-cacheable accesses when no shareability"
Reported-and-tested-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Pavel Fedin <p.fedin@samsung.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1442142873-20213-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
drivers/irqchip/irq-gic-v3-its.c