drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
authorNavare, Manasi D <manasi.d.navare@intel.com>
Mon, 17 Jul 2017 22:05:22 +0000 (15:05 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 27 Jul 2017 20:07:22 +0000 (22:07 +0200)
commit5846a73f26a1efa45e2c2edd36aa2ed0a6ad380a
treeb2354e36b469f8400d1fc5c78fb7bfec9978e7aa
parent283d6860d64f5091565bf729b0a6d6af14ae6c27
drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence

The condition for setting the Loadgen Select bit of
PORT_TX_DW4 register during DDI Vswing Sequence should be
Bit rate <=6 GHz whereas the existing code checks only
Bit Rate < 6GHz. This patch fixes this condition.
While at it also remove the redundant paranthesis.

Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1500329122-32662-1-git-send-email-manasi.d.navare@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit a8e45a1c42d11597e975f3e5f2fe182f90cdaa7f)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ddi.c