MIPS: Fix cacheinfo overflow
authorJames Hogan <james.hogan@imgtec.com>
Fri, 10 Feb 2017 22:44:03 +0000 (22:44 +0000)
committerJames Hogan <james.hogan@imgtec.com>
Mon, 13 Feb 2017 18:57:34 +0000 (18:57 +0000)
commit4828b5f56f9596f014567ceef0e5c200fb582e13
tree4dcad3dc8b9382b4fea9f9cdcaf53c5890822de9
parentf229454d34e000e714280e767811304e29d96bea
MIPS: Fix cacheinfo overflow

The recently added MIPS cacheinfo support used a macro populate_cache()
to populate the cacheinfo structures depending on which caches are
present. However the macro contains multiple statements without
enclosing them in a do {} while (0) loop, so the L2 and L3 cache
conditionals in populate_cache_leaves() only conditionalised the first
statement in the macro.

This overflows the buffer allocated by detect_cache_attributes(),
resulting in boot failures under QEMU where neither the L2 or L2 caches
are present.

Enclose the macro statements in a do {} while (0) block to keep the
whole macro inside the conditionals.

Fixes: ef462f3b64e9 ("MIPS: Add cacheinfo support")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Justin Chen <justin.chen@broadcom.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: bcm-kernel-feedback-list@broadcom.com
Patchwork: https://patchwork.linux-mips.org/patch/15276/
arch/mips/kernel/cacheinfo.c