lockref: allow relaxed cmpxchg64 variant for lockless updates
authorWill Deacon <will.deacon@arm.com>
Thu, 26 Sep 2013 16:27:00 +0000 (17:27 +0100)
committerLinus Torvalds <torvalds@linux-foundation.org>
Fri, 27 Sep 2013 16:15:01 +0000 (09:15 -0700)
commitd2212b4dce596fee83e5c523400bf084f4cc816c
tree811e0dd289daad8bdebdeef37100587f647f75c1
parent4b97280675f45c1650ee4e388bd711ecbb18c4b4
lockref: allow relaxed cmpxchg64 variant for lockless updates

The 64-bit cmpxchg operation on the lockref is ordered by virtue of
hazarding between the cmpxchg operation and the reference count
manipulation. On weakly ordered memory architectures (such as ARM), it
can be of great benefit to omit the barrier instructions where they are
not needed.

This patch moves the lockless lockref code over to a cmpxchg64_relaxed
operation, which doesn't provide barrier semantics. If the operation
isn't defined, we simply #define it as the usual 64-bit cmpxchg macro.

Cc: Waiman Long <Waiman.Long@hp.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
lib/lockref.c