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(parent: d61b594) | patch
mmc: sdhci: add DDR50 1.8V mode support for BayTrail eMMC Controller
authorMaurice Petallo <mauricex.r.petallo@intel.com>
Tue, 8 Jul 2014 11:11:01 +0000 (19:11 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Thu, 10 Jul 2014 12:58:29 +0000 (14:58 +0200)
commitf25c33724d1512a72554c0ad4cb70b43ba15374e
tree05aef5afbddc4d01c5facc90246293864f44e4dctree | snapshot
parentd61b59461b0cd0106f03e566d537b9072029e059commit | diff
mmc: sdhci: add DDR50 1.8V mode support for BayTrail eMMC Controller

This is to enable DDR50 bus speed mode with 1.8V signaling capability
for BayTrail ACPI and PCI mode eMMC Controller.

Signed-off-by: Maurice Petallo <mauricex.r.petallo@intel.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/sdhci-acpi.c diff | blob | blame | history
drivers/mmc/host/sdhci-pci.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)