drm/radeon: fixes for gfx clockgating on SI
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 15 Aug 2013 20:20:26 +0000 (16:20 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Aug 2013 20:30:50 +0000 (16:30 -0400)
commit5594a558faca933f64277c2033bd724968cd3d89
treef57480adddfb225fefaf435bb2dbe58b100dbdb6
parente16866ecfbfabc546fe8f02fdf4359707f81e81e
drm/radeon: fixes for gfx clockgating on SI

Clockgating requires signalling between the CP and the
RLC to work properly.  Resetting the CP block in the
CP resume code messed up the internal coordination
between the blocks.  Removing the reset allows gfx
clockgating to work properly.  However, when gfx clock
gating is enabled, there is a strange interaction with
dpm which causes the chip to stay in the high performance
level all the time, so leave gfx clockgating disabled
for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/si.c