perf/x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X
authorYan, Zheng <zheng.z.yan@intel.com>
Thu, 18 Jul 2013 09:02:23 +0000 (17:02 +0800)
committerIngo Molnar <mingo@kernel.org>
Mon, 2 Sep 2013 06:42:47 +0000 (08:42 +0200)
commit53ad0447208d3f5897f673ca0b16c776583eedba
tree6966be991efc98edce985854defe71b62ff4f116
parentea79ca0de05198159bcb8a45479122a75e4a5861
perf/x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.

To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event code
for OFFCORE_RSP_N by x86_pmu.extra_regs[N].event.

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1374138144-17278-1-git-send-email-zheng.z.yan@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event_intel.c