perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge
authorVince Weaver <vincent.weaver@maine.edu>
Mon, 14 Jul 2014 19:33:25 +0000 (15:33 -0400)
committerIngo Molnar <mingo@kernel.org>
Wed, 16 Jul 2014 11:18:40 +0000 (13:18 +0200)
commit1996388e9f4e3444db8273bc08d25164d2967c21
treeb04d7178fec737871cc102edb2b201c8d5d3987a
parent1903d50cba54261a6562a476c05085f3d7a54097
perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge

This was discussed back in February:

https://lkml.org/lkml/2014/2/18/956

But I never saw a patch come out of it.

On IvyBridge we share the SandyBridge cache event tables, but the
dTLB-load-miss event is not compatible.  Patch it up after
the fact to the proper DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: http://lkml.kernel.org/r/alpine.DEB.2.11.1407141528200.17214@vincent-weaver-1.umelst.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event_intel.c