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arm64: dts: r8a7795: Add L2 cache-controller nodes
authorGeert Uytterhoeven <geert+renesas@glider.be>
Sat, 16 Jan 2016 14:17:36 +0000 (15:17 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Fri, 5 Feb 2016 09:43:42 +0000 (10:43 +0100)
commit7b337e61a4104d5a0abde1e733916de2208800e6
treee3c0ceee12a7ad506f0c3d4418051462da32f9ectree | snapshot
parenta3fc85e27b7e3c29b30909929bc64737a19fd251commit | diff
arm64: dts: r8a7795: Add L2 cache-controller nodes

Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a7795.dtsi diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)