arm64: Add 16K page size support
authorSuzuki K. Poulose <suzuki.poulose@arm.com>
Mon, 19 Oct 2015 13:19:37 +0000 (14:19 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Mon, 19 Oct 2015 16:55:12 +0000 (17:55 +0100)
commit44eaacf1b8999b15cec89bd9d9cd989da4798d53
tree08d4afb61baa16d41c98fb9035c54d9d788a48dd
parent9d372c9fab34cd8803141871195141995f85c7f7
arm64: Add 16K page size support

This patch turns on the 16K page support in the kernel. We
support 48bit VA (4 level page tables) and 47bit VA (3 level
page tables).

With 16K we can map 128 entries using contiguous bit hint
at level 3 to map 2M using single TLB entry.

TODO: 16K supports 32 contiguous entries at level 2 to get us
1G(which is not yet supported by the infrastructure). That should
be a separate patch altogether.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Steve Capper <steve.capper@linaro.org>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/Kconfig
arch/arm64/include/asm/page.h
arch/arm64/include/asm/sysreg.h
arch/arm64/include/asm/thread_info.h
arch/arm64/kvm/Kconfig
arch/arm64/mm/proc.S