Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next

[linux-2.6-block.git] / include / linux / mlx5 / mlx5_ifc.h

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 3d5d32e5446c3cb33176d48dd1d34b053ce9a447..a528b35a022e0bd1ad840392c7d32a0c44aa3a6f 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -200,6 +200,7 @@ enum {
        MLX5_CMD_OP_QUERY_SQ                      = 0x907,
        MLX5_CMD_OP_CREATE_RQ                     = 0x908,
        MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
+       MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
        MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
        MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
        MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
@@ -294,8 +295,10 @@ struct mlx5_ifc_flow_table_fields_supported_bits {
        u8         inner_tcp_dport[0x1];
        u8         inner_tcp_flags[0x1];
        u8         reserved_at_37[0x9];
+       u8         reserved_at_40[0x1a];
+       u8         bth_dst_qp[0x1];
 
-       u8         reserved_at_40[0x40];
+       u8         reserved_at_5b[0x25];
 };
 
 struct mlx5_ifc_flow_table_prop_layout_bits {
@@ -431,7 +434,9 @@ struct mlx5_ifc_fte_match_set_misc_bits {
        u8         reserved_at_100[0xc];
        u8         inner_ipv6_flow_label[0x14];
 
-       u8         reserved_at_120[0xe0];
+       u8         reserved_at_120[0x28];
+       u8         bth_dst_qp[0x18];
+       u8         reserved_at_160[0xa0];
 };
 
 struct mlx5_ifc_cmd_pas_bits {
@@ -599,7 +604,7 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
        u8         rss_ind_tbl_cap[0x4];
        u8         reg_umr_sq[0x1];
        u8         scatter_fcs[0x1];
-       u8         reserved_at_1a[0x1];
+       u8         enhanced_multi_pkt_send_wqe[0x1];
        u8         tunnel_lso_const_out_ip_id[0x1];
        u8         reserved_at_1c[0x2];
        u8         tunnel_stateless_gre[0x1];
@@ -840,7 +845,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         retransmission_q_counters[0x1];
        u8         reserved_at_183[0x1];
        u8         modify_rq_counter_set_id[0x1];
-       u8         reserved_at_185[0x1];
+       u8         rq_delay_drop[0x1];
        u8         max_qp_cnt[0xa];
        u8         pkey_table_size[0x10];
 
@@ -857,7 +862,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         pcam_reg[0x1];
        u8         local_ca_ack_delay[0x5];
        u8         port_module_event[0x1];
-       u8         reserved_at_1b1[0x1];
+       u8         enhanced_error_q_counters[0x1];
        u8         ports_check[0x1];
        u8         reserved_at_1b3[0x1];
        u8         disable_link_up[0x1];
@@ -873,7 +878,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         max_tc[0x4];
        u8         reserved_at_1d0[0x1];
        u8         dcbx[0x1];
-       u8         reserved_at_1d2[0x3];
+       u8         general_notification_event[0x1];
+       u8         reserved_at_1d3[0x2];
        u8         fpga[0x1];
        u8         rol_s[0x1];
        u8         rol_g[0x1];
@@ -1016,7 +1022,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         log_max_wq_sz[0x5];
 
        u8         nic_vport_change_event[0x1];
-       u8         reserved_at_3e1[0xa];
+       u8         disable_local_lb[0x1];
+       u8         reserved_at_3e2[0x9];
        u8         log_max_vlan_list[0x5];
        u8         reserved_at_3f0[0x3];
        u8         log_max_current_mc_list[0x5];
@@ -1185,7 +1192,8 @@ struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 
        u8         reserved_at_c0[0x12];
        u8         cnp_dscp[0x6];
-       u8         reserved_at_d8[0x5];
+       u8         reserved_at_d8[0x4];
+       u8         cnp_prio_mode[0x1];
        u8         cnp_802p_prio[0x3];
 
        u8         reserved_at_e0[0x720];
@@ -2034,6 +2042,10 @@ enum {
        MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
 };
 
+enum {
+       MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
+};
+
 enum {
        MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
        MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
@@ -2077,7 +2089,8 @@ struct mlx5_ifc_qpc_bits {
        u8         st[0x8];
        u8         reserved_at_10[0x3];
        u8         pm_state[0x2];
-       u8         reserved_at_15[0x7];
+       u8         reserved_at_15[0x3];
+       u8         offload_type[0x4];
        u8         end_padding_mode[0x2];
        u8         reserved_at_1e[0x2];
 
@@ -2457,7 +2470,7 @@ struct mlx5_ifc_sqc_bits {
        u8         cd_master[0x1];
        u8         fre[0x1];
        u8         flush_in_error_en[0x1];
-       u8         reserved_at_4[0x1];
+       u8         allow_multi_pkt_send_wqe[0x1];
        u8         min_wqe_inline_mode[0x3];
        u8         state[0x4];
        u8         reg_umr[0x1];
@@ -2535,7 +2548,7 @@ enum {
 
 struct mlx5_ifc_rqc_bits {
        u8         rlky[0x1];
-       u8         reserved_at_1[0x1];
+       u8         delay_drop_en[0x1];
        u8         scatter_fcs[0x1];
        u8         vsd[0x1];
        u8         mem_rq_type[0x4];
@@ -2582,7 +2595,9 @@ struct mlx5_ifc_rmpc_bits {
 struct mlx5_ifc_nic_vport_context_bits {
        u8         reserved_at_0[0x5];
        u8         min_wqe_inline_mode[0x3];
-       u8         reserved_at_8[0x17];
+       u8         reserved_at_8[0x15];
+       u8         disable_mc_local_lb[0x1];
+       u8         disable_uc_local_lb[0x1];
        u8         roce_en[0x1];
 
        u8         arm_change_event[0x1];
@@ -3020,7 +3035,7 @@ struct mlx5_ifc_xrqc_bits {
 
        struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
 
-       u8         reserved_at_180[0x880];
+       u8         reserved_at_180[0x280];
 
        struct mlx5_ifc_wq_bits wq;
 };
@@ -3967,7 +3982,47 @@ struct mlx5_ifc_query_q_counter_out_bits {
 
        u8         local_ack_timeout_err[0x20];
 
-       u8         reserved_at_320[0x4e0];
+       u8         reserved_at_320[0xa0];
+
+       u8         resp_local_length_error[0x20];
+
+       u8         req_local_length_error[0x20];
+
+       u8         resp_local_qp_error[0x20];
+
+       u8         local_operation_error[0x20];
+
+       u8         resp_local_protection[0x20];
+
+       u8         req_local_protection[0x20];
+
+       u8         resp_cqe_error[0x20];
+
+       u8         req_cqe_error[0x20];
+
+       u8         req_mw_binding[0x20];
+
+       u8         req_bad_response[0x20];
+
+       u8         req_remote_invalid_request[0x20];
+
+       u8         resp_remote_invalid_request[0x20];
+
+       u8         req_remote_access_errors[0x20];
+
+       u8         resp_remote_access_errors[0x20];
+
+       u8         req_remote_operation_errors[0x20];
+
+       u8         req_transport_retries_exceeded[0x20];
+
+       u8         cq_overflow[0x20];
+
+       u8         resp_cqe_flush_error[0x20];
+
+       u8         req_cqe_flush_error[0x20];
+
+       u8         reserved_at_620[0x1e0];
 };
 
 struct mlx5_ifc_query_q_counter_in_bits {
@@ -5248,7 +5303,9 @@ struct mlx5_ifc_modify_nic_vport_context_out_bits {
 };
 
 struct mlx5_ifc_modify_nic_vport_field_select_bits {
-       u8         reserved_at_0[0x16];
+       u8         reserved_at_0[0x14];
+       u8         disable_uc_local_lb[0x1];
+       u8         disable_mc_local_lb[0x1];
        u8         node_guid[0x1];
        u8         port_guid[0x1];
        u8         min_inline[0x1];
@@ -5866,6 +5923,28 @@ struct mlx5_ifc_destroy_rq_in_bits {
        u8         reserved_at_60[0x20];
 };
 
+struct mlx5_ifc_set_delay_drop_params_in_bits {
+       u8         opcode[0x10];
+       u8         reserved_at_10[0x10];
+
+       u8         reserved_at_20[0x10];
+       u8         op_mod[0x10];
+
+       u8         reserved_at_40[0x20];
+
+       u8         reserved_at_60[0x10];
+       u8         delay_drop_timeout[0x10];
+};
+
+struct mlx5_ifc_set_delay_drop_params_out_bits {
+       u8         status[0x8];
+       u8         reserved_at_8[0x18];
+
+       u8         syndrome[0x20];
+
+       u8         reserved_at_40[0x40];
+};
+
 struct mlx5_ifc_destroy_rmp_out_bits {
        u8         status[0x8];
        u8         reserved_at_8[0x18];