Merge tag 'drm-intel-next-2019-05-24' of git://anongit.freedesktop.org/drm/drm-intel...

[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_hdmi.c

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2a4086cf2692aa672f24c7af41af7cee3873b198..a0b98a0178f6f361e3da02687c54b3bf8805561f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -214,7 +214,6 @@ static void g4x_write_infoframe(struct intel_encoder *encoder,
 
        I915_WRITE(VIDEO_DIP_CTL, val);
 
-       mmiowb();
        for (i = 0; i < len; i += 4) {
                I915_WRITE(VIDEO_DIP_DATA, *data);
                data++;
@@ -222,7 +221,6 @@ static void g4x_write_infoframe(struct intel_encoder *encoder,
        /* Write every possible data byte to force correct ECC calculation. */
        for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
                I915_WRITE(VIDEO_DIP_DATA, 0);
-       mmiowb();
 
        val |= g4x_infoframe_enable(type);
        val &= ~VIDEO_DIP_FREQ_MASK;
@@ -289,7 +287,6 @@ static void ibx_write_infoframe(struct intel_encoder *encoder,
 
        I915_WRITE(reg, val);
 
-       mmiowb();
        for (i = 0; i < len; i += 4) {
                I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
                data++;
@@ -297,7 +294,6 @@ static void ibx_write_infoframe(struct intel_encoder *encoder,
        /* Write every possible data byte to force correct ECC calculation. */
        for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
                I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
-       mmiowb();
 
        val |= g4x_infoframe_enable(type);
        val &= ~VIDEO_DIP_FREQ_MASK;
@@ -371,7 +367,6 @@ static void cpt_write_infoframe(struct intel_encoder *encoder,
 
        I915_WRITE(reg, val);
 
-       mmiowb();
        for (i = 0; i < len; i += 4) {
                I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
                data++;
@@ -379,7 +374,6 @@ static void cpt_write_infoframe(struct intel_encoder *encoder,
        /* Write every possible data byte to force correct ECC calculation. */
        for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
                I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
-       mmiowb();
 
        val |= g4x_infoframe_enable(type);
        val &= ~VIDEO_DIP_FREQ_MASK;
@@ -446,7 +440,6 @@ static void vlv_write_infoframe(struct intel_encoder *encoder,
 
        I915_WRITE(reg, val);
 
-       mmiowb();
        for (i = 0; i < len; i += 4) {
                I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
                data++;
@@ -454,7 +447,6 @@ static void vlv_write_infoframe(struct intel_encoder *encoder,
        /* Write every possible data byte to force correct ECC calculation. */
        for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
                I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
-       mmiowb();
 
        val |= g4x_infoframe_enable(type);
        val &= ~VIDEO_DIP_FREQ_MASK;
@@ -521,7 +513,6 @@ static void hsw_write_infoframe(struct intel_encoder *encoder,
        val &= ~hsw_infoframe_enable(type);
        I915_WRITE(ctl_reg, val);
 
-       mmiowb();
        for (i = 0; i < len; i += 4) {
                I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
                                            type, i >> 2), *data);
@@ -531,7 +522,6 @@ static void hsw_write_infoframe(struct intel_encoder *encoder,
        for (; i < data_size; i += 4)
                I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
                                            type, i >> 2), 0);
-       mmiowb();
 
        val |= hsw_infoframe_enable(type);
        I915_WRITE(ctl_reg, val);