Merge tag 'topic/drm-misc-2016-10-24' of git://anongit.freedesktop.org/drm-intel...

[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6c5c36eba6cbb2f998d5c3446d31d10b1f1d615a..4c21d2ec2c51b86206963fd56e63935d6bf70f22 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3408,6 +3408,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
        dst_w--;
        dst_h--;
 
+       intel_crtc->dspaddr_offset = surf_addr;
+
        intel_crtc->adjusted_x = src_x;
        intel_crtc->adjusted_y = src_y;
 
@@ -3629,6 +3631,7 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
                intel_runtime_pm_disable_interrupts(dev_priv);
                intel_runtime_pm_enable_interrupts(dev_priv);
 
+               intel_pps_unlock_regs_wa(dev_priv);
                intel_modeset_init_hw(dev);
 
                spin_lock_irq(&dev_priv->irq_lock);
@@ -9511,6 +9514,24 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
        if (intel_crtc_has_dp_encoder(crtc_state))
                dpll |= DPLL_SDVO_HIGH_SPEED;
 
+       /*
+        * The high speed IO clock is only really required for
+        * SDVO/HDMI/DP, but we also enable it for CRT to make it
+        * possible to share the DPLL between CRT and HDMI. Enabling
+        * the clock needlessly does no real harm, except use up a
+        * bit of power potentially.
+        *
+        * We'll limit this to IVB with 3 pipes, since it has only two
+        * DPLLs and so DPLL sharing is the only way to get three pipes
+        * driving PCH ports at the same time. On SNB we could do this,
+        * and potentially avoid enabling the second DPLL, but it's not
+        * clear if it''s a win or loss power wise. No point in doing
+        * this on ILK at all since it has a fixed DPLL<->pipe mapping.
+        */
+       if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
+           intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
+               dpll |= DPLL_SDVO_HIGH_SPEED;
+
        /* compute bitmask from p1 value */
        dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
        /* also FPA1 */
@@ -14369,8 +14390,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
                 * SKL workaround: bspec recommends we disable the SAGV when we
                 * have more then one pipe enabled
                 */
-               if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))
-                       skl_disable_sagv(dev_priv);
+               if (!intel_can_enable_sagv(state))
+                       intel_disable_sagv(dev_priv);
 
                intel_modeset_verify_disabled(dev);
        }
@@ -14427,9 +14448,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
                intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
        }
 
-       if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
-           skl_can_enable_sagv(state))
-               skl_enable_sagv(dev_priv);
+       if (intel_state->modeset && intel_can_enable_sagv(state))
+               intel_enable_sagv(dev_priv);
 
        drm_atomic_helper_commit_hw_done(state);