drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZE

[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfxhub_v2_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index d605b4963f8aca31b308470b6d910cd1eaa4055e..b4f32d853ca142091635a0f583f1ffcafd0d78c0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -46,21 +46,25 @@ u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
        return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
 }
 
-static void gfxhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev)
+void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+                               uint64_t page_table_base)
 {
-       uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
+       /* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */
+       int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+                       - mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 
+       WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+                               offset * vmid, lower_32_bits(page_table_base));
 
-       WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
-                    lower_32_bits(value));
-
-       WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
-                    upper_32_bits(value));
+       WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+                               offset * vmid, upper_32_bits(page_table_base));
 }
 
 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 {
-       gfxhub_v2_0_init_gart_pt_regs(adev);
+       uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+       gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
 
        WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
                     (u32)(adev->gmc.gart_start >> 12));
@@ -140,7 +144,7 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
        /* XXX for emulation, Refer to closed source code.*/
        tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
                            L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
-       tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
+       tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
        tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
        tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
        WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
@@ -151,6 +155,15 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
        WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
 
        tmp = mmGCVM_L2_CNTL3_DEFAULT;
+       if (adev->gmc.translate_further) {
+               tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
+               tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
+                                   L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+       } else {
+               tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
+               tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
+                                   L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+       }
        WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
 
        tmp = mmGCVM_L2_CNTL4_DEFAULT;
@@ -166,6 +179,8 @@ static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
        tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
        tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
        tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+       tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
+                           RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
        WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
 }
 
@@ -333,7 +348,7 @@ void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
 
 void gfxhub_v2_0_init(struct amdgpu_device *adev)
 {
-       struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
+       struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 
        hub->ctx0_ptb_addr_lo32 =
                SOC15_REG_OFFSET(GC, 0,