2 * VGIC MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/bsearch.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/iodev.h>
19 #include <kvm/arm_vgic.h>
22 #include "vgic-mmio.h"
24 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
25 gpa_t addr, unsigned int len)
30 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
31 gpa_t addr, unsigned int len)
36 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
37 unsigned int len, unsigned long val)
43 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
44 * of the enabled bit, so there is only one function for both here.
46 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
47 gpa_t addr, unsigned int len)
49 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
53 /* Loop over all IRQs affected by this read */
54 for (i = 0; i < len * 8; i++) {
55 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
60 vgic_put_irq(vcpu->kvm, irq);
66 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
67 gpa_t addr, unsigned int len,
70 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
74 for_each_set_bit(i, &val, len * 8) {
75 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
77 spin_lock_irqsave(&irq->irq_lock, flags);
79 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
81 vgic_put_irq(vcpu->kvm, irq);
85 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
86 gpa_t addr, unsigned int len,
89 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
93 for_each_set_bit(i, &val, len * 8) {
94 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
96 spin_lock_irqsave(&irq->irq_lock, flags);
100 spin_unlock_irqrestore(&irq->irq_lock, flags);
101 vgic_put_irq(vcpu->kvm, irq);
105 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
106 gpa_t addr, unsigned int len)
108 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
112 /* Loop over all IRQs affected by this read */
113 for (i = 0; i < len * 8; i++) {
114 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
116 if (irq_is_pending(irq))
119 vgic_put_irq(vcpu->kvm, irq);
125 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
126 gpa_t addr, unsigned int len,
129 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
133 for_each_set_bit(i, &val, len * 8) {
134 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
136 spin_lock_irqsave(&irq->irq_lock, flags);
137 irq->pending_latch = true;
139 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
140 vgic_put_irq(vcpu->kvm, irq);
144 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
145 gpa_t addr, unsigned int len,
148 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
152 for_each_set_bit(i, &val, len * 8) {
153 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
155 spin_lock_irqsave(&irq->irq_lock, flags);
157 irq->pending_latch = false;
159 spin_unlock_irqrestore(&irq->irq_lock, flags);
160 vgic_put_irq(vcpu->kvm, irq);
164 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
165 gpa_t addr, unsigned int len)
167 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
171 /* Loop over all IRQs affected by this read */
172 for (i = 0; i < len * 8; i++) {
173 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
178 vgic_put_irq(vcpu->kvm, irq);
184 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
185 bool new_active_state)
187 struct kvm_vcpu *requester_vcpu;
189 spin_lock_irqsave(&irq->irq_lock, flags);
192 * The vcpu parameter here can mean multiple things depending on how
193 * this function is called; when handling a trap from the kernel it
194 * depends on the GIC version, and these functions are also called as
195 * part of save/restore from userspace.
197 * Therefore, we have to figure out the requester in a reliable way.
199 * When accessing VGIC state from user space, the requester_vcpu is
200 * NULL, which is fine, because we guarantee that no VCPUs are running
201 * when accessing VGIC state from user space so irq->vcpu->cpu is
204 requester_vcpu = kvm_arm_get_running_vcpu();
207 * If this virtual IRQ was written into a list register, we
208 * have to make sure the CPU that runs the VCPU thread has
209 * synced back the LR state to the struct vgic_irq.
211 * As long as the conditions below are true, we know the VCPU thread
212 * may be on its way back from the guest (we kicked the VCPU thread in
213 * vgic_change_active_prepare) and still has to sync back this IRQ,
214 * so we release and re-acquire the spin_lock to let the other thread
217 while (irq->vcpu && /* IRQ may have state in an LR somewhere */
218 irq->vcpu != requester_vcpu && /* Current thread is not the VCPU thread */
219 irq->vcpu->cpu != -1) /* VCPU thread is running */
220 cond_resched_lock(&irq->irq_lock);
222 irq->active = new_active_state;
223 if (new_active_state)
224 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
226 spin_unlock_irqrestore(&irq->irq_lock, flags);
230 * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
231 * is not queued on some running VCPU's LRs, because then the change to the
232 * active state can be overwritten when the VCPU's state is synced coming back
235 * For shared interrupts, we have to stop all the VCPUs because interrupts can
236 * be migrated while we don't hold the IRQ locks and we don't want to be
237 * chasing moving targets.
239 * For private interrupts we don't have to do anything because userspace
240 * accesses to the VGIC state already require all VCPUs to be stopped, and
241 * only the VCPU itself can modify its private interrupts active state, which
242 * guarantees that the VCPU is not running.
244 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
246 if (intid > VGIC_NR_PRIVATE_IRQS)
247 kvm_arm_halt_guest(vcpu->kvm);
250 /* See vgic_change_active_prepare */
251 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
253 if (intid > VGIC_NR_PRIVATE_IRQS)
254 kvm_arm_resume_guest(vcpu->kvm);
257 static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
258 gpa_t addr, unsigned int len,
261 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
264 for_each_set_bit(i, &val, len * 8) {
265 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
266 vgic_mmio_change_active(vcpu, irq, false);
267 vgic_put_irq(vcpu->kvm, irq);
271 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
272 gpa_t addr, unsigned int len,
275 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
277 mutex_lock(&vcpu->kvm->lock);
278 vgic_change_active_prepare(vcpu, intid);
280 __vgic_mmio_write_cactive(vcpu, addr, len, val);
282 vgic_change_active_finish(vcpu, intid);
283 mutex_unlock(&vcpu->kvm->lock);
286 void vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
287 gpa_t addr, unsigned int len,
290 __vgic_mmio_write_cactive(vcpu, addr, len, val);
293 static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
294 gpa_t addr, unsigned int len,
297 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
300 for_each_set_bit(i, &val, len * 8) {
301 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
302 vgic_mmio_change_active(vcpu, irq, true);
303 vgic_put_irq(vcpu->kvm, irq);
307 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
308 gpa_t addr, unsigned int len,
311 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
313 mutex_lock(&vcpu->kvm->lock);
314 vgic_change_active_prepare(vcpu, intid);
316 __vgic_mmio_write_sactive(vcpu, addr, len, val);
318 vgic_change_active_finish(vcpu, intid);
319 mutex_unlock(&vcpu->kvm->lock);
322 void vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
323 gpa_t addr, unsigned int len,
326 __vgic_mmio_write_sactive(vcpu, addr, len, val);
329 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
330 gpa_t addr, unsigned int len)
332 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
336 for (i = 0; i < len; i++) {
337 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
339 val |= (u64)irq->priority << (i * 8);
341 vgic_put_irq(vcpu->kvm, irq);
348 * We currently don't handle changing the priority of an interrupt that
349 * is already pending on a VCPU. If there is a need for this, we would
350 * need to make this VCPU exit and re-evaluate the priorities, potentially
351 * leading to this interrupt getting presented now to the guest (if it has
352 * been masked by the priority mask before).
354 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
355 gpa_t addr, unsigned int len,
358 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
362 for (i = 0; i < len; i++) {
363 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
365 spin_lock_irqsave(&irq->irq_lock, flags);
366 /* Narrow the priority range to what we actually support */
367 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
368 spin_unlock_irqrestore(&irq->irq_lock, flags);
370 vgic_put_irq(vcpu->kvm, irq);
374 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
375 gpa_t addr, unsigned int len)
377 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
381 for (i = 0; i < len * 4; i++) {
382 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
384 if (irq->config == VGIC_CONFIG_EDGE)
385 value |= (2U << (i * 2));
387 vgic_put_irq(vcpu->kvm, irq);
393 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
394 gpa_t addr, unsigned int len,
397 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
401 for (i = 0; i < len * 4; i++) {
402 struct vgic_irq *irq;
405 * The configuration cannot be changed for SGIs in general,
406 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
407 * code relies on PPIs being level triggered, so we also
408 * make them read-only here.
410 if (intid + i < VGIC_NR_PRIVATE_IRQS)
413 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
414 spin_lock_irqsave(&irq->irq_lock, flags);
416 if (test_bit(i * 2 + 1, &val))
417 irq->config = VGIC_CONFIG_EDGE;
419 irq->config = VGIC_CONFIG_LEVEL;
421 spin_unlock_irqrestore(&irq->irq_lock, flags);
422 vgic_put_irq(vcpu->kvm, irq);
426 u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
430 int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
432 for (i = 0; i < 32; i++) {
433 struct vgic_irq *irq;
435 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
438 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
439 if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
442 vgic_put_irq(vcpu->kvm, irq);
448 void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
452 int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
455 for (i = 0; i < 32; i++) {
456 struct vgic_irq *irq;
459 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
462 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
465 * Line level is set irrespective of irq type
466 * (level or edge) to avoid dependency that VM should
467 * restore irq config before line level.
469 new_level = !!(val & (1U << i));
470 spin_lock_irqsave(&irq->irq_lock, flags);
471 irq->line_level = new_level;
473 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
475 spin_unlock_irqrestore(&irq->irq_lock, flags);
477 vgic_put_irq(vcpu->kvm, irq);
481 static int match_region(const void *key, const void *elt)
483 const unsigned int offset = (unsigned long)key;
484 const struct vgic_register_region *region = elt;
486 if (offset < region->reg_offset)
489 if (offset >= region->reg_offset + region->len)
495 const struct vgic_register_region *
496 vgic_find_mmio_region(const struct vgic_register_region *regions,
497 int nr_regions, unsigned int offset)
499 return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
500 sizeof(regions[0]), match_region);
503 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
505 if (kvm_vgic_global_state.type == VGIC_V2)
506 vgic_v2_set_vmcr(vcpu, vmcr);
508 vgic_v3_set_vmcr(vcpu, vmcr);
511 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
513 if (kvm_vgic_global_state.type == VGIC_V2)
514 vgic_v2_get_vmcr(vcpu, vmcr);
516 vgic_v3_get_vmcr(vcpu, vmcr);
520 * kvm_mmio_read_buf() returns a value in a format where it can be converted
521 * to a byte array and be directly observed as the guest wanted it to appear
522 * in memory if it had done the store itself, which is LE for the GIC, as the
523 * guest knows the GIC is always LE.
525 * We convert this value to the CPUs native format to deal with it as a data
528 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
530 unsigned long data = kvm_mmio_read_buf(val, len);
536 return le16_to_cpu(data);
538 return le32_to_cpu(data);
540 return le64_to_cpu(data);
545 * kvm_mmio_write_buf() expects a value in a format such that if converted to
546 * a byte array it is observed as the guest would see it if it could perform
547 * the load directly. Since the GIC is LE, and the guest knows this, the
548 * guest expects a value in little endian format.
550 * We convert the data value from the CPUs native format to LE so that the
551 * value is returned in the proper format.
553 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
560 data = cpu_to_le16(data);
563 data = cpu_to_le32(data);
566 data = cpu_to_le64(data);
569 kvm_mmio_write_buf(buf, len, data);
573 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
575 return container_of(dev, struct vgic_io_device, dev);
578 static bool check_region(const struct kvm *kvm,
579 const struct vgic_register_region *region,
582 int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
586 flags = VGIC_ACCESS_8bit;
589 flags = VGIC_ACCESS_32bit;
592 flags = VGIC_ACCESS_64bit;
598 if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
599 if (!region->bits_per_irq)
602 /* Do we access a non-allocated IRQ? */
603 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
609 const struct vgic_register_region *
610 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
613 const struct vgic_register_region *region;
615 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
616 addr - iodev->base_addr);
617 if (!region || !check_region(vcpu->kvm, region, addr, len))
623 static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
624 gpa_t addr, u32 *val)
626 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
627 const struct vgic_register_region *region;
628 struct kvm_vcpu *r_vcpu;
630 region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
636 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
637 if (region->uaccess_read)
638 *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
640 *val = region->read(r_vcpu, addr, sizeof(u32));
645 static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
646 gpa_t addr, const u32 *val)
648 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
649 const struct vgic_register_region *region;
650 struct kvm_vcpu *r_vcpu;
652 region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
656 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
657 if (region->uaccess_write)
658 region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
660 region->write(r_vcpu, addr, sizeof(u32), *val);
666 * Userland access to VGIC registers.
668 int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
669 bool is_write, int offset, u32 *val)
672 return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
674 return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
677 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
678 gpa_t addr, int len, void *val)
680 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
681 const struct vgic_register_region *region;
682 unsigned long data = 0;
684 region = vgic_get_mmio_region(vcpu, iodev, addr, len);
690 switch (iodev->iodev_type) {
692 data = region->read(vcpu, addr, len);
695 data = region->read(vcpu, addr, len);
698 data = region->read(iodev->redist_vcpu, addr, len);
701 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
705 vgic_data_host_to_mmio_bus(val, len, data);
709 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
710 gpa_t addr, int len, const void *val)
712 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
713 const struct vgic_register_region *region;
714 unsigned long data = vgic_data_mmio_bus_to_host(val, len);
716 region = vgic_get_mmio_region(vcpu, iodev, addr, len);
720 switch (iodev->iodev_type) {
722 region->write(vcpu, addr, len, data);
725 region->write(vcpu, addr, len, data);
728 region->write(iodev->redist_vcpu, addr, len, data);
731 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
738 struct kvm_io_device_ops kvm_io_gic_ops = {
739 .read = dispatch_mmio_read,
740 .write = dispatch_mmio_write,
743 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
746 struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
752 len = vgic_v2_init_dist_iodev(io_device);
755 len = vgic_v3_init_dist_iodev(io_device);
761 io_device->base_addr = dist_base_address;
762 io_device->iodev_type = IODEV_DIST;
763 io_device->redist_vcpu = NULL;
765 mutex_lock(&kvm->slots_lock);
766 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
767 len, &io_device->dev);
768 mutex_unlock(&kvm->slots_lock);