virt/kvm/arm/vgic/vgic-mmio.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * VGIC MMIO handling functions
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/bsearch.h>
   8 #include <linux/kvm.h>
   9 #include <linux/kvm_host.h>
  10 #include <kvm/iodev.h>
  11 #include <kvm/arm_arch_timer.h>
  12 #include <kvm/arm_vgic.h>
  13
  14 #include "vgic.h"
  15 #include "vgic-mmio.h"
  16
  17 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
  18                                  gpa_t addr, unsigned int len)
  19 {
  20         return 0;
  21 }
  22
  23 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
  24                                  gpa_t addr, unsigned int len)
  25 {
  26         return -1UL;
  27 }
  28
  29 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  30                         unsigned int len, unsigned long val)
  31 {
  32         /* Ignore */
  33 }
  34
  35 int vgic_mmio_uaccess_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  36                                unsigned int len, unsigned long val)
  37 {
  38         /* Ignore */
  39         return 0;
  40 }
  41
  42 unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu,
  43                                    gpa_t addr, unsigned int len)
  44 {
  45         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  46         u32 value = 0;
  47         int i;
  48
  49         /* Loop over all IRQs affected by this read */
  50         for (i = 0; i < len * 8; i++) {
  51                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  52
  53                 if (irq->group)
  54                         value |= BIT(i);
  55
  56                 vgic_put_irq(vcpu->kvm, irq);
  57         }
  58
  59         return value;
  60 }
  61
  62 void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
  63                            unsigned int len, unsigned long val)
  64 {
  65         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  66         int i;
  67         unsigned long flags;
  68
  69         for (i = 0; i < len * 8; i++) {
  70                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  71
  72                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
  73                 irq->group = !!(val & BIT(i));
  74                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
  75
  76                 vgic_put_irq(vcpu->kvm, irq);
  77         }
  78 }
  79
  80 /*
  81  * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
  82  * of the enabled bit, so there is only one function for both here.
  83  */
  84 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
  85                                     gpa_t addr, unsigned int len)
  86 {
  87         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  88         u32 value = 0;
  89         int i;
  90
  91         /* Loop over all IRQs affected by this read */
  92         for (i = 0; i < len * 8; i++) {
  93                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  94
  95                 if (irq->enabled)
  96                         value |= (1U << i);
  97
  98                 vgic_put_irq(vcpu->kvm, irq);
  99         }
 100
 101         return value;
 102 }
 103
 104 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
 105                              gpa_t addr, unsigned int len,
 106                              unsigned long val)
 107 {
 108         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 109         int i;
 110         unsigned long flags;
 111
 112         for_each_set_bit(i, &val, len * 8) {
 113                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 114
 115                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 116                 irq->enabled = true;
 117                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 118
 119                 vgic_put_irq(vcpu->kvm, irq);
 120         }
 121 }
 122
 123 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
 124                              gpa_t addr, unsigned int len,
 125                              unsigned long val)
 126 {
 127         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 128         int i;
 129         unsigned long flags;
 130
 131         for_each_set_bit(i, &val, len * 8) {
 132                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 133
 134                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 135
 136                 irq->enabled = false;
 137
 138                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 139                 vgic_put_irq(vcpu->kvm, irq);
 140         }
 141 }
 142
 143 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 144                                      gpa_t addr, unsigned int len)
 145 {
 146         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 147         u32 value = 0;
 148         int i;
 149
 150         /* Loop over all IRQs affected by this read */
 151         for (i = 0; i < len * 8; i++) {
 152                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 153                 unsigned long flags;
 154
 155                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 156                 if (irq_is_pending(irq))
 157                         value |= (1U << i);
 158                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 159
 160                 vgic_put_irq(vcpu->kvm, irq);
 161         }
 162
 163         return value;
 164 }
 165
 166 /*
 167  * This function will return the VCPU that performed the MMIO access and
 168  * trapped from within the VM, and will return NULL if this is a userspace
 169  * access.
 170  *
 171  * We can disable preemption locally around accessing the per-CPU variable,
 172  * and use the resolved vcpu pointer after enabling preemption again, because
 173  * even if the current thread is migrated to another CPU, reading the per-CPU
 174  * value later will give us the same value as we update the per-CPU variable
 175  * in the preempt notifier handlers.
 176  */
 177 static struct kvm_vcpu *vgic_get_mmio_requester_vcpu(void)
 178 {
 179         struct kvm_vcpu *vcpu;
 180
 181         preempt_disable();
 182         vcpu = kvm_arm_get_running_vcpu();
 183         preempt_enable();
 184         return vcpu;
 185 }
 186
 187 /* Must be called with irq->irq_lock held */
 188 static void vgic_hw_irq_spending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 189                                  bool is_uaccess)
 190 {
 191         if (is_uaccess)
 192                 return;
 193
 194         irq->pending_latch = true;
 195         vgic_irq_set_phys_active(irq, true);
 196 }
 197
 198 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
 199                               gpa_t addr, unsigned int len,
 200                               unsigned long val)
 201 {
 202         bool is_uaccess = !vgic_get_mmio_requester_vcpu();
 203         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 204         int i;
 205         unsigned long flags;
 206
 207         for_each_set_bit(i, &val, len * 8) {
 208                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 209
 210                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 211                 if (irq->hw)
 212                         vgic_hw_irq_spending(vcpu, irq, is_uaccess);
 213                 else
 214                         irq->pending_latch = true;
 215                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 216                 vgic_put_irq(vcpu->kvm, irq);
 217         }
 218 }
 219
 220 /* Must be called with irq->irq_lock held */
 221 static void vgic_hw_irq_cpending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 222                                  bool is_uaccess)
 223 {
 224         if (is_uaccess)
 225                 return;
 226
 227         irq->pending_latch = false;
 228
 229         /*
 230          * We don't want the guest to effectively mask the physical
 231          * interrupt by doing a write to SPENDR followed by a write to
 232          * CPENDR for HW interrupts, so we clear the active state on
 233          * the physical side if the virtual interrupt is not active.
 234          * This may lead to taking an additional interrupt on the
 235          * host, but that should not be a problem as the worst that
 236          * can happen is an additional vgic injection.  We also clear
 237          * the pending state to maintain proper semantics for edge HW
 238          * interrupts.
 239          */
 240         vgic_irq_set_phys_pending(irq, false);
 241         if (!irq->active)
 242                 vgic_irq_set_phys_active(irq, false);
 243 }
 244
 245 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
 246                               gpa_t addr, unsigned int len,
 247                               unsigned long val)
 248 {
 249         bool is_uaccess = !vgic_get_mmio_requester_vcpu();
 250         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 251         int i;
 252         unsigned long flags;
 253
 254         for_each_set_bit(i, &val, len * 8) {
 255                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 256
 257                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 258
 259                 if (irq->hw)
 260                         vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
 261                 else
 262                         irq->pending_latch = false;
 263
 264                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 265                 vgic_put_irq(vcpu->kvm, irq);
 266         }
 267 }
 268
 269 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
 270                                     gpa_t addr, unsigned int len)
 271 {
 272         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 273         u32 value = 0;
 274         int i;
 275
 276         /* Loop over all IRQs affected by this read */
 277         for (i = 0; i < len * 8; i++) {
 278                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 279
 280                 if (irq->active)
 281                         value |= (1U << i);
 282
 283                 vgic_put_irq(vcpu->kvm, irq);
 284         }
 285
 286         return value;
 287 }
 288
 289 /* Must be called with irq->irq_lock held */
 290 static void vgic_hw_irq_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 291                                       bool active, bool is_uaccess)
 292 {
 293         if (is_uaccess)
 294                 return;
 295
 296         irq->active = active;
 297         vgic_irq_set_phys_active(irq, active);
 298 }
 299
 300 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 301                                     bool active)
 302 {
 303         unsigned long flags;
 304         struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();
 305
 306         raw_spin_lock_irqsave(&irq->irq_lock, flags);
 307
 308         if (irq->hw) {
 309                 vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
 310         } else {
 311                 u32 model = vcpu->kvm->arch.vgic.vgic_model;
 312                 u8 active_source;
 313
 314                 irq->active = active;
 315
 316                 /*
 317                  * The GICv2 architecture indicates that the source CPUID for
 318                  * an SGI should be provided during an EOI which implies that
 319                  * the active state is stored somewhere, but at the same time
 320                  * this state is not architecturally exposed anywhere and we
 321                  * have no way of knowing the right source.
 322                  *
 323                  * This may lead to a VCPU not being able to receive
 324                  * additional instances of a particular SGI after migration
 325                  * for a GICv2 VM on some GIC implementations.  Oh well.
 326                  */
 327                 active_source = (requester_vcpu) ? requester_vcpu->vcpu_id : 0;
 328
 329                 if (model == KVM_DEV_TYPE_ARM_VGIC_V2 &&
 330                     active && vgic_irq_is_sgi(irq->intid))
 331                         irq->active_source = active_source;
 332         }
 333
 334         if (irq->active)
 335                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 336         else
 337                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 338 }
 339
 340 /*
 341  * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
 342  * is not queued on some running VCPU's LRs, because then the change to the
 343  * active state can be overwritten when the VCPU's state is synced coming back
 344  * from the guest.
 345  *
 346  * For shared interrupts, we have to stop all the VCPUs because interrupts can
 347  * be migrated while we don't hold the IRQ locks and we don't want to be
 348  * chasing moving targets.
 349  *
 350  * For private interrupts we don't have to do anything because userspace
 351  * accesses to the VGIC state already require all VCPUs to be stopped, and
 352  * only the VCPU itself can modify its private interrupts active state, which
 353  * guarantees that the VCPU is not running.
 354  */
 355 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
 356 {
 357         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
 358             intid > VGIC_NR_PRIVATE_IRQS)
 359                 kvm_arm_halt_guest(vcpu->kvm);
 360 }
 361
 362 /* See vgic_change_active_prepare */
 363 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
 364 {
 365         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
 366             intid > VGIC_NR_PRIVATE_IRQS)
 367                 kvm_arm_resume_guest(vcpu->kvm);
 368 }
 369
 370 static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 371                                       gpa_t addr, unsigned int len,
 372                                       unsigned long val)
 373 {
 374         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 375         int i;
 376
 377         for_each_set_bit(i, &val, len * 8) {
 378                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 379                 vgic_mmio_change_active(vcpu, irq, false);
 380                 vgic_put_irq(vcpu->kvm, irq);
 381         }
 382 }
 383
 384 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 385                              gpa_t addr, unsigned int len,
 386                              unsigned long val)
 387 {
 388         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 389
 390         mutex_lock(&vcpu->kvm->lock);
 391         vgic_change_active_prepare(vcpu, intid);
 392
 393         __vgic_mmio_write_cactive(vcpu, addr, len, val);
 394
 395         vgic_change_active_finish(vcpu, intid);
 396         mutex_unlock(&vcpu->kvm->lock);
 397 }
 398
 399 int vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
 400                                      gpa_t addr, unsigned int len,
 401                                      unsigned long val)
 402 {
 403         __vgic_mmio_write_cactive(vcpu, addr, len, val);
 404         return 0;
 405 }
 406
 407 static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 408                                       gpa_t addr, unsigned int len,
 409                                       unsigned long val)
 410 {
 411         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 412         int i;
 413
 414         for_each_set_bit(i, &val, len * 8) {
 415                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 416                 vgic_mmio_change_active(vcpu, irq, true);
 417                 vgic_put_irq(vcpu->kvm, irq);
 418         }
 419 }
 420
 421 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 422                              gpa_t addr, unsigned int len,
 423                              unsigned long val)
 424 {
 425         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 426
 427         mutex_lock(&vcpu->kvm->lock);
 428         vgic_change_active_prepare(vcpu, intid);
 429
 430         __vgic_mmio_write_sactive(vcpu, addr, len, val);
 431
 432         vgic_change_active_finish(vcpu, intid);
 433         mutex_unlock(&vcpu->kvm->lock);
 434 }
 435
 436 int vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
 437                                      gpa_t addr, unsigned int len,
 438                                      unsigned long val)
 439 {
 440         __vgic_mmio_write_sactive(vcpu, addr, len, val);
 441         return 0;
 442 }
 443
 444 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
 445                                       gpa_t addr, unsigned int len)
 446 {
 447         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 448         int i;
 449         u64 val = 0;
 450
 451         for (i = 0; i < len; i++) {
 452                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 453
 454                 val |= (u64)irq->priority << (i * 8);
 455
 456                 vgic_put_irq(vcpu->kvm, irq);
 457         }
 458
 459         return val;
 460 }
 461
 462 /*
 463  * We currently don't handle changing the priority of an interrupt that
 464  * is already pending on a VCPU. If there is a need for this, we would
 465  * need to make this VCPU exit and re-evaluate the priorities, potentially
 466  * leading to this interrupt getting presented now to the guest (if it has
 467  * been masked by the priority mask before).
 468  */
 469 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
 470                               gpa_t addr, unsigned int len,
 471                               unsigned long val)
 472 {
 473         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 474         int i;
 475         unsigned long flags;
 476
 477         for (i = 0; i < len; i++) {
 478                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 479
 480                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 481                 /* Narrow the priority range to what we actually support */
 482                 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
 483                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 484
 485                 vgic_put_irq(vcpu->kvm, irq);
 486         }
 487 }
 488
 489 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
 490                                     gpa_t addr, unsigned int len)
 491 {
 492         u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
 493         u32 value = 0;
 494         int i;
 495
 496         for (i = 0; i < len * 4; i++) {
 497                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 498
 499                 if (irq->config == VGIC_CONFIG_EDGE)
 500                         value |= (2U << (i * 2));
 501
 502                 vgic_put_irq(vcpu->kvm, irq);
 503         }
 504
 505         return value;
 506 }
 507
 508 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
 509                             gpa_t addr, unsigned int len,
 510                             unsigned long val)
 511 {
 512         u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
 513         int i;
 514         unsigned long flags;
 515
 516         for (i = 0; i < len * 4; i++) {
 517                 struct vgic_irq *irq;
 518
 519                 /*
 520                  * The configuration cannot be changed for SGIs in general,
 521                  * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
 522                  * code relies on PPIs being level triggered, so we also
 523                  * make them read-only here.
 524                  */
 525                 if (intid + i < VGIC_NR_PRIVATE_IRQS)
 526                         continue;
 527
 528                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 529                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 530
 531                 if (test_bit(i * 2 + 1, &val))
 532                         irq->config = VGIC_CONFIG_EDGE;
 533                 else
 534                         irq->config = VGIC_CONFIG_LEVEL;
 535
 536                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 537                 vgic_put_irq(vcpu->kvm, irq);
 538         }
 539 }
 540
 541 u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
 542 {
 543         int i;
 544         u64 val = 0;
 545         int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 546
 547         for (i = 0; i < 32; i++) {
 548                 struct vgic_irq *irq;
 549
 550                 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
 551                         continue;
 552
 553                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 554                 if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
 555                         val |= (1U << i);
 556
 557                 vgic_put_irq(vcpu->kvm, irq);
 558         }
 559
 560         return val;
 561 }
 562
 563 void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
 564                                     const u64 val)
 565 {
 566         int i;
 567         int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 568         unsigned long flags;
 569
 570         for (i = 0; i < 32; i++) {
 571                 struct vgic_irq *irq;
 572                 bool new_level;
 573
 574                 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
 575                         continue;
 576
 577                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 578
 579                 /*
 580                  * Line level is set irrespective of irq type
 581                  * (level or edge) to avoid dependency that VM should
 582                  * restore irq config before line level.
 583                  */
 584                 new_level = !!(val & (1U << i));
 585                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 586                 irq->line_level = new_level;
 587                 if (new_level)
 588                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 589                 else
 590                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 591
 592                 vgic_put_irq(vcpu->kvm, irq);
 593         }
 594 }
 595
 596 static int match_region(const void *key, const void *elt)
 597 {
 598         const unsigned int offset = (unsigned long)key;
 599         const struct vgic_register_region *region = elt;
 600
 601         if (offset < region->reg_offset)
 602                 return -1;
 603
 604         if (offset >= region->reg_offset + region->len)
 605                 return 1;
 606
 607         return 0;
 608 }
 609
 610 const struct vgic_register_region *
 611 vgic_find_mmio_region(const struct vgic_register_region *regions,
 612                       int nr_regions, unsigned int offset)
 613 {
 614         return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
 615                        sizeof(regions[0]), match_region);
 616 }
 617
 618 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 619 {
 620         if (kvm_vgic_global_state.type == VGIC_V2)
 621                 vgic_v2_set_vmcr(vcpu, vmcr);
 622         else
 623                 vgic_v3_set_vmcr(vcpu, vmcr);
 624 }
 625
 626 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 627 {
 628         if (kvm_vgic_global_state.type == VGIC_V2)
 629                 vgic_v2_get_vmcr(vcpu, vmcr);
 630         else
 631                 vgic_v3_get_vmcr(vcpu, vmcr);
 632 }
 633
 634 /*
 635  * kvm_mmio_read_buf() returns a value in a format where it can be converted
 636  * to a byte array and be directly observed as the guest wanted it to appear
 637  * in memory if it had done the store itself, which is LE for the GIC, as the
 638  * guest knows the GIC is always LE.
 639  *
 640  * We convert this value to the CPUs native format to deal with it as a data
 641  * value.
 642  */
 643 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
 644 {
 645         unsigned long data = kvm_mmio_read_buf(val, len);
 646
 647         switch (len) {
 648         case 1:
 649                 return data;
 650         case 2:
 651                 return le16_to_cpu(data);
 652         case 4:
 653                 return le32_to_cpu(data);
 654         default:
 655                 return le64_to_cpu(data);
 656         }
 657 }
 658
 659 /*
 660  * kvm_mmio_write_buf() expects a value in a format such that if converted to
 661  * a byte array it is observed as the guest would see it if it could perform
 662  * the load directly.  Since the GIC is LE, and the guest knows this, the
 663  * guest expects a value in little endian format.
 664  *
 665  * We convert the data value from the CPUs native format to LE so that the
 666  * value is returned in the proper format.
 667  */
 668 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
 669                                 unsigned long data)
 670 {
 671         switch (len) {
 672         case 1:
 673                 break;
 674         case 2:
 675                 data = cpu_to_le16(data);
 676                 break;
 677         case 4:
 678                 data = cpu_to_le32(data);
 679                 break;
 680         default:
 681                 data = cpu_to_le64(data);
 682         }
 683
 684         kvm_mmio_write_buf(buf, len, data);
 685 }
 686
 687 static
 688 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
 689 {
 690         return container_of(dev, struct vgic_io_device, dev);
 691 }
 692
 693 static bool check_region(const struct kvm *kvm,
 694                          const struct vgic_register_region *region,
 695                          gpa_t addr, int len)
 696 {
 697         int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 698
 699         switch (len) {
 700         case sizeof(u8):
 701                 flags = VGIC_ACCESS_8bit;
 702                 break;
 703         case sizeof(u32):
 704                 flags = VGIC_ACCESS_32bit;
 705                 break;
 706         case sizeof(u64):
 707                 flags = VGIC_ACCESS_64bit;
 708                 break;
 709         default:
 710                 return false;
 711         }
 712
 713         if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
 714                 if (!region->bits_per_irq)
 715                         return true;
 716
 717                 /* Do we access a non-allocated IRQ? */
 718                 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
 719         }
 720
 721         return false;
 722 }
 723
 724 const struct vgic_register_region *
 725 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
 726                      gpa_t addr, int len)
 727 {
 728         const struct vgic_register_region *region;
 729
 730         region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
 731                                        addr - iodev->base_addr);
 732         if (!region || !check_region(vcpu->kvm, region, addr, len))
 733                 return NULL;
 734
 735         return region;
 736 }
 737
 738 static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 739                              gpa_t addr, u32 *val)
 740 {
 741         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 742         const struct vgic_register_region *region;
 743         struct kvm_vcpu *r_vcpu;
 744
 745         region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
 746         if (!region) {
 747                 *val = 0;
 748                 return 0;
 749         }
 750
 751         r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
 752         if (region->uaccess_read)
 753                 *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
 754         else
 755                 *val = region->read(r_vcpu, addr, sizeof(u32));
 756
 757         return 0;
 758 }
 759
 760 static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 761                               gpa_t addr, const u32 *val)
 762 {
 763         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 764         const struct vgic_register_region *region;
 765         struct kvm_vcpu *r_vcpu;
 766
 767         region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
 768         if (!region)
 769                 return 0;
 770
 771         r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
 772         if (region->uaccess_write)
 773                 return region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
 774
 775         region->write(r_vcpu, addr, sizeof(u32), *val);
 776         return 0;
 777 }
 778
 779 /*
 780  * Userland access to VGIC registers.
 781  */
 782 int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
 783                  bool is_write, int offset, u32 *val)
 784 {
 785         if (is_write)
 786                 return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
 787         else
 788                 return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
 789 }
 790
 791 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 792                               gpa_t addr, int len, void *val)
 793 {
 794         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 795         const struct vgic_register_region *region;
 796         unsigned long data = 0;
 797
 798         region = vgic_get_mmio_region(vcpu, iodev, addr, len);
 799         if (!region) {
 800                 memset(val, 0, len);
 801                 return 0;
 802         }
 803
 804         switch (iodev->iodev_type) {
 805         case IODEV_CPUIF:
 806                 data = region->read(vcpu, addr, len);
 807                 break;
 808         case IODEV_DIST:
 809                 data = region->read(vcpu, addr, len);
 810                 break;
 811         case IODEV_REDIST:
 812                 data = region->read(iodev->redist_vcpu, addr, len);
 813                 break;
 814         case IODEV_ITS:
 815                 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
 816                 break;
 817         }
 818
 819         vgic_data_host_to_mmio_bus(val, len, data);
 820         return 0;
 821 }
 822
 823 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 824                                gpa_t addr, int len, const void *val)
 825 {
 826         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 827         const struct vgic_register_region *region;
 828         unsigned long data = vgic_data_mmio_bus_to_host(val, len);
 829
 830         region = vgic_get_mmio_region(vcpu, iodev, addr, len);
 831         if (!region)
 832                 return 0;
 833
 834         switch (iodev->iodev_type) {
 835         case IODEV_CPUIF:
 836                 region->write(vcpu, addr, len, data);
 837                 break;
 838         case IODEV_DIST:
 839                 region->write(vcpu, addr, len, data);
 840                 break;
 841         case IODEV_REDIST:
 842                 region->write(iodev->redist_vcpu, addr, len, data);
 843                 break;
 844         case IODEV_ITS:
 845                 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
 846                 break;
 847         }
 848
 849         return 0;
 850 }
 851
 852 struct kvm_io_device_ops kvm_io_gic_ops = {
 853         .read = dispatch_mmio_read,
 854         .write = dispatch_mmio_write,
 855 };
 856
 857 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
 858                              enum vgic_type type)
 859 {
 860         struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
 861         int ret = 0;
 862         unsigned int len;
 863
 864         switch (type) {
 865         case VGIC_V2:
 866                 len = vgic_v2_init_dist_iodev(io_device);
 867                 break;
 868         case VGIC_V3:
 869                 len = vgic_v3_init_dist_iodev(io_device);
 870                 break;
 871         default:
 872                 BUG_ON(1);
 873         }
 874
 875         io_device->base_addr = dist_base_address;
 876         io_device->iodev_type = IODEV_DIST;
 877         io_device->redist_vcpu = NULL;
 878
 879         mutex_lock(&kvm->slots_lock);
 880         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
 881                                       len, &io_device->dev);
 882         mutex_unlock(&kvm->slots_lock);
 883
 884         return ret;
 885 }