drivers/video/da8xx-fb.c

   1 /*
   2  * Copyright (C) 2008-2009 MontaVista Software Inc.
   3  * Copyright (C) 2008-2009 Texas Instruments Inc
   4  *
   5  * Based on the LCD driver for TI Avalanche processors written by
   6  * Ajay Singh and Shalom Hai.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option)any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/fb.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/clk.h>
  32 #include <video/da8xx-fb.h>
  33
  34 #define DRIVER_NAME "da8xx_lcdc"
  35
  36 /* LCD Status Register */
  37 #define LCD_END_OF_FRAME0               BIT(8)
  38 #define LCD_FIFO_UNDERFLOW              BIT(5)
  39 #define LCD_SYNC_LOST                   BIT(2)
  40
  41 /* LCD DMA Control Register */
  42 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
  43 #define LCD_DMA_BURST_1                 0x0
  44 #define LCD_DMA_BURST_2                 0x1
  45 #define LCD_DMA_BURST_4                 0x2
  46 #define LCD_DMA_BURST_8                 0x3
  47 #define LCD_DMA_BURST_16                0x4
  48 #define LCD_END_OF_FRAME_INT_ENA        BIT(2)
  49 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
  50
  51 /* LCD Control Register */
  52 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
  53 #define LCD_RASTER_MODE                 0x01
  54
  55 /* LCD Raster Control Register */
  56 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
  57 #define PALETTE_AND_DATA                0x00
  58 #define PALETTE_ONLY                    0x01
  59
  60 #define LCD_MONO_8BIT_MODE              BIT(9)
  61 #define LCD_RASTER_ORDER                BIT(8)
  62 #define LCD_TFT_MODE                    BIT(7)
  63 #define LCD_UNDERFLOW_INT_ENA           BIT(6)
  64 #define LCD_MONOCHROME_MODE             BIT(1)
  65 #define LCD_RASTER_ENABLE               BIT(0)
  66 #define LCD_TFT_ALT_ENABLE              BIT(23)
  67 #define LCD_STN_565_ENABLE              BIT(24)
  68
  69 /* LCD Raster Timing 2 Register */
  70 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  71 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  72 #define LCD_SYNC_CTRL                           BIT(25)
  73 #define LCD_SYNC_EDGE                           BIT(24)
  74 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
  75 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
  76 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
  77
  78 /* LCD Block */
  79 #define  LCD_CTRL_REG                           0x4
  80 #define  LCD_STAT_REG                           0x8
  81 #define  LCD_RASTER_CTRL_REG                    0x28
  82 #define  LCD_RASTER_TIMING_0_REG                0x2C
  83 #define  LCD_RASTER_TIMING_1_REG                0x30
  84 #define  LCD_RASTER_TIMING_2_REG                0x34
  85 #define  LCD_DMA_CTRL_REG                       0x40
  86 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
  87 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
  88
  89 #define WSI_TIMEOUT     50
  90 #define PALETTE_SIZE    256
  91 #define LEFT_MARGIN     64
  92 #define RIGHT_MARGIN    64
  93 #define UPPER_MARGIN    32
  94 #define LOWER_MARGIN    32
  95
  96 static resource_size_t da8xx_fb_reg_base;
  97 static struct resource *lcdc_regs;
  98
  99 static inline unsigned int lcdc_read(unsigned int addr)
 100 {
 101         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
 102 }
 103
 104 static inline void lcdc_write(unsigned int val, unsigned int addr)
 105 {
 106         __raw_writel(val, da8xx_fb_reg_base + (addr));
 107 }
 108
 109 struct da8xx_fb_par {
 110         resource_size_t p_palette_base;
 111         unsigned char *v_palette_base;
 112         struct clk *lcdc_clk;
 113         int irq;
 114         unsigned short pseudo_palette[16];
 115         unsigned int databuf_sz;
 116         unsigned int palette_sz;
 117 };
 118
 119 /* Variable Screen Information */
 120 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
 121         .xoffset = 0,
 122         .yoffset = 0,
 123         .transp = {0, 0, 0},
 124         .nonstd = 0,
 125         .activate = 0,
 126         .height = -1,
 127         .width = -1,
 128         .pixclock = 46666,      /* 46us - AUO display */
 129         .accel_flags = 0,
 130         .left_margin = LEFT_MARGIN,
 131         .right_margin = RIGHT_MARGIN,
 132         .upper_margin = UPPER_MARGIN,
 133         .lower_margin = LOWER_MARGIN,
 134         .sync = 0,
 135         .vmode = FB_VMODE_NONINTERLACED
 136 };
 137
 138 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
 139         .id = "DA8xx FB Drv",
 140         .type = FB_TYPE_PACKED_PIXELS,
 141         .type_aux = 0,
 142         .visual = FB_VISUAL_PSEUDOCOLOR,
 143         .xpanstep = 1,
 144         .ypanstep = 1,
 145         .ywrapstep = 1,
 146         .accel = FB_ACCEL_NONE
 147 };
 148
 149 struct da8xx_panel {
 150         const char      name[25];       /* Full name <vendor>_<model> */
 151         unsigned short  width;
 152         unsigned short  height;
 153         int             hfp;            /* Horizontal front porch */
 154         int             hbp;            /* Horizontal back porch */
 155         int             hsw;            /* Horizontal Sync Pulse Width */
 156         int             vfp;            /* Vertical front porch */
 157         int             vbp;            /* Vertical back porch */
 158         int             vsw;            /* Vertical Sync Pulse Width */
 159         int             pxl_clk;        /* Pixel clock */
 160         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
 161 };
 162
 163 static struct da8xx_panel known_lcd_panels[] = {
 164         /* Sharp LCD035Q3DG01 */
 165         [0] = {
 166                 .name = "Sharp_LCD035Q3DG01",
 167                 .width = 320,
 168                 .height = 240,
 169                 .hfp = 8,
 170                 .hbp = 6,
 171                 .hsw = 0,
 172                 .vfp = 2,
 173                 .vbp = 2,
 174                 .vsw = 0,
 175                 .pxl_clk = 0x10,
 176                 .invert_pxl_clk = 1,
 177         },
 178         /* Sharp LK043T1DG01 */
 179         [1] = {
 180                 .name = "Sharp_LK043T1DG01",
 181                 .width = 480,
 182                 .height = 272,
 183                 .hfp = 2,
 184                 .hbp = 2,
 185                 .hsw = 41,
 186                 .vfp = 2,
 187                 .vbp = 2,
 188                 .vsw = 10,
 189                 .pxl_clk = 0x12,
 190                 .invert_pxl_clk = 0,
 191         },
 192 };
 193
 194 /* Disable the Raster Engine of the LCD Controller */
 195 static void lcd_disable_raster(struct da8xx_fb_par *par)
 196 {
 197         u32 reg;
 198
 199         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 200         if (reg & LCD_RASTER_ENABLE)
 201                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 202 }
 203
 204 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 205 {
 206         u32 tmp = par->p_palette_base + par->databuf_sz - 4;
 207         u32 reg;
 208
 209         /* Update the databuf in the hw. */
 210         lcdc_write(par->p_palette_base, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 211         lcdc_write(tmp, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 212
 213         /* Start the DMA. */
 214         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 215         reg &= ~(3 << 20);
 216         if (load_mode == LOAD_DATA)
 217                 reg |= LCD_PALETTE_LOAD_MODE(PALETTE_AND_DATA);
 218         else if (load_mode == LOAD_PALETTE)
 219                 reg |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 220
 221         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 222 }
 223
 224 /* Configure the Burst Size of DMA */
 225 static int lcd_cfg_dma(int burst_size)
 226 {
 227         u32 reg;
 228
 229         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
 230         switch (burst_size) {
 231         case 1:
 232                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 233                 break;
 234         case 2:
 235                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 236                 break;
 237         case 4:
 238                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 239                 break;
 240         case 8:
 241                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 242                 break;
 243         case 16:
 244                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 245                 break;
 246         default:
 247                 return -EINVAL;
 248         }
 249         lcdc_write(reg, LCD_DMA_CTRL_REG);
 250
 251         return 0;
 252 }
 253
 254 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 255 {
 256         u32 reg;
 257
 258         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
 259         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
 260         reg |= LCD_AC_BIAS_FREQUENCY(period) |
 261                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 262         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 263 }
 264
 265 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 266                 int front_porch)
 267 {
 268         u32 reg;
 269
 270         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
 271         reg |= ((back_porch & 0xff) << 24)
 272             | ((front_porch & 0xff) << 16)
 273             | ((pulse_width & 0x3f) << 10);
 274         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 275 }
 276
 277 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 278                 int front_porch)
 279 {
 280         u32 reg;
 281
 282         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
 283         reg |= ((back_porch & 0xff) << 24)
 284             | ((front_porch & 0xff) << 16)
 285             | ((pulse_width & 0x3f) << 10);
 286         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 287 }
 288
 289 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
 290 {
 291         u32 reg;
 292
 293         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
 294                                                 LCD_MONO_8BIT_MODE |
 295                                                 LCD_MONOCHROME_MODE);
 296
 297         switch (cfg->p_disp_panel->panel_shade) {
 298         case MONOCHROME:
 299                 reg |= LCD_MONOCHROME_MODE;
 300                 if (cfg->mono_8bit_mode)
 301                         reg |= LCD_MONO_8BIT_MODE;
 302                 break;
 303         case COLOR_ACTIVE:
 304                 reg |= LCD_TFT_MODE;
 305                 if (cfg->tft_alt_mode)
 306                         reg |= LCD_TFT_ALT_ENABLE;
 307                 break;
 308
 309         case COLOR_PASSIVE:
 310                 if (cfg->stn_565_mode)
 311                         reg |= LCD_STN_565_ENABLE;
 312                 break;
 313
 314         default:
 315                 return -EINVAL;
 316         }
 317
 318         /* enable additional interrupts here */
 319         reg |= LCD_UNDERFLOW_INT_ENA;
 320
 321         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 322
 323         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 324
 325         if (cfg->sync_ctrl)
 326                 reg |= LCD_SYNC_CTRL;
 327         else
 328                 reg &= ~LCD_SYNC_CTRL;
 329
 330         if (cfg->sync_edge)
 331                 reg |= LCD_SYNC_EDGE;
 332         else
 333                 reg &= ~LCD_SYNC_EDGE;
 334
 335         if (cfg->invert_line_clock)
 336                 reg |= LCD_INVERT_LINE_CLOCK;
 337         else
 338                 reg &= ~LCD_INVERT_LINE_CLOCK;
 339
 340         if (cfg->invert_frm_clock)
 341                 reg |= LCD_INVERT_FRAME_CLOCK;
 342         else
 343                 reg &= ~LCD_INVERT_FRAME_CLOCK;
 344
 345         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 346
 347         return 0;
 348 }
 349
 350 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 351                 u32 bpp, u32 raster_order)
 352 {
 353         u32 bpl, reg;
 354
 355         /* Disable Dual Frame Buffer. */
 356         reg = lcdc_read(LCD_DMA_CTRL_REG);
 357         lcdc_write(reg & ~LCD_DUAL_FRAME_BUFFER_ENABLE,
 358                                                 LCD_DMA_CTRL_REG);
 359         /* Set the Panel Width */
 360         /* Pixels per line = (PPL + 1)*16 */
 361         /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
 362         width &= 0x3f0;
 363         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
 364         reg &= 0xfffffc00;
 365         reg |= ((width >> 4) - 1) << 4;
 366         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 367
 368         /* Set the Panel Height */
 369         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
 370         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 371         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 372
 373         /* Set the Raster Order of the Frame Buffer */
 374         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
 375         if (raster_order)
 376                 reg |= LCD_RASTER_ORDER;
 377         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 378
 379         switch (bpp) {
 380         case 1:
 381         case 2:
 382         case 4:
 383         case 16:
 384                 par->palette_sz = 16 * 2;
 385                 break;
 386
 387         case 8:
 388                 par->palette_sz = 256 * 2;
 389                 break;
 390
 391         default:
 392                 return -EINVAL;
 393         }
 394
 395         bpl = width * bpp / 8;
 396         par->databuf_sz = height * bpl + par->palette_sz;
 397
 398         return 0;
 399 }
 400
 401 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 402                               unsigned blue, unsigned transp,
 403                               struct fb_info *info)
 404 {
 405         struct da8xx_fb_par *par = info->par;
 406         unsigned short *palette = (unsigned short *)par->v_palette_base;
 407         u_short pal;
 408
 409         if (regno > 255)
 410                 return 1;
 411
 412         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 413                 return 1;
 414
 415         if (info->var.bits_per_pixel == 8) {
 416                 red >>= 4;
 417                 green >>= 8;
 418                 blue >>= 12;
 419
 420                 pal = (red & 0x0f00);
 421                 pal |= (green & 0x00f0);
 422                 pal |= (blue & 0x000f);
 423
 424                 palette[regno] = pal;
 425
 426         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
 427                 red >>= (16 - info->var.red.length);
 428                 red <<= info->var.red.offset;
 429
 430                 green >>= (16 - info->var.green.length);
 431                 green <<= info->var.green.offset;
 432
 433                 blue >>= (16 - info->var.blue.length);
 434                 blue <<= info->var.blue.offset;
 435
 436                 par->pseudo_palette[regno] = red | green | blue;
 437
 438                 palette[0] = 0x4000;
 439         }
 440
 441         return 0;
 442 }
 443
 444 static void lcd_reset(struct da8xx_fb_par *par)
 445 {
 446         /* Disable the Raster if previously Enabled */
 447         if (lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE)
 448                 lcd_disable_raster(par);
 449
 450         /* DMA has to be disabled */
 451         lcdc_write(0, LCD_DMA_CTRL_REG);
 452         lcdc_write(0, LCD_RASTER_CTRL_REG);
 453 }
 454
 455 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 456                 struct da8xx_panel *panel)
 457 {
 458         u32 bpp;
 459         int ret = 0;
 460
 461         lcd_reset(par);
 462
 463         /* Configure the LCD clock divisor. */
 464         lcdc_write(LCD_CLK_DIVISOR(panel->pxl_clk) |
 465                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
 466
 467         if (panel->invert_pxl_clk)
 468                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
 469                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 470         else
 471                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
 472                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 473
 474         /* Configure the DMA burst size. */
 475         ret = lcd_cfg_dma(cfg->dma_burst_sz);
 476         if (ret < 0)
 477                 return ret;
 478
 479         /* Configure the AC bias properties. */
 480         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 481
 482         /* Configure the vertical and horizontal sync properties. */
 483         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
 484         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
 485
 486         /* Configure for disply */
 487         ret = lcd_cfg_display(cfg);
 488         if (ret < 0)
 489                 return ret;
 490
 491         if (QVGA != cfg->p_disp_panel->panel_type)
 492                 return -EINVAL;
 493
 494         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
 495             cfg->bpp >= cfg->p_disp_panel->min_bpp)
 496                 bpp = cfg->bpp;
 497         else
 498                 bpp = cfg->p_disp_panel->max_bpp;
 499         if (bpp == 12)
 500                 bpp = 16;
 501         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
 502                                 (unsigned int)panel->height, bpp,
 503                                 cfg->raster_order);
 504         if (ret < 0)
 505                 return ret;
 506
 507         /* Configure FDD */
 508         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
 509                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
 510
 511         return 0;
 512 }
 513
 514 static irqreturn_t lcdc_irq_handler(int irq, void *arg)
 515 {
 516         u32 stat = lcdc_read(LCD_STAT_REG);
 517         u32 reg;
 518
 519         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 520                 reg = lcdc_read(LCD_RASTER_CTRL_REG);
 521                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 522                 lcdc_write(stat, LCD_STAT_REG);
 523                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 524         } else
 525                 lcdc_write(stat, LCD_STAT_REG);
 526
 527         return IRQ_HANDLED;
 528 }
 529
 530 static int fb_check_var(struct fb_var_screeninfo *var,
 531                         struct fb_info *info)
 532 {
 533         int err = 0;
 534
 535         switch (var->bits_per_pixel) {
 536         case 1:
 537         case 8:
 538                 var->red.offset = 0;
 539                 var->red.length = 8;
 540                 var->green.offset = 0;
 541                 var->green.length = 8;
 542                 var->blue.offset = 0;
 543                 var->blue.length = 8;
 544                 var->transp.offset = 0;
 545                 var->transp.length = 0;
 546                 break;
 547         case 4:
 548                 var->red.offset = 0;
 549                 var->red.length = 4;
 550                 var->green.offset = 0;
 551                 var->green.length = 4;
 552                 var->blue.offset = 0;
 553                 var->blue.length = 4;
 554                 var->transp.offset = 0;
 555                 var->transp.length = 0;
 556                 break;
 557         case 16:                /* RGB 565 */
 558                 var->red.offset = 0;
 559                 var->red.length = 5;
 560                 var->green.offset = 5;
 561                 var->green.length = 6;
 562                 var->blue.offset = 11;
 563                 var->blue.length = 5;
 564                 var->transp.offset = 0;
 565                 var->transp.length = 0;
 566                 break;
 567         default:
 568                 err = -EINVAL;
 569         }
 570
 571         var->red.msb_right = 0;
 572         var->green.msb_right = 0;
 573         var->blue.msb_right = 0;
 574         var->transp.msb_right = 0;
 575         return err;
 576 }
 577
 578 static int __devexit fb_remove(struct platform_device *dev)
 579 {
 580         struct fb_info *info = dev_get_drvdata(&dev->dev);
 581
 582         if (info) {
 583                 struct da8xx_fb_par *par = info->par;
 584
 585                 if (lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE)
 586                         lcd_disable_raster(par);
 587                 lcdc_write(0, LCD_RASTER_CTRL_REG);
 588
 589                 /* disable DMA  */
 590                 lcdc_write(0, LCD_DMA_CTRL_REG);
 591
 592                 unregister_framebuffer(info);
 593                 fb_dealloc_cmap(&info->cmap);
 594                 dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
 595                                         info->screen_base,
 596                                         info->fix.smem_start);
 597                 free_irq(par->irq, par);
 598                 clk_disable(par->lcdc_clk);
 599                 clk_put(par->lcdc_clk);
 600                 framebuffer_release(info);
 601                 iounmap((void __iomem *)da8xx_fb_reg_base);
 602                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
 603
 604         }
 605         return 0;
 606 }
 607
 608 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
 609                           unsigned long arg)
 610 {
 611         struct lcd_sync_arg sync_arg;
 612
 613         switch (cmd) {
 614         case FBIOGET_CONTRAST:
 615         case FBIOPUT_CONTRAST:
 616         case FBIGET_BRIGHTNESS:
 617         case FBIPUT_BRIGHTNESS:
 618         case FBIGET_COLOR:
 619         case FBIPUT_COLOR:
 620                 return -ENOTTY;
 621         case FBIPUT_HSYNC:
 622                 if (copy_from_user(&sync_arg, (char *)arg,
 623                                 sizeof(struct lcd_sync_arg)))
 624                         return -EFAULT;
 625                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
 626                                         sync_arg.pulse_width,
 627                                         sync_arg.front_porch);
 628                 break;
 629         case FBIPUT_VSYNC:
 630                 if (copy_from_user(&sync_arg, (char *)arg,
 631                                 sizeof(struct lcd_sync_arg)))
 632                         return -EFAULT;
 633                 lcd_cfg_vertical_sync(sync_arg.back_porch,
 634                                         sync_arg.pulse_width,
 635                                         sync_arg.front_porch);
 636                 break;
 637         default:
 638                 return -EINVAL;
 639         }
 640         return 0;
 641 }
 642
 643 static struct fb_ops da8xx_fb_ops = {
 644         .owner = THIS_MODULE,
 645         .fb_check_var = fb_check_var,
 646         .fb_setcolreg = fb_setcolreg,
 647         .fb_ioctl = fb_ioctl,
 648         .fb_fillrect = cfb_fillrect,
 649         .fb_copyarea = cfb_copyarea,
 650         .fb_imageblit = cfb_imageblit,
 651 };
 652
 653 static int __init fb_probe(struct platform_device *device)
 654 {
 655         struct da8xx_lcdc_platform_data *fb_pdata =
 656                                                 device->dev.platform_data;
 657         struct lcd_ctrl_config *lcd_cfg;
 658         struct da8xx_panel *lcdc_info;
 659         struct fb_info *da8xx_fb_info;
 660         struct clk *fb_clk = NULL;
 661         struct da8xx_fb_par *par;
 662         resource_size_t len;
 663         int ret, i;
 664
 665         if (fb_pdata == NULL) {
 666                 dev_err(&device->dev, "Can not get platform data\n");
 667                 return -ENOENT;
 668         }
 669
 670         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
 671         if (!lcdc_regs) {
 672                 dev_err(&device->dev,
 673                         "Can not get memory resource for LCD controller\n");
 674                 return -ENOENT;
 675         }
 676
 677         len = resource_size(lcdc_regs);
 678
 679         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
 680         if (!lcdc_regs)
 681                 return -EBUSY;
 682
 683         da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
 684         if (!da8xx_fb_reg_base) {
 685                 ret = -EBUSY;
 686                 goto err_request_mem;
 687         }
 688
 689         fb_clk = clk_get(&device->dev, NULL);
 690         if (IS_ERR(fb_clk)) {
 691                 dev_err(&device->dev, "Can not get device clock\n");
 692                 ret = -ENODEV;
 693                 goto err_ioremap;
 694         }
 695         ret = clk_enable(fb_clk);
 696         if (ret)
 697                 goto err_clk_put;
 698
 699         for (i = 0, lcdc_info = known_lcd_panels;
 700                 i < ARRAY_SIZE(known_lcd_panels);
 701                 i++, lcdc_info++) {
 702                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
 703                         break;
 704         }
 705
 706         if (i == ARRAY_SIZE(known_lcd_panels)) {
 707                 dev_err(&device->dev, "GLCD: No valid panel found\n");
 708                 ret = ENODEV;
 709                 goto err_clk_disable;
 710         } else
 711                 dev_info(&device->dev, "GLCD: Found %s panel\n",
 712                                         fb_pdata->type);
 713
 714         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
 715
 716         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
 717                                         &device->dev);
 718         if (!da8xx_fb_info) {
 719                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
 720                 ret = -ENOMEM;
 721                 goto err_clk_disable;
 722         }
 723
 724         par = da8xx_fb_info->par;
 725
 726         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
 727                 dev_err(&device->dev, "lcd_init failed\n");
 728                 ret = -EFAULT;
 729                 goto err_release_fb;
 730         }
 731
 732         /* allocate frame buffer */
 733         da8xx_fb_info->screen_base = dma_alloc_coherent(NULL,
 734                                         par->databuf_sz + PAGE_SIZE,
 735                                         (resource_size_t *)
 736                                         &da8xx_fb_info->fix.smem_start,
 737                                         GFP_KERNEL | GFP_DMA);
 738
 739         if (!da8xx_fb_info->screen_base) {
 740                 dev_err(&device->dev,
 741                         "GLCD: kmalloc for frame buffer failed\n");
 742                 ret = -EINVAL;
 743                 goto err_release_fb;
 744         }
 745
 746         /* move palette base pointer by (PAGE_SIZE - palette_sz) bytes */
 747         par->v_palette_base = da8xx_fb_info->screen_base +
 748                                 (PAGE_SIZE - par->palette_sz);
 749         par->p_palette_base = da8xx_fb_info->fix.smem_start +
 750                                 (PAGE_SIZE - par->palette_sz);
 751
 752         /* the rest of the frame buffer is pixel data */
 753         da8xx_fb_fix.smem_start = par->p_palette_base + par->palette_sz;
 754         da8xx_fb_fix.smem_len = par->databuf_sz - par->palette_sz;
 755         da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
 756
 757         par->lcdc_clk = fb_clk;
 758
 759         par->irq = platform_get_irq(device, 0);
 760         if (par->irq < 0) {
 761                 ret = -ENOENT;
 762                 goto err_release_fb_mem;
 763         }
 764
 765         ret = request_irq(par->irq, lcdc_irq_handler, 0, DRIVER_NAME, par);
 766         if (ret)
 767                 goto err_release_fb_mem;
 768
 769         /* Initialize par */
 770         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
 771
 772         da8xx_fb_var.xres = lcdc_info->width;
 773         da8xx_fb_var.xres_virtual = lcdc_info->width;
 774
 775         da8xx_fb_var.yres = lcdc_info->height;
 776         da8xx_fb_var.yres_virtual = lcdc_info->height;
 777
 778         da8xx_fb_var.grayscale =
 779             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
 780         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
 781
 782         da8xx_fb_var.hsync_len = lcdc_info->hsw;
 783         da8xx_fb_var.vsync_len = lcdc_info->vsw;
 784
 785         /* Initialize fbinfo */
 786         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
 787         da8xx_fb_info->fix = da8xx_fb_fix;
 788         da8xx_fb_info->var = da8xx_fb_var;
 789         da8xx_fb_info->fbops = &da8xx_fb_ops;
 790         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
 791
 792         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
 793         if (ret)
 794                 goto err_free_irq;
 795
 796         /* First palette_sz byte of the frame buffer is the palette */
 797         da8xx_fb_info->cmap.len = par->palette_sz;
 798
 799         /* Flush the buffer to the screen. */
 800         lcd_blit(LOAD_DATA, par);
 801
 802         /* initialize var_screeninfo */
 803         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
 804         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
 805
 806         dev_set_drvdata(&device->dev, da8xx_fb_info);
 807         /* Register the Frame Buffer  */
 808         if (register_framebuffer(da8xx_fb_info) < 0) {
 809                 dev_err(&device->dev,
 810                         "GLCD: Frame Buffer Registration Failed!\n");
 811                 ret = -EINVAL;
 812                 goto err_dealloc_cmap;
 813         }
 814
 815         /* enable raster engine */
 816         lcdc_write(lcdc_read(LCD_RASTER_CTRL_REG) |
 817                         LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 818
 819         return 0;
 820
 821 err_dealloc_cmap:
 822         fb_dealloc_cmap(&da8xx_fb_info->cmap);
 823
 824 err_free_irq:
 825         free_irq(par->irq, par);
 826
 827 err_release_fb_mem:
 828         dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
 829                                 da8xx_fb_info->screen_base,
 830                                 da8xx_fb_info->fix.smem_start);
 831
 832 err_release_fb:
 833         framebuffer_release(da8xx_fb_info);
 834
 835 err_clk_disable:
 836         clk_disable(fb_clk);
 837
 838 err_clk_put:
 839         clk_put(fb_clk);
 840
 841 err_ioremap:
 842         iounmap((void __iomem *)da8xx_fb_reg_base);
 843
 844 err_request_mem:
 845         release_mem_region(lcdc_regs->start, len);
 846
 847         return ret;
 848 }
 849
 850 #ifdef CONFIG_PM
 851 static int fb_suspend(struct platform_device *dev, pm_message_t state)
 852 {
 853          return -EBUSY;
 854 }
 855 static int fb_resume(struct platform_device *dev)
 856 {
 857          return -EBUSY;
 858 }
 859 #else
 860 #define fb_suspend NULL
 861 #define fb_resume NULL
 862 #endif
 863
 864 static struct platform_driver da8xx_fb_driver = {
 865         .probe = fb_probe,
 866         .remove = fb_remove,
 867         .suspend = fb_suspend,
 868         .resume = fb_resume,
 869         .driver = {
 870                    .name = DRIVER_NAME,
 871                    .owner = THIS_MODULE,
 872                    },
 873 };
 874
 875 static int __init da8xx_fb_init(void)
 876 {
 877         return platform_driver_register(&da8xx_fb_driver);
 878 }
 879
 880 static void __exit da8xx_fb_cleanup(void)
 881 {
 882         platform_driver_unregister(&da8xx_fb_driver);
 883 }
 884
 885 module_init(da8xx_fb_init);
 886 module_exit(da8xx_fb_cleanup);
 887
 888 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
 889 MODULE_AUTHOR("Texas Instruments");
 890 MODULE_LICENSE("GPL");