1 // SPDX-License-Identifier: GPL-2.0+
3 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
5 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
6 * Author: Thomas Dahlmann
10 * This file does the core driver implementation for the UDC that is based
11 * on Synopsys device controller IP (different than HS OTG IP) that is either
12 * connected through PCI bus or integrated to SoC platforms.
16 #define UDC_MOD_DESCRIPTION "Synopsys USB Device Controller"
17 #define UDC_DRIVER_VERSION_STRING "01.00.0206"
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/timer.h>
28 #include <linux/list.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioctl.h>
32 #include <linux/dmapool.h>
33 #include <linux/prefetch.h>
34 #include <linux/moduleparam.h>
35 #include <asm/byteorder.h>
36 #include <asm/unaligned.h>
37 #include "amd5536udc.h"
39 static void udc_tasklet_disconnect(unsigned long);
40 static void udc_setup_endpoints(struct udc *dev);
41 static void udc_soft_reset(struct udc *dev);
42 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
43 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
46 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
47 static const char name[] = "udc";
49 /* structure to hold endpoint function pointers */
50 static const struct usb_ep_ops udc_ep_ops;
52 /* received setup data */
53 static union udc_setup_data setup_data;
55 /* pointer to device object */
56 static struct udc *udc;
58 /* irq spin lock for soft reset */
59 static DEFINE_SPINLOCK(udc_irq_spinlock);
61 static DEFINE_SPINLOCK(udc_stall_spinlock);
64 * slave mode: pending bytes in rx fifo after nyet,
65 * used if EPIN irq came but no req was available
67 static unsigned int udc_rxfifo_pending;
69 /* count soft resets after suspend to avoid loop */
70 static int soft_reset_occured;
71 static int soft_reset_after_usbreset_occured;
74 static struct timer_list udc_timer;
75 static int stop_timer;
77 /* set_rde -- Is used to control enabling of RX DMA. Problem is
78 * that UDC has only one bit (RDE) to enable/disable RX DMA for
79 * all OUT endpoints. So we have to handle race conditions like
80 * when OUT data reaches the fifo but no request was queued yet.
81 * This cannot be solved by letting the RX DMA disabled until a
82 * request gets queued because there may be other OUT packets
83 * in the FIFO (important for not blocking control traffic).
84 * The value of set_rde controls the correspondig timer.
86 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
87 * set_rde 0 == do not touch RDE, do no start the RDE timer
88 * set_rde 1 == timer function will look whether FIFO has data
89 * set_rde 2 == set by timer function to enable RX DMA on next call
91 static int set_rde = -1;
93 static DECLARE_COMPLETION(on_exit);
94 static struct timer_list udc_pollstall_timer;
95 static int stop_pollstall_timer;
96 static DECLARE_COMPLETION(on_pollstall_exit);
98 /* tasklet for usb disconnect */
99 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
100 (unsigned long) &udc);
103 /* endpoint names used for print */
104 static const char ep0_string[] = "ep0in";
105 static const struct {
107 const struct usb_ep_caps caps;
109 #define EP_INFO(_name, _caps) \
116 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_IN)),
118 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
119 EP_INFO("ep2in-bulk",
120 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
121 EP_INFO("ep3in-bulk",
122 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
123 EP_INFO("ep4in-bulk",
124 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
125 EP_INFO("ep5in-bulk",
126 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
127 EP_INFO("ep6in-bulk",
128 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
129 EP_INFO("ep7in-bulk",
130 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
131 EP_INFO("ep8in-bulk",
132 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
133 EP_INFO("ep9in-bulk",
134 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
135 EP_INFO("ep10in-bulk",
136 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
137 EP_INFO("ep11in-bulk",
138 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
139 EP_INFO("ep12in-bulk",
140 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
141 EP_INFO("ep13in-bulk",
142 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
143 EP_INFO("ep14in-bulk",
144 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
145 EP_INFO("ep15in-bulk",
146 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
148 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_OUT)),
149 EP_INFO("ep1out-bulk",
150 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
151 EP_INFO("ep2out-bulk",
152 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
153 EP_INFO("ep3out-bulk",
154 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
155 EP_INFO("ep4out-bulk",
156 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
157 EP_INFO("ep5out-bulk",
158 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
159 EP_INFO("ep6out-bulk",
160 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
161 EP_INFO("ep7out-bulk",
162 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
163 EP_INFO("ep8out-bulk",
164 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
165 EP_INFO("ep9out-bulk",
166 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
167 EP_INFO("ep10out-bulk",
168 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
169 EP_INFO("ep11out-bulk",
170 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
171 EP_INFO("ep12out-bulk",
172 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
173 EP_INFO("ep13out-bulk",
174 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
175 EP_INFO("ep14out-bulk",
176 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
177 EP_INFO("ep15out-bulk",
178 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
183 /* buffer fill mode */
184 static int use_dma_bufferfill_mode;
185 /* tx buffer size for high speed */
186 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
188 /*---------------------------------------------------------------------------*/
189 /* Prints UDC device registers and endpoint irq registers */
190 static void print_regs(struct udc *dev)
192 DBG(dev, "------- Device registers -------\n");
193 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
194 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
195 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
197 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
198 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
200 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
201 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
203 DBG(dev, "USE DMA = %d\n", use_dma);
204 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
205 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
206 "WITHOUT desc. update)\n");
207 dev_info(dev->dev, "DMA mode (%s)\n", "PPBNDU");
208 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
209 DBG(dev, "DMA mode = PPBDU (packet per buffer "
210 "WITH desc. update)\n");
211 dev_info(dev->dev, "DMA mode (%s)\n", "PPBDU");
213 if (use_dma && use_dma_bufferfill_mode) {
214 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
215 dev_info(dev->dev, "DMA mode (%s)\n", "BF");
218 dev_info(dev->dev, "FIFO mode\n");
219 DBG(dev, "-------------------------------------------------------\n");
222 /* Masks unused interrupts */
223 int udc_mask_unused_interrupts(struct udc *dev)
227 /* mask all dev interrupts */
228 tmp = AMD_BIT(UDC_DEVINT_SVC) |
229 AMD_BIT(UDC_DEVINT_ENUM) |
230 AMD_BIT(UDC_DEVINT_US) |
231 AMD_BIT(UDC_DEVINT_UR) |
232 AMD_BIT(UDC_DEVINT_ES) |
233 AMD_BIT(UDC_DEVINT_SI) |
234 AMD_BIT(UDC_DEVINT_SOF)|
235 AMD_BIT(UDC_DEVINT_SC);
236 writel(tmp, &dev->regs->irqmsk);
238 /* mask all ep interrupts */
239 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
243 EXPORT_SYMBOL_GPL(udc_mask_unused_interrupts);
245 /* Enables endpoint 0 interrupts */
246 static int udc_enable_ep0_interrupts(struct udc *dev)
250 DBG(dev, "udc_enable_ep0_interrupts()\n");
253 tmp = readl(&dev->regs->ep_irqmsk);
254 /* enable ep0 irq's */
255 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
256 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
257 writel(tmp, &dev->regs->ep_irqmsk);
262 /* Enables device interrupts for SET_INTF and SET_CONFIG */
263 int udc_enable_dev_setup_interrupts(struct udc *dev)
267 DBG(dev, "enable device interrupts for setup data\n");
270 tmp = readl(&dev->regs->irqmsk);
272 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
273 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
274 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
275 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
276 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
277 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
278 writel(tmp, &dev->regs->irqmsk);
282 EXPORT_SYMBOL_GPL(udc_enable_dev_setup_interrupts);
284 /* Calculates fifo start of endpoint based on preceding endpoints */
285 static int udc_set_txfifo_addr(struct udc_ep *ep)
291 if (!ep || !(ep->in))
295 ep->txfifo = dev->txfifo;
298 for (i = 0; i < ep->num; i++) {
299 if (dev->ep[i].regs) {
301 tmp = readl(&dev->ep[i].regs->bufin_framenum);
302 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
309 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
310 static u32 cnak_pending;
312 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
314 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
315 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
316 cnak_pending |= 1 << (num);
319 cnak_pending = cnak_pending & (~(1 << (num)));
323 /* Enables endpoint, is called by gadget driver */
325 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
330 unsigned long iflags;
335 || usbep->name == ep0_string
337 || desc->bDescriptorType != USB_DT_ENDPOINT)
340 ep = container_of(usbep, struct udc_ep, ep);
343 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
345 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
348 spin_lock_irqsave(&dev->lock, iflags);
353 /* set traffic type */
354 tmp = readl(&dev->ep[ep->num].regs->ctl);
355 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
356 writel(tmp, &dev->ep[ep->num].regs->ctl);
358 /* set max packet size */
359 maxpacket = usb_endpoint_maxp(desc);
360 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
361 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
362 ep->ep.maxpacket = maxpacket;
363 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
368 /* ep ix in UDC CSR register space */
369 udc_csr_epix = ep->num;
371 /* set buffer size (tx fifo entries) */
372 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
373 /* double buffering: fifo size = 2 x max packet size */
376 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
379 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
381 /* calc. tx fifo base addr */
382 udc_set_txfifo_addr(ep);
385 tmp = readl(&ep->regs->ctl);
386 tmp |= AMD_BIT(UDC_EPCTL_F);
387 writel(tmp, &ep->regs->ctl);
391 /* ep ix in UDC CSR register space */
392 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
394 /* set max packet size UDC CSR */
395 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
396 tmp = AMD_ADDBITS(tmp, maxpacket,
398 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
400 if (use_dma && !ep->in) {
401 /* alloc and init BNA dummy request */
402 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
403 ep->bna_occurred = 0;
406 if (ep->num != UDC_EP0OUT_IX)
407 dev->data_ep_enabled = 1;
411 tmp = readl(&dev->csr->ne[udc_csr_epix]);
413 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
415 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
417 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
419 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
421 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
423 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
425 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
427 writel(tmp, &dev->csr->ne[udc_csr_epix]);
430 tmp = readl(&dev->regs->ep_irqmsk);
431 tmp &= AMD_UNMASK_BIT(ep->num);
432 writel(tmp, &dev->regs->ep_irqmsk);
435 * clear NAK by writing CNAK
436 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
438 if (!use_dma || ep->in) {
439 tmp = readl(&ep->regs->ctl);
440 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
441 writel(tmp, &ep->regs->ctl);
443 UDC_QUEUE_CNAK(ep, ep->num);
445 tmp = desc->bEndpointAddress;
446 DBG(dev, "%s enabled\n", usbep->name);
448 spin_unlock_irqrestore(&dev->lock, iflags);
452 /* Resets endpoint */
453 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
457 VDBG(ep->dev, "ep-%d reset\n", ep->num);
459 ep->ep.ops = &udc_ep_ops;
460 INIT_LIST_HEAD(&ep->queue);
462 usb_ep_set_maxpacket_limit(&ep->ep,(u16) ~0);
464 tmp = readl(&ep->regs->ctl);
465 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
466 writel(tmp, &ep->regs->ctl);
469 /* disable interrupt */
470 tmp = readl(®s->ep_irqmsk);
471 tmp |= AMD_BIT(ep->num);
472 writel(tmp, ®s->ep_irqmsk);
475 /* unset P and IN bit of potential former DMA */
476 tmp = readl(&ep->regs->ctl);
477 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
478 writel(tmp, &ep->regs->ctl);
480 tmp = readl(&ep->regs->sts);
481 tmp |= AMD_BIT(UDC_EPSTS_IN);
482 writel(tmp, &ep->regs->sts);
485 tmp = readl(&ep->regs->ctl);
486 tmp |= AMD_BIT(UDC_EPCTL_F);
487 writel(tmp, &ep->regs->ctl);
490 /* reset desc pointer */
491 writel(0, &ep->regs->desptr);
494 /* Disables endpoint, is called by gadget driver */
495 static int udc_ep_disable(struct usb_ep *usbep)
497 struct udc_ep *ep = NULL;
498 unsigned long iflags;
503 ep = container_of(usbep, struct udc_ep, ep);
504 if (usbep->name == ep0_string || !ep->ep.desc)
507 DBG(ep->dev, "Disable ep-%d\n", ep->num);
509 spin_lock_irqsave(&ep->dev->lock, iflags);
510 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
512 ep_init(ep->dev->regs, ep);
513 spin_unlock_irqrestore(&ep->dev->lock, iflags);
518 /* Allocates request packet, called by gadget driver */
519 static struct usb_request *
520 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
522 struct udc_request *req;
523 struct udc_data_dma *dma_desc;
529 ep = container_of(usbep, struct udc_ep, ep);
531 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
532 req = kzalloc(sizeof(struct udc_request), gfp);
536 req->req.dma = DMA_DONT_USE;
537 INIT_LIST_HEAD(&req->queue);
540 /* ep0 in requests are allocated from data pool here */
541 dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp,
548 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
551 (unsigned long)req->td_phys);
552 /* prevent from using desc. - set HOST BUSY */
553 dma_desc->status = AMD_ADDBITS(dma_desc->status,
554 UDC_DMA_STP_STS_BS_HOST_BUSY,
556 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
557 req->td_data = dma_desc;
558 req->td_data_last = NULL;
565 /* frees pci pool descriptors of a DMA chain */
566 static void udc_free_dma_chain(struct udc *dev, struct udc_request *req)
568 struct udc_data_dma *td = req->td_data;
571 dma_addr_t addr_next = 0x00;
572 dma_addr_t addr = (dma_addr_t)td->next;
574 DBG(dev, "free chain req = %p\n", req);
576 /* do not free first desc., will be done by free for request */
577 for (i = 1; i < req->chain_len; i++) {
578 td = phys_to_virt(addr);
579 addr_next = (dma_addr_t)td->next;
580 dma_pool_free(dev->data_requests, td, addr);
585 /* Frees request packet, called by gadget driver */
587 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
590 struct udc_request *req;
592 if (!usbep || !usbreq)
595 ep = container_of(usbep, struct udc_ep, ep);
596 req = container_of(usbreq, struct udc_request, req);
597 VDBG(ep->dev, "free_req req=%p\n", req);
598 BUG_ON(!list_empty(&req->queue));
600 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
602 /* free dma chain if created */
603 if (req->chain_len > 1)
604 udc_free_dma_chain(ep->dev, req);
606 dma_pool_free(ep->dev->data_requests, req->td_data,
612 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
613 static void udc_init_bna_dummy(struct udc_request *req)
617 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
618 /* set next pointer to itself */
619 req->td_data->next = req->td_phys;
622 = AMD_ADDBITS(req->td_data->status,
623 UDC_DMA_STP_STS_BS_DMA_DONE,
626 pr_debug("bna desc = %p, sts = %08x\n",
627 req->td_data, req->td_data->status);
632 /* Allocate BNA dummy descriptor */
633 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
635 struct udc_request *req = NULL;
636 struct usb_request *_req = NULL;
638 /* alloc the dummy request */
639 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
641 req = container_of(_req, struct udc_request, req);
642 ep->bna_dummy_req = req;
643 udc_init_bna_dummy(req);
648 /* Write data to TX fifo for IN packets */
650 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
656 unsigned remaining = 0;
661 req_buf = req->buf + req->actual;
663 remaining = req->length - req->actual;
665 buf = (u32 *) req_buf;
667 bytes = ep->ep.maxpacket;
668 if (bytes > remaining)
672 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
673 writel(*(buf + i), ep->txfifo);
675 /* remaining bytes must be written by byte access */
676 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
677 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
681 /* dummy write confirm */
682 writel(0, &ep->regs->confirm);
685 /* Read dwords from RX fifo for OUT transfers */
686 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
690 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
692 for (i = 0; i < dwords; i++)
693 *(buf + i) = readl(dev->rxfifo);
697 /* Read bytes from RX fifo for OUT transfers */
698 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
703 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
706 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
707 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
709 /* remaining bytes must be read by byte access */
710 if (bytes % UDC_DWORD_BYTES) {
711 tmp = readl(dev->rxfifo);
712 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
713 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
714 tmp = tmp >> UDC_BITS_PER_BYTE;
721 /* Read data from RX fifo for OUT transfers */
723 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
728 unsigned finished = 0;
730 /* received number bytes */
731 bytes = readl(&ep->regs->sts);
732 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
734 buf_space = req->req.length - req->req.actual;
735 buf = req->req.buf + req->req.actual;
736 if (bytes > buf_space) {
737 if ((buf_space % ep->ep.maxpacket) != 0) {
739 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
740 ep->ep.name, bytes, buf_space);
741 req->req.status = -EOVERFLOW;
745 req->req.actual += bytes;
748 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
749 || ((req->req.actual == req->req.length) && !req->req.zero))
752 /* read rx fifo bytes */
753 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
754 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
759 /* Creates or re-inits a DMA chain */
760 static int udc_create_dma_chain(
762 struct udc_request *req,
763 unsigned long buf_len, gfp_t gfp_flags
766 unsigned long bytes = req->req.length;
769 struct udc_data_dma *td = NULL;
770 struct udc_data_dma *last = NULL;
771 unsigned long txbytes;
772 unsigned create_new_chain = 0;
775 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
777 dma_addr = DMA_DONT_USE;
779 /* unset L bit in first desc for OUT */
781 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
783 /* alloc only new desc's if not already available */
784 len = req->req.length / ep->ep.maxpacket;
785 if (req->req.length % ep->ep.maxpacket)
788 if (len > req->chain_len) {
789 /* shorter chain already allocated before */
790 if (req->chain_len > 1)
791 udc_free_dma_chain(ep->dev, req);
792 req->chain_len = len;
793 create_new_chain = 1;
797 /* gen. required number of descriptors and buffers */
798 for (i = buf_len; i < bytes; i += buf_len) {
799 /* create or determine next desc. */
800 if (create_new_chain) {
801 td = dma_pool_alloc(ep->dev->data_requests,
802 gfp_flags, &dma_addr);
807 } else if (i == buf_len) {
809 td = (struct udc_data_dma *)phys_to_virt(
813 td = (struct udc_data_dma *)phys_to_virt(last->next);
818 td->bufptr = req->req.dma + i; /* assign buffer */
823 if ((bytes - i) >= buf_len) {
830 /* link td and assign tx bytes */
832 if (create_new_chain)
833 req->td_data->next = dma_addr;
836 * req->td_data->next = virt_to_phys(td);
841 req->td_data->status =
842 AMD_ADDBITS(req->td_data->status,
844 UDC_DMA_IN_STS_TXBYTES);
846 td->status = AMD_ADDBITS(td->status,
848 UDC_DMA_IN_STS_TXBYTES);
851 if (create_new_chain)
852 last->next = dma_addr;
855 * last->next = virt_to_phys(td);
859 td->status = AMD_ADDBITS(td->status,
861 UDC_DMA_IN_STS_TXBYTES);
868 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
869 /* last desc. points to itself */
870 req->td_data_last = td;
876 /* create/re-init a DMA descriptor or a DMA descriptor chain */
877 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
882 VDBG(ep->dev, "prep_dma\n");
883 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
884 ep->num, req->td_data);
886 /* set buffer pointer */
887 req->td_data->bufptr = req->req.dma;
890 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
892 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
895 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
897 if (retval == -ENOMEM)
898 DBG(ep->dev, "Out of DMA memory\n");
902 if (req->req.length == ep->ep.maxpacket) {
904 req->td_data->status =
905 AMD_ADDBITS(req->td_data->status,
907 UDC_DMA_IN_STS_TXBYTES);
915 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
916 "maxpacket=%d ep%d\n",
917 use_dma_ppb, req->req.length,
918 ep->ep.maxpacket, ep->num);
920 * if bytes < max packet then tx bytes must
921 * be written in packet per buffer mode
923 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
924 || ep->num == UDC_EP0OUT_IX
925 || ep->num == UDC_EP0IN_IX) {
927 req->td_data->status =
928 AMD_ADDBITS(req->td_data->status,
930 UDC_DMA_IN_STS_TXBYTES);
931 /* reset frame num */
932 req->td_data->status =
933 AMD_ADDBITS(req->td_data->status,
935 UDC_DMA_IN_STS_FRAMENUM);
938 req->td_data->status =
939 AMD_ADDBITS(req->td_data->status,
940 UDC_DMA_STP_STS_BS_HOST_BUSY,
943 VDBG(ep->dev, "OUT set host ready\n");
945 req->td_data->status =
946 AMD_ADDBITS(req->td_data->status,
947 UDC_DMA_STP_STS_BS_HOST_READY,
950 /* clear NAK by writing CNAK */
952 tmp = readl(&ep->regs->ctl);
953 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
954 writel(tmp, &ep->regs->ctl);
956 UDC_QUEUE_CNAK(ep, ep->num);
964 /* Completes request packet ... caller MUST hold lock */
966 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
967 __releases(ep->dev->lock)
968 __acquires(ep->dev->lock)
973 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
978 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
983 /* set new status if pending */
984 if (req->req.status == -EINPROGRESS)
985 req->req.status = sts;
987 /* remove from ep queue */
988 list_del_init(&req->queue);
990 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
991 &req->req, req->req.length, ep->ep.name, sts);
993 spin_unlock(&dev->lock);
994 usb_gadget_giveback_request(&ep->ep, &req->req);
995 spin_lock(&dev->lock);
999 /* Iterates to the end of a DMA chain and returns last descriptor */
1000 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
1002 struct udc_data_dma *td;
1005 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
1006 td = phys_to_virt(td->next);
1012 /* Iterates to the end of a DMA chain and counts bytes received */
1013 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
1015 struct udc_data_dma *td;
1019 /* received number bytes */
1020 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
1022 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
1023 td = phys_to_virt(td->next);
1024 /* received number bytes */
1026 count += AMD_GETBITS(td->status,
1027 UDC_DMA_OUT_STS_RXBYTES);
1035 /* Enabling RX DMA */
1036 static void udc_set_rde(struct udc *dev)
1040 VDBG(dev, "udc_set_rde()\n");
1041 /* stop RDE timer */
1042 if (timer_pending(&udc_timer)) {
1044 mod_timer(&udc_timer, jiffies - 1);
1047 tmp = readl(&dev->regs->ctl);
1048 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1049 writel(tmp, &dev->regs->ctl);
1052 /* Queues a request packet, called by gadget driver */
1054 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1058 unsigned long iflags;
1060 struct udc_request *req;
1064 /* check the inputs */
1065 req = container_of(usbreq, struct udc_request, req);
1067 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1068 || !list_empty(&req->queue))
1071 ep = container_of(usbep, struct udc_ep, ep);
1072 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1075 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1078 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1081 /* map dma (usually done before) */
1083 VDBG(dev, "DMA map req %p\n", req);
1084 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1089 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1090 usbep->name, usbreq, usbreq->length,
1091 req->td_data, usbreq->buf);
1093 spin_lock_irqsave(&dev->lock, iflags);
1095 usbreq->status = -EINPROGRESS;
1098 /* on empty queue just do first transfer */
1099 if (list_empty(&ep->queue)) {
1101 if (usbreq->length == 0) {
1102 /* IN zlp's are handled by hardware */
1103 complete_req(ep, req, 0);
1104 VDBG(dev, "%s: zlp\n", ep->ep.name);
1106 * if set_config or set_intf is waiting for ack by zlp
1109 if (dev->set_cfg_not_acked) {
1110 tmp = readl(&dev->regs->ctl);
1111 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1112 writel(tmp, &dev->regs->ctl);
1113 dev->set_cfg_not_acked = 0;
1115 /* setup command is ACK'ed now by zlp */
1116 if (dev->waiting_zlp_ack_ep0in) {
1117 /* clear NAK by writing CNAK in EP0_IN */
1118 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1119 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1120 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1121 dev->ep[UDC_EP0IN_IX].naking = 0;
1122 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1124 dev->waiting_zlp_ack_ep0in = 0;
1129 retval = prep_dma(ep, req, GFP_ATOMIC);
1132 /* write desc pointer to enable DMA */
1134 /* set HOST READY */
1135 req->td_data->status =
1136 AMD_ADDBITS(req->td_data->status,
1137 UDC_DMA_IN_STS_BS_HOST_READY,
1141 /* disabled rx dma while descriptor update */
1143 /* stop RDE timer */
1144 if (timer_pending(&udc_timer)) {
1146 mod_timer(&udc_timer, jiffies - 1);
1149 tmp = readl(&dev->regs->ctl);
1150 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1151 writel(tmp, &dev->regs->ctl);
1155 * if BNA occurred then let BNA dummy desc.
1156 * point to current desc.
1158 if (ep->bna_occurred) {
1159 VDBG(dev, "copy to BNA dummy desc.\n");
1160 memcpy(ep->bna_dummy_req->td_data,
1162 sizeof(struct udc_data_dma));
1165 /* write desc pointer */
1166 writel(req->td_phys, &ep->regs->desptr);
1168 /* clear NAK by writing CNAK */
1170 tmp = readl(&ep->regs->ctl);
1171 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1172 writel(tmp, &ep->regs->ctl);
1174 UDC_QUEUE_CNAK(ep, ep->num);
1179 tmp = readl(&dev->regs->ep_irqmsk);
1180 tmp &= AMD_UNMASK_BIT(ep->num);
1181 writel(tmp, &dev->regs->ep_irqmsk);
1183 } else if (ep->in) {
1185 tmp = readl(&dev->regs->ep_irqmsk);
1186 tmp &= AMD_UNMASK_BIT(ep->num);
1187 writel(tmp, &dev->regs->ep_irqmsk);
1190 } else if (ep->dma) {
1193 * prep_dma not used for OUT ep's, this is not possible
1194 * for PPB modes, because of chain creation reasons
1197 retval = prep_dma(ep, req, GFP_ATOMIC);
1202 VDBG(dev, "list_add\n");
1203 /* add request to ep queue */
1206 list_add_tail(&req->queue, &ep->queue);
1208 /* open rxfifo if out data queued */
1213 if (ep->num != UDC_EP0OUT_IX)
1214 dev->data_ep_queued = 1;
1216 /* stop OUT naking */
1218 if (!use_dma && udc_rxfifo_pending) {
1219 DBG(dev, "udc_queue(): pending bytes in "
1220 "rxfifo after nyet\n");
1222 * read pending bytes afer nyet:
1225 if (udc_rxfifo_read(ep, req)) {
1227 complete_req(ep, req, 0);
1229 udc_rxfifo_pending = 0;
1236 spin_unlock_irqrestore(&dev->lock, iflags);
1240 /* Empty request queue of an endpoint; caller holds spinlock */
1241 void empty_req_queue(struct udc_ep *ep)
1243 struct udc_request *req;
1246 while (!list_empty(&ep->queue)) {
1247 req = list_entry(ep->queue.next,
1250 complete_req(ep, req, -ESHUTDOWN);
1253 EXPORT_SYMBOL_GPL(empty_req_queue);
1255 /* Dequeues a request packet, called by gadget driver */
1256 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1259 struct udc_request *req;
1261 unsigned long iflags;
1263 ep = container_of(usbep, struct udc_ep, ep);
1264 if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
1265 && ep->num != UDC_EP0OUT_IX)))
1268 req = container_of(usbreq, struct udc_request, req);
1270 spin_lock_irqsave(&ep->dev->lock, iflags);
1271 halted = ep->halted;
1273 /* request in processing or next one */
1274 if (ep->queue.next == &req->queue) {
1275 if (ep->dma && req->dma_going) {
1277 ep->cancel_transfer = 1;
1281 /* stop potential receive DMA */
1282 tmp = readl(&udc->regs->ctl);
1283 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1286 * Cancel transfer later in ISR
1287 * if descriptor was touched.
1289 dma_sts = AMD_GETBITS(req->td_data->status,
1290 UDC_DMA_OUT_STS_BS);
1291 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1292 ep->cancel_transfer = 1;
1294 udc_init_bna_dummy(ep->req);
1295 writel(ep->bna_dummy_req->td_phys,
1298 writel(tmp, &udc->regs->ctl);
1302 complete_req(ep, req, -ECONNRESET);
1303 ep->halted = halted;
1305 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1309 /* Halt or clear halt of endpoint */
1311 udc_set_halt(struct usb_ep *usbep, int halt)
1315 unsigned long iflags;
1321 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1323 ep = container_of(usbep, struct udc_ep, ep);
1324 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1326 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1329 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1330 /* halt or clear halt */
1333 ep->dev->stall_ep0in = 1;
1337 * rxfifo empty not taken into acount
1339 tmp = readl(&ep->regs->ctl);
1340 tmp |= AMD_BIT(UDC_EPCTL_S);
1341 writel(tmp, &ep->regs->ctl);
1344 /* setup poll timer */
1345 if (!timer_pending(&udc_pollstall_timer)) {
1346 udc_pollstall_timer.expires = jiffies +
1347 HZ * UDC_POLLSTALL_TIMER_USECONDS
1349 if (!stop_pollstall_timer) {
1350 DBG(ep->dev, "start polltimer\n");
1351 add_timer(&udc_pollstall_timer);
1356 /* ep is halted by set_halt() before */
1358 tmp = readl(&ep->regs->ctl);
1359 /* clear stall bit */
1360 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1361 /* clear NAK by writing CNAK */
1362 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1363 writel(tmp, &ep->regs->ctl);
1365 UDC_QUEUE_CNAK(ep, ep->num);
1368 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1372 /* gadget interface */
1373 static const struct usb_ep_ops udc_ep_ops = {
1374 .enable = udc_ep_enable,
1375 .disable = udc_ep_disable,
1377 .alloc_request = udc_alloc_request,
1378 .free_request = udc_free_request,
1381 .dequeue = udc_dequeue,
1383 .set_halt = udc_set_halt,
1384 /* fifo ops not implemented */
1387 /*-------------------------------------------------------------------------*/
1389 /* Get frame counter (not implemented) */
1390 static int udc_get_frame(struct usb_gadget *gadget)
1395 /* Initiates a remote wakeup */
1396 static int udc_remote_wakeup(struct udc *dev)
1398 unsigned long flags;
1401 DBG(dev, "UDC initiates remote wakeup\n");
1403 spin_lock_irqsave(&dev->lock, flags);
1405 tmp = readl(&dev->regs->ctl);
1406 tmp |= AMD_BIT(UDC_DEVCTL_RES);
1407 writel(tmp, &dev->regs->ctl);
1408 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
1409 writel(tmp, &dev->regs->ctl);
1411 spin_unlock_irqrestore(&dev->lock, flags);
1415 /* Remote wakeup gadget interface */
1416 static int udc_wakeup(struct usb_gadget *gadget)
1422 dev = container_of(gadget, struct udc, gadget);
1423 udc_remote_wakeup(dev);
1428 static int amd5536_udc_start(struct usb_gadget *g,
1429 struct usb_gadget_driver *driver);
1430 static int amd5536_udc_stop(struct usb_gadget *g);
1432 static const struct usb_gadget_ops udc_ops = {
1433 .wakeup = udc_wakeup,
1434 .get_frame = udc_get_frame,
1435 .udc_start = amd5536_udc_start,
1436 .udc_stop = amd5536_udc_stop,
1439 /* Setups endpoint parameters, adds endpoints to linked list */
1440 static void make_ep_lists(struct udc *dev)
1442 /* make gadget ep lists */
1443 INIT_LIST_HEAD(&dev->gadget.ep_list);
1444 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1445 &dev->gadget.ep_list);
1446 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1447 &dev->gadget.ep_list);
1448 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1449 &dev->gadget.ep_list);
1452 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1453 if (dev->gadget.speed == USB_SPEED_FULL)
1454 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1455 else if (dev->gadget.speed == USB_SPEED_HIGH)
1456 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1457 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1460 /* Inits UDC context */
1461 void udc_basic_init(struct udc *dev)
1465 DBG(dev, "udc_basic_init()\n");
1467 dev->gadget.speed = USB_SPEED_UNKNOWN;
1469 /* stop RDE timer */
1470 if (timer_pending(&udc_timer)) {
1472 mod_timer(&udc_timer, jiffies - 1);
1474 /* stop poll stall timer */
1475 if (timer_pending(&udc_pollstall_timer))
1476 mod_timer(&udc_pollstall_timer, jiffies - 1);
1478 tmp = readl(&dev->regs->ctl);
1479 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1480 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1481 writel(tmp, &dev->regs->ctl);
1483 /* enable dynamic CSR programming */
1484 tmp = readl(&dev->regs->cfg);
1485 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1486 /* set self powered */
1487 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1488 /* set remote wakeupable */
1489 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1490 writel(tmp, &dev->regs->cfg);
1494 dev->data_ep_enabled = 0;
1495 dev->data_ep_queued = 0;
1497 EXPORT_SYMBOL_GPL(udc_basic_init);
1499 /* init registers at driver load time */
1500 static int startup_registers(struct udc *dev)
1504 /* init controller by soft reset */
1505 udc_soft_reset(dev);
1507 /* mask not needed interrupts */
1508 udc_mask_unused_interrupts(dev);
1510 /* put into initial config */
1511 udc_basic_init(dev);
1512 /* link up all endpoints */
1513 udc_setup_endpoints(dev);
1516 tmp = readl(&dev->regs->cfg);
1518 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1520 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1521 writel(tmp, &dev->regs->cfg);
1526 /* Sets initial endpoint parameters */
1527 static void udc_setup_endpoints(struct udc *dev)
1533 DBG(dev, "udc_setup_endpoints()\n");
1535 /* read enum speed */
1536 tmp = readl(&dev->regs->sts);
1537 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1538 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1539 dev->gadget.speed = USB_SPEED_HIGH;
1540 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1541 dev->gadget.speed = USB_SPEED_FULL;
1543 /* set basic ep parameters */
1544 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1547 ep->ep.name = ep_info[tmp].name;
1548 ep->ep.caps = ep_info[tmp].caps;
1550 /* txfifo size is calculated at enable time */
1551 ep->txfifo = dev->txfifo;
1554 if (tmp < UDC_EPIN_NUM) {
1555 ep->fifo_depth = UDC_TXFIFO_SIZE;
1558 ep->fifo_depth = UDC_RXFIFO_SIZE;
1562 ep->regs = &dev->ep_regs[tmp];
1564 * ep will be reset only if ep was not enabled before to avoid
1565 * disabling ep interrupts when ENUM interrupt occurs but ep is
1566 * not enabled by gadget driver
1569 ep_init(dev->regs, ep);
1573 * ep->dma is not really used, just to indicate that
1574 * DMA is active: remove this
1575 * dma regs = dev control regs
1577 ep->dma = &dev->regs->ctl;
1579 /* nak OUT endpoints until enable - not for ep0 */
1580 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1581 && tmp > UDC_EPIN_NUM) {
1583 reg = readl(&dev->ep[tmp].regs->ctl);
1584 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1585 writel(reg, &dev->ep[tmp].regs->ctl);
1586 dev->ep[tmp].naking = 1;
1591 /* EP0 max packet */
1592 if (dev->gadget.speed == USB_SPEED_FULL) {
1593 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1594 UDC_FS_EP0IN_MAX_PKT_SIZE);
1595 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1596 UDC_FS_EP0OUT_MAX_PKT_SIZE);
1597 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1598 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1599 UDC_EP0IN_MAX_PKT_SIZE);
1600 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1601 UDC_EP0OUT_MAX_PKT_SIZE);
1605 * with suspend bug workaround, ep0 params for gadget driver
1606 * are set at gadget driver bind() call
1608 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1609 dev->ep[UDC_EP0IN_IX].halted = 0;
1610 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1612 /* init cfg/alt/int */
1613 dev->cur_config = 0;
1618 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1619 static void usb_connect(struct udc *dev)
1621 /* Return if already connected */
1625 dev_info(dev->dev, "USB Connect\n");
1629 /* put into initial config */
1630 udc_basic_init(dev);
1632 /* enable device setup interrupts */
1633 udc_enable_dev_setup_interrupts(dev);
1637 * Calls gadget with disconnect event and resets the UDC and makes
1638 * initial bringup to be ready for ep0 events
1640 static void usb_disconnect(struct udc *dev)
1642 /* Return if already disconnected */
1643 if (!dev->connected)
1646 dev_info(dev->dev, "USB Disconnect\n");
1650 /* mask interrupts */
1651 udc_mask_unused_interrupts(dev);
1653 /* REVISIT there doesn't seem to be a point to having this
1654 * talk to a tasklet ... do it directly, we already hold
1655 * the spinlock needed to process the disconnect.
1658 tasklet_schedule(&disconnect_tasklet);
1661 /* Tasklet for disconnect to be outside of interrupt context */
1662 static void udc_tasklet_disconnect(unsigned long par)
1664 struct udc *dev = (struct udc *)(*((struct udc **) par));
1667 DBG(dev, "Tasklet disconnect\n");
1668 spin_lock_irq(&dev->lock);
1671 spin_unlock(&dev->lock);
1672 dev->driver->disconnect(&dev->gadget);
1673 spin_lock(&dev->lock);
1676 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1677 empty_req_queue(&dev->ep[tmp]);
1683 &dev->ep[UDC_EP0IN_IX]);
1686 if (!soft_reset_occured) {
1687 /* init controller by soft reset */
1688 udc_soft_reset(dev);
1689 soft_reset_occured++;
1692 /* re-enable dev interrupts */
1693 udc_enable_dev_setup_interrupts(dev);
1694 /* back to full speed ? */
1695 if (use_fullspeed) {
1696 tmp = readl(&dev->regs->cfg);
1697 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1698 writel(tmp, &dev->regs->cfg);
1701 spin_unlock_irq(&dev->lock);
1704 /* Reset the UDC core */
1705 static void udc_soft_reset(struct udc *dev)
1707 unsigned long flags;
1709 DBG(dev, "Soft reset\n");
1711 * reset possible waiting interrupts, because int.
1712 * status is lost after soft reset,
1713 * ep int. status reset
1715 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1716 /* device int. status reset */
1717 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1719 /* Don't do this for Broadcom UDC since this is a reserved
1722 if (dev->chiprev != UDC_BCM_REV) {
1723 spin_lock_irqsave(&udc_irq_spinlock, flags);
1724 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1725 readl(&dev->regs->cfg);
1726 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1730 /* RDE timer callback to set RDE bit */
1731 static void udc_timer_function(struct timer_list *unused)
1735 spin_lock_irq(&udc_irq_spinlock);
1739 * open the fifo if fifo was filled on last timer call
1743 /* set RDE to receive setup data */
1744 tmp = readl(&udc->regs->ctl);
1745 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1746 writel(tmp, &udc->regs->ctl);
1748 } else if (readl(&udc->regs->sts)
1749 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1751 * if fifo empty setup polling, do not just
1754 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1756 add_timer(&udc_timer);
1759 * fifo contains data now, setup timer for opening
1760 * the fifo when timer expires to be able to receive
1761 * setup packets, when data packets gets queued by
1762 * gadget layer then timer will forced to expire with
1763 * set_rde=0 (RDE is set in udc_queue())
1766 /* debug: lhadmot_timer_start = 221070 */
1767 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1769 add_timer(&udc_timer);
1773 set_rde = -1; /* RDE was set by udc_queue() */
1774 spin_unlock_irq(&udc_irq_spinlock);
1780 /* Handle halt state, used in stall poll timer */
1781 static void udc_handle_halt_state(struct udc_ep *ep)
1784 /* set stall as long not halted */
1785 if (ep->halted == 1) {
1786 tmp = readl(&ep->regs->ctl);
1787 /* STALL cleared ? */
1788 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1790 * FIXME: MSC spec requires that stall remains
1791 * even on receivng of CLEAR_FEATURE HALT. So
1792 * we would set STALL again here to be compliant.
1793 * But with current mass storage drivers this does
1794 * not work (would produce endless host retries).
1795 * So we clear halt on CLEAR_FEATURE.
1797 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1798 tmp |= AMD_BIT(UDC_EPCTL_S);
1799 writel(tmp, &ep->regs->ctl);*/
1801 /* clear NAK by writing CNAK */
1802 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1803 writel(tmp, &ep->regs->ctl);
1805 UDC_QUEUE_CNAK(ep, ep->num);
1810 /* Stall timer callback to poll S bit and set it again after */
1811 static void udc_pollstall_timer_function(struct timer_list *unused)
1816 spin_lock_irq(&udc_stall_spinlock);
1818 * only one IN and OUT endpoints are handled
1821 ep = &udc->ep[UDC_EPIN_IX];
1822 udc_handle_halt_state(ep);
1825 /* OUT poll stall */
1826 ep = &udc->ep[UDC_EPOUT_IX];
1827 udc_handle_halt_state(ep);
1831 /* setup timer again when still halted */
1832 if (!stop_pollstall_timer && halted) {
1833 udc_pollstall_timer.expires = jiffies +
1834 HZ * UDC_POLLSTALL_TIMER_USECONDS
1836 add_timer(&udc_pollstall_timer);
1838 spin_unlock_irq(&udc_stall_spinlock);
1840 if (stop_pollstall_timer)
1841 complete(&on_pollstall_exit);
1844 /* Inits endpoint 0 so that SETUP packets are processed */
1845 static void activate_control_endpoints(struct udc *dev)
1849 DBG(dev, "activate_control_endpoints\n");
1852 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1853 tmp |= AMD_BIT(UDC_EPCTL_F);
1854 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1856 /* set ep0 directions */
1857 dev->ep[UDC_EP0IN_IX].in = 1;
1858 dev->ep[UDC_EP0OUT_IX].in = 0;
1860 /* set buffer size (tx fifo entries) of EP0_IN */
1861 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1862 if (dev->gadget.speed == USB_SPEED_FULL)
1863 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1864 UDC_EPIN_BUFF_SIZE);
1865 else if (dev->gadget.speed == USB_SPEED_HIGH)
1866 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1867 UDC_EPIN_BUFF_SIZE);
1868 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1870 /* set max packet size of EP0_IN */
1871 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1872 if (dev->gadget.speed == USB_SPEED_FULL)
1873 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1874 UDC_EP_MAX_PKT_SIZE);
1875 else if (dev->gadget.speed == USB_SPEED_HIGH)
1876 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1877 UDC_EP_MAX_PKT_SIZE);
1878 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1880 /* set max packet size of EP0_OUT */
1881 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1882 if (dev->gadget.speed == USB_SPEED_FULL)
1883 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1884 UDC_EP_MAX_PKT_SIZE);
1885 else if (dev->gadget.speed == USB_SPEED_HIGH)
1886 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1887 UDC_EP_MAX_PKT_SIZE);
1888 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1890 /* set max packet size of EP0 in UDC CSR */
1891 tmp = readl(&dev->csr->ne[0]);
1892 if (dev->gadget.speed == USB_SPEED_FULL)
1893 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1894 UDC_CSR_NE_MAX_PKT);
1895 else if (dev->gadget.speed == USB_SPEED_HIGH)
1896 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1897 UDC_CSR_NE_MAX_PKT);
1898 writel(tmp, &dev->csr->ne[0]);
1901 dev->ep[UDC_EP0OUT_IX].td->status |=
1902 AMD_BIT(UDC_DMA_OUT_STS_L);
1903 /* write dma desc address */
1904 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1905 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1906 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1907 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1908 /* stop RDE timer */
1909 if (timer_pending(&udc_timer)) {
1911 mod_timer(&udc_timer, jiffies - 1);
1913 /* stop pollstall timer */
1914 if (timer_pending(&udc_pollstall_timer))
1915 mod_timer(&udc_pollstall_timer, jiffies - 1);
1917 tmp = readl(&dev->regs->ctl);
1918 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1919 | AMD_BIT(UDC_DEVCTL_RDE)
1920 | AMD_BIT(UDC_DEVCTL_TDE);
1921 if (use_dma_bufferfill_mode)
1922 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1923 else if (use_dma_ppb_du)
1924 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1925 writel(tmp, &dev->regs->ctl);
1928 /* clear NAK by writing CNAK for EP0IN */
1929 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1930 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1931 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1932 dev->ep[UDC_EP0IN_IX].naking = 0;
1933 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1935 /* clear NAK by writing CNAK for EP0OUT */
1936 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1937 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1938 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1939 dev->ep[UDC_EP0OUT_IX].naking = 0;
1940 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1943 /* Make endpoint 0 ready for control traffic */
1944 static int setup_ep0(struct udc *dev)
1946 activate_control_endpoints(dev);
1947 /* enable ep0 interrupts */
1948 udc_enable_ep0_interrupts(dev);
1949 /* enable device setup interrupts */
1950 udc_enable_dev_setup_interrupts(dev);
1955 /* Called by gadget driver to register itself */
1956 static int amd5536_udc_start(struct usb_gadget *g,
1957 struct usb_gadget_driver *driver)
1959 struct udc *dev = to_amd5536_udc(g);
1962 driver->driver.bus = NULL;
1963 dev->driver = driver;
1965 /* Some gadget drivers use both ep0 directions.
1966 * NOTE: to gadget driver, ep0 is just one endpoint...
1968 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1969 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1971 /* get ready for ep0 traffic */
1975 tmp = readl(&dev->regs->ctl);
1976 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1977 writel(tmp, &dev->regs->ctl);
1984 /* shutdown requests and disconnect from gadget */
1986 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1987 __releases(dev->lock)
1988 __acquires(dev->lock)
1992 /* empty queues and init hardware */
1993 udc_basic_init(dev);
1995 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1996 empty_req_queue(&dev->ep[tmp]);
1998 udc_setup_endpoints(dev);
2001 /* Called by gadget driver to unregister itself */
2002 static int amd5536_udc_stop(struct usb_gadget *g)
2004 struct udc *dev = to_amd5536_udc(g);
2005 unsigned long flags;
2008 spin_lock_irqsave(&dev->lock, flags);
2009 udc_mask_unused_interrupts(dev);
2010 shutdown(dev, NULL);
2011 spin_unlock_irqrestore(&dev->lock, flags);
2016 tmp = readl(&dev->regs->ctl);
2017 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2018 writel(tmp, &dev->regs->ctl);
2023 /* Clear pending NAK bits */
2024 static void udc_process_cnak_queue(struct udc *dev)
2030 DBG(dev, "CNAK pending queue processing\n");
2031 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2032 if (cnak_pending & (1 << tmp)) {
2033 DBG(dev, "CNAK pending for ep%d\n", tmp);
2034 /* clear NAK by writing CNAK */
2035 reg = readl(&dev->ep[tmp].regs->ctl);
2036 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2037 writel(reg, &dev->ep[tmp].regs->ctl);
2038 dev->ep[tmp].naking = 0;
2039 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2042 /* ... and ep0out */
2043 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2044 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2045 /* clear NAK by writing CNAK */
2046 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2047 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2048 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2049 dev->ep[UDC_EP0OUT_IX].naking = 0;
2050 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2051 dev->ep[UDC_EP0OUT_IX].num);
2055 /* Enabling RX DMA after setup packet */
2056 static void udc_ep0_set_rde(struct udc *dev)
2060 * only enable RXDMA when no data endpoint enabled
2063 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2067 * setup timer for enabling RDE (to not enable
2068 * RXFIFO DMA for data endpoints to early)
2070 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2072 jiffies + HZ/UDC_RDE_TIMER_DIV;
2075 add_timer(&udc_timer);
2082 /* Interrupt handler for data OUT traffic */
2083 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2085 irqreturn_t ret_val = IRQ_NONE;
2088 struct udc_request *req;
2090 struct udc_data_dma *td = NULL;
2093 VDBG(dev, "ep%d irq\n", ep_ix);
2094 ep = &dev->ep[ep_ix];
2096 tmp = readl(&ep->regs->sts);
2099 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2100 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2101 ep->num, readl(&ep->regs->desptr));
2103 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2104 if (!ep->cancel_transfer)
2105 ep->bna_occurred = 1;
2107 ep->cancel_transfer = 0;
2108 ret_val = IRQ_HANDLED;
2113 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2114 dev_err(dev->dev, "HE ep%dout occurred\n", ep->num);
2117 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2118 ret_val = IRQ_HANDLED;
2122 if (!list_empty(&ep->queue)) {
2125 req = list_entry(ep->queue.next,
2126 struct udc_request, queue);
2129 udc_rxfifo_pending = 1;
2131 VDBG(dev, "req = %p\n", req);
2136 if (req && udc_rxfifo_read(ep, req)) {
2137 ret_val = IRQ_HANDLED;
2140 complete_req(ep, req, 0);
2142 if (!list_empty(&ep->queue) && !ep->halted) {
2143 req = list_entry(ep->queue.next,
2144 struct udc_request, queue);
2150 } else if (!ep->cancel_transfer && req) {
2151 ret_val = IRQ_HANDLED;
2153 /* check for DMA done */
2155 dma_done = AMD_GETBITS(req->td_data->status,
2156 UDC_DMA_OUT_STS_BS);
2157 /* packet per buffer mode - rx bytes */
2160 * if BNA occurred then recover desc. from
2163 if (ep->bna_occurred) {
2164 VDBG(dev, "Recover desc. from BNA dummy\n");
2165 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2166 sizeof(struct udc_data_dma));
2167 ep->bna_occurred = 0;
2168 udc_init_bna_dummy(ep->req);
2170 td = udc_get_last_dma_desc(req);
2171 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2173 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2174 /* buffer fill mode - rx bytes */
2176 /* received number bytes */
2177 count = AMD_GETBITS(req->td_data->status,
2178 UDC_DMA_OUT_STS_RXBYTES);
2179 VDBG(dev, "rx bytes=%u\n", count);
2180 /* packet per buffer mode - rx bytes */
2182 VDBG(dev, "req->td_data=%p\n", req->td_data);
2183 VDBG(dev, "last desc = %p\n", td);
2184 /* received number bytes */
2185 if (use_dma_ppb_du) {
2186 /* every desc. counts bytes */
2187 count = udc_get_ppbdu_rxbytes(req);
2189 /* last desc. counts bytes */
2190 count = AMD_GETBITS(td->status,
2191 UDC_DMA_OUT_STS_RXBYTES);
2192 if (!count && req->req.length
2193 == UDC_DMA_MAXPACKET) {
2195 * on 64k packets the RXBYTES
2198 count = UDC_DMA_MAXPACKET;
2201 VDBG(dev, "last desc rx bytes=%u\n", count);
2204 tmp = req->req.length - req->req.actual;
2206 if ((tmp % ep->ep.maxpacket) != 0) {
2207 DBG(dev, "%s: rx %db, space=%db\n",
2208 ep->ep.name, count, tmp);
2209 req->req.status = -EOVERFLOW;
2213 req->req.actual += count;
2215 /* complete request */
2216 complete_req(ep, req, 0);
2219 if (!list_empty(&ep->queue) && !ep->halted) {
2220 req = list_entry(ep->queue.next,
2224 * DMA may be already started by udc_queue()
2225 * called by gadget drivers completion
2226 * routine. This happens when queue
2227 * holds one request only.
2229 if (req->dma_going == 0) {
2231 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2233 /* write desc pointer */
2234 writel(req->td_phys,
2242 * implant BNA dummy descriptor to allow
2243 * RXFIFO opening by RDE
2245 if (ep->bna_dummy_req) {
2246 /* write desc pointer */
2247 writel(ep->bna_dummy_req->td_phys,
2249 ep->bna_occurred = 0;
2253 * schedule timer for setting RDE if queue
2254 * remains empty to allow ep0 packets pass
2258 && !timer_pending(&udc_timer)) {
2261 + HZ*UDC_RDE_TIMER_SECONDS;
2264 add_timer(&udc_timer);
2266 if (ep->num != UDC_EP0OUT_IX)
2267 dev->data_ep_queued = 0;
2272 * RX DMA must be reenabled for each desc in PPBDU mode
2273 * and must be enabled for PPBNDU mode in case of BNA
2278 } else if (ep->cancel_transfer) {
2279 ret_val = IRQ_HANDLED;
2280 ep->cancel_transfer = 0;
2283 /* check pending CNAKS */
2285 /* CNAk processing when rxfifo empty only */
2286 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2287 udc_process_cnak_queue(dev);
2290 /* clear OUT bits in ep status */
2291 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2296 /* Interrupt handler for data IN traffic */
2297 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2299 irqreturn_t ret_val = IRQ_NONE;
2303 struct udc_request *req;
2304 struct udc_data_dma *td;
2307 ep = &dev->ep[ep_ix];
2309 epsts = readl(&ep->regs->sts);
2312 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2314 "BNA ep%din occurred - DESPTR = %08lx\n",
2316 (unsigned long) readl(&ep->regs->desptr));
2319 writel(epsts, &ep->regs->sts);
2320 ret_val = IRQ_HANDLED;
2325 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2327 "HE ep%dn occurred - DESPTR = %08lx\n",
2328 ep->num, (unsigned long) readl(&ep->regs->desptr));
2331 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2332 ret_val = IRQ_HANDLED;
2336 /* DMA completion */
2337 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2338 VDBG(dev, "TDC set- completion\n");
2339 ret_val = IRQ_HANDLED;
2340 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2341 req = list_entry(ep->queue.next,
2342 struct udc_request, queue);
2344 * length bytes transferred
2345 * check dma done of last desc. in PPBDU mode
2347 if (use_dma_ppb_du) {
2348 td = udc_get_last_dma_desc(req);
2350 req->req.actual = req->req.length;
2352 /* assume all bytes transferred */
2353 req->req.actual = req->req.length;
2356 if (req->req.actual == req->req.length) {
2358 complete_req(ep, req, 0);
2360 /* further request available ? */
2361 if (list_empty(&ep->queue)) {
2362 /* disable interrupt */
2363 tmp = readl(&dev->regs->ep_irqmsk);
2364 tmp |= AMD_BIT(ep->num);
2365 writel(tmp, &dev->regs->ep_irqmsk);
2369 ep->cancel_transfer = 0;
2373 * status reg has IN bit set and TDC not set (if TDC was handled,
2374 * IN must not be handled (UDC defect) ?
2376 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2377 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2378 ret_val = IRQ_HANDLED;
2379 if (!list_empty(&ep->queue)) {
2381 req = list_entry(ep->queue.next,
2382 struct udc_request, queue);
2386 udc_txfifo_write(ep, &req->req);
2387 len = req->req.length - req->req.actual;
2388 if (len > ep->ep.maxpacket)
2389 len = ep->ep.maxpacket;
2390 req->req.actual += len;
2391 if (req->req.actual == req->req.length
2392 || (len != ep->ep.maxpacket)) {
2394 complete_req(ep, req, 0);
2397 } else if (req && !req->dma_going) {
2398 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2405 * unset L bit of first desc.
2408 if (use_dma_ppb && req->req.length >
2410 req->td_data->status &=
2415 /* write desc pointer */
2416 writel(req->td_phys, &ep->regs->desptr);
2418 /* set HOST READY */
2419 req->td_data->status =
2421 req->td_data->status,
2422 UDC_DMA_IN_STS_BS_HOST_READY,
2425 /* set poll demand bit */
2426 tmp = readl(&ep->regs->ctl);
2427 tmp |= AMD_BIT(UDC_EPCTL_P);
2428 writel(tmp, &ep->regs->ctl);
2432 } else if (!use_dma && ep->in) {
2433 /* disable interrupt */
2435 &dev->regs->ep_irqmsk);
2436 tmp |= AMD_BIT(ep->num);
2438 &dev->regs->ep_irqmsk);
2441 /* clear status bits */
2442 writel(epsts, &ep->regs->sts);
2449 /* Interrupt handler for Control OUT traffic */
2450 static irqreturn_t udc_control_out_isr(struct udc *dev)
2451 __releases(dev->lock)
2452 __acquires(dev->lock)
2454 irqreturn_t ret_val = IRQ_NONE;
2456 int setup_supported;
2460 struct udc_ep *ep_tmp;
2462 ep = &dev->ep[UDC_EP0OUT_IX];
2465 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2467 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2468 /* check BNA and clear if set */
2469 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2470 VDBG(dev, "ep0: BNA set\n");
2471 writel(AMD_BIT(UDC_EPSTS_BNA),
2472 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2473 ep->bna_occurred = 1;
2474 ret_val = IRQ_HANDLED;
2478 /* type of data: SETUP or DATA 0 bytes */
2479 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2480 VDBG(dev, "data_typ = %x\n", tmp);
2483 if (tmp == UDC_EPSTS_OUT_SETUP) {
2484 ret_val = IRQ_HANDLED;
2486 ep->dev->stall_ep0in = 0;
2487 dev->waiting_zlp_ack_ep0in = 0;
2489 /* set NAK for EP0_IN */
2490 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2491 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2492 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2493 dev->ep[UDC_EP0IN_IX].naking = 1;
2494 /* get setup data */
2497 /* clear OUT bits in ep status */
2498 writel(UDC_EPSTS_OUT_CLEAR,
2499 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2501 setup_data.data[0] =
2502 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2503 setup_data.data[1] =
2504 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2505 /* set HOST READY */
2506 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2507 UDC_DMA_STP_STS_BS_HOST_READY;
2510 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2513 /* determine direction of control data */
2514 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2515 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2517 udc_ep0_set_rde(dev);
2520 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2522 * implant BNA dummy descriptor to allow RXFIFO opening
2525 if (ep->bna_dummy_req) {
2526 /* write desc pointer */
2527 writel(ep->bna_dummy_req->td_phys,
2528 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2529 ep->bna_occurred = 0;
2533 dev->ep[UDC_EP0OUT_IX].naking = 1;
2535 * setup timer for enabling RDE (to not enable
2536 * RXFIFO DMA for data to early)
2539 if (!timer_pending(&udc_timer)) {
2540 udc_timer.expires = jiffies +
2541 HZ/UDC_RDE_TIMER_DIV;
2543 add_timer(&udc_timer);
2548 * mass storage reset must be processed here because
2549 * next packet may be a CLEAR_FEATURE HALT which would not
2550 * clear the stall bit when no STALL handshake was received
2551 * before (autostall can cause this)
2553 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2554 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2555 DBG(dev, "MSC Reset\n");
2558 * only one IN and OUT endpoints are handled
2560 ep_tmp = &udc->ep[UDC_EPIN_IX];
2561 udc_set_halt(&ep_tmp->ep, 0);
2562 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2563 udc_set_halt(&ep_tmp->ep, 0);
2566 /* call gadget with setup data received */
2567 spin_unlock(&dev->lock);
2568 setup_supported = dev->driver->setup(&dev->gadget,
2569 &setup_data.request);
2570 spin_lock(&dev->lock);
2572 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2573 /* ep0 in returns data (not zlp) on IN phase */
2574 if (setup_supported >= 0 && setup_supported <
2575 UDC_EP0IN_MAXPACKET) {
2576 /* clear NAK by writing CNAK in EP0_IN */
2577 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2578 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2579 dev->ep[UDC_EP0IN_IX].naking = 0;
2580 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2582 /* if unsupported request then stall */
2583 } else if (setup_supported < 0) {
2584 tmp |= AMD_BIT(UDC_EPCTL_S);
2585 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2587 dev->waiting_zlp_ack_ep0in = 1;
2590 /* clear NAK by writing CNAK in EP0_OUT */
2592 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2593 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2594 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2595 dev->ep[UDC_EP0OUT_IX].naking = 0;
2596 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2600 /* clear OUT bits in ep status */
2601 writel(UDC_EPSTS_OUT_CLEAR,
2602 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2605 /* data packet 0 bytes */
2606 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2607 /* clear OUT bits in ep status */
2608 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2610 /* get setup data: only 0 packet */
2612 /* no req if 0 packet, just reactivate */
2613 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2616 /* set HOST READY */
2617 dev->ep[UDC_EP0OUT_IX].td->status =
2619 dev->ep[UDC_EP0OUT_IX].td->status,
2620 UDC_DMA_OUT_STS_BS_HOST_READY,
2621 UDC_DMA_OUT_STS_BS);
2623 udc_ep0_set_rde(dev);
2624 ret_val = IRQ_HANDLED;
2628 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2629 /* re-program desc. pointer for possible ZLPs */
2630 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2631 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2633 udc_ep0_set_rde(dev);
2637 /* received number bytes */
2638 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2639 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2640 /* out data for fifo mode not working */
2643 /* 0 packet or real data ? */
2645 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2647 /* dummy read confirm */
2648 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2649 ret_val = IRQ_HANDLED;
2654 /* check pending CNAKS */
2656 /* CNAk processing when rxfifo empty only */
2657 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2658 udc_process_cnak_queue(dev);
2665 /* Interrupt handler for Control IN traffic */
2666 static irqreturn_t udc_control_in_isr(struct udc *dev)
2668 irqreturn_t ret_val = IRQ_NONE;
2671 struct udc_request *req;
2674 ep = &dev->ep[UDC_EP0IN_IX];
2677 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2679 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2680 /* DMA completion */
2681 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2682 VDBG(dev, "isr: TDC clear\n");
2683 ret_val = IRQ_HANDLED;
2686 writel(AMD_BIT(UDC_EPSTS_TDC),
2687 &dev->ep[UDC_EP0IN_IX].regs->sts);
2689 /* status reg has IN bit set ? */
2690 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2691 ret_val = IRQ_HANDLED;
2695 writel(AMD_BIT(UDC_EPSTS_IN),
2696 &dev->ep[UDC_EP0IN_IX].regs->sts);
2698 if (dev->stall_ep0in) {
2699 DBG(dev, "stall ep0in\n");
2701 tmp = readl(&ep->regs->ctl);
2702 tmp |= AMD_BIT(UDC_EPCTL_S);
2703 writel(tmp, &ep->regs->ctl);
2705 if (!list_empty(&ep->queue)) {
2707 req = list_entry(ep->queue.next,
2708 struct udc_request, queue);
2711 /* write desc pointer */
2712 writel(req->td_phys, &ep->regs->desptr);
2713 /* set HOST READY */
2714 req->td_data->status =
2716 req->td_data->status,
2717 UDC_DMA_STP_STS_BS_HOST_READY,
2718 UDC_DMA_STP_STS_BS);
2720 /* set poll demand bit */
2722 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2723 tmp |= AMD_BIT(UDC_EPCTL_P);
2725 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2727 /* all bytes will be transferred */
2728 req->req.actual = req->req.length;
2731 complete_req(ep, req, 0);
2735 udc_txfifo_write(ep, &req->req);
2737 /* lengh bytes transferred */
2738 len = req->req.length - req->req.actual;
2739 if (len > ep->ep.maxpacket)
2740 len = ep->ep.maxpacket;
2742 req->req.actual += len;
2743 if (req->req.actual == req->req.length
2744 || (len != ep->ep.maxpacket)) {
2746 complete_req(ep, req, 0);
2753 dev->stall_ep0in = 0;
2756 writel(AMD_BIT(UDC_EPSTS_IN),
2757 &dev->ep[UDC_EP0IN_IX].regs->sts);
2765 /* Interrupt handler for global device events */
2766 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2767 __releases(dev->lock)
2768 __acquires(dev->lock)
2770 irqreturn_t ret_val = IRQ_NONE;
2777 /* SET_CONFIG irq ? */
2778 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2779 ret_val = IRQ_HANDLED;
2781 /* read config value */
2782 tmp = readl(&dev->regs->sts);
2783 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2784 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2785 dev->cur_config = cfg;
2786 dev->set_cfg_not_acked = 1;
2788 /* make usb request for gadget driver */
2789 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2790 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2791 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2793 /* programm the NE registers */
2794 for (i = 0; i < UDC_EP_NUM; i++) {
2798 /* ep ix in UDC CSR register space */
2799 udc_csr_epix = ep->num;
2804 /* ep ix in UDC CSR register space */
2805 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2808 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2810 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2813 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2815 /* clear stall bits */
2817 tmp = readl(&ep->regs->ctl);
2818 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2819 writel(tmp, &ep->regs->ctl);
2821 /* call gadget zero with setup data received */
2822 spin_unlock(&dev->lock);
2823 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2824 spin_lock(&dev->lock);
2826 } /* SET_INTERFACE ? */
2827 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2828 ret_val = IRQ_HANDLED;
2830 dev->set_cfg_not_acked = 1;
2831 /* read interface and alt setting values */
2832 tmp = readl(&dev->regs->sts);
2833 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2834 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2836 /* make usb request for gadget driver */
2837 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2838 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2839 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2840 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2841 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2843 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2844 dev->cur_alt, dev->cur_intf);
2846 /* programm the NE registers */
2847 for (i = 0; i < UDC_EP_NUM; i++) {
2851 /* ep ix in UDC CSR register space */
2852 udc_csr_epix = ep->num;
2857 /* ep ix in UDC CSR register space */
2858 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2863 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2865 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2867 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2869 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2872 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2874 /* clear stall bits */
2876 tmp = readl(&ep->regs->ctl);
2877 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2878 writel(tmp, &ep->regs->ctl);
2881 /* call gadget zero with setup data received */
2882 spin_unlock(&dev->lock);
2883 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2884 spin_lock(&dev->lock);
2887 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2888 DBG(dev, "USB Reset interrupt\n");
2889 ret_val = IRQ_HANDLED;
2891 /* allow soft reset when suspend occurs */
2892 soft_reset_occured = 0;
2894 dev->waiting_zlp_ack_ep0in = 0;
2895 dev->set_cfg_not_acked = 0;
2897 /* mask not needed interrupts */
2898 udc_mask_unused_interrupts(dev);
2900 /* call gadget to resume and reset configs etc. */
2901 spin_unlock(&dev->lock);
2902 if (dev->sys_suspended && dev->driver->resume) {
2903 dev->driver->resume(&dev->gadget);
2904 dev->sys_suspended = 0;
2906 usb_gadget_udc_reset(&dev->gadget, dev->driver);
2907 spin_lock(&dev->lock);
2909 /* disable ep0 to empty req queue */
2910 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2911 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2913 /* soft reset when rxfifo not empty */
2914 tmp = readl(&dev->regs->sts);
2915 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2916 && !soft_reset_after_usbreset_occured) {
2917 udc_soft_reset(dev);
2918 soft_reset_after_usbreset_occured++;
2922 * DMA reset to kill potential old DMA hw hang,
2923 * POLL bit is already reset by ep_init() through
2926 DBG(dev, "DMA machine reset\n");
2927 tmp = readl(&dev->regs->cfg);
2928 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2929 writel(tmp, &dev->regs->cfg);
2931 /* put into initial config */
2932 udc_basic_init(dev);
2934 /* enable device setup interrupts */
2935 udc_enable_dev_setup_interrupts(dev);
2937 /* enable suspend interrupt */
2938 tmp = readl(&dev->regs->irqmsk);
2939 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2940 writel(tmp, &dev->regs->irqmsk);
2943 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2944 DBG(dev, "USB Suspend interrupt\n");
2945 ret_val = IRQ_HANDLED;
2946 if (dev->driver->suspend) {
2947 spin_unlock(&dev->lock);
2948 dev->sys_suspended = 1;
2949 dev->driver->suspend(&dev->gadget);
2950 spin_lock(&dev->lock);
2953 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2954 DBG(dev, "ENUM interrupt\n");
2955 ret_val = IRQ_HANDLED;
2956 soft_reset_after_usbreset_occured = 0;
2958 /* disable ep0 to empty req queue */
2959 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2960 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2962 /* link up all endpoints */
2963 udc_setup_endpoints(dev);
2964 dev_info(dev->dev, "Connect: %s\n",
2965 usb_speed_string(dev->gadget.speed));
2968 activate_control_endpoints(dev);
2970 /* enable ep0 interrupts */
2971 udc_enable_ep0_interrupts(dev);
2973 /* session valid change interrupt */
2974 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2975 DBG(dev, "USB SVC interrupt\n");
2976 ret_val = IRQ_HANDLED;
2978 /* check that session is not valid to detect disconnect */
2979 tmp = readl(&dev->regs->sts);
2980 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2981 /* disable suspend interrupt */
2982 tmp = readl(&dev->regs->irqmsk);
2983 tmp |= AMD_BIT(UDC_DEVINT_US);
2984 writel(tmp, &dev->regs->irqmsk);
2985 DBG(dev, "USB Disconnect (session valid low)\n");
2986 /* cleanup on disconnect */
2987 usb_disconnect(udc);
2995 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2996 irqreturn_t udc_irq(int irq, void *pdev)
2998 struct udc *dev = pdev;
3002 irqreturn_t ret_val = IRQ_NONE;
3004 spin_lock(&dev->lock);
3006 /* check for ep irq */
3007 reg = readl(&dev->regs->ep_irqsts);
3009 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3010 ret_val |= udc_control_out_isr(dev);
3011 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3012 ret_val |= udc_control_in_isr(dev);
3018 for (i = 1; i < UDC_EP_NUM; i++) {
3020 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3023 /* clear irq status */
3024 writel(ep_irq, &dev->regs->ep_irqsts);
3026 /* irq for out ep ? */
3027 if (i > UDC_EPIN_NUM)
3028 ret_val |= udc_data_out_isr(dev, i);
3030 ret_val |= udc_data_in_isr(dev, i);
3036 /* check for dev irq */
3037 reg = readl(&dev->regs->irqsts);
3040 writel(reg, &dev->regs->irqsts);
3041 ret_val |= udc_dev_isr(dev, reg);
3045 spin_unlock(&dev->lock);
3048 EXPORT_SYMBOL_GPL(udc_irq);
3050 /* Tears down device */
3051 void gadget_release(struct device *pdev)
3053 struct amd5536udc *dev = dev_get_drvdata(pdev);
3056 EXPORT_SYMBOL_GPL(gadget_release);
3058 /* Cleanup on device remove */
3059 void udc_remove(struct udc *dev)
3063 if (timer_pending(&udc_timer))
3064 wait_for_completion(&on_exit);
3065 del_timer_sync(&udc_timer);
3066 /* remove pollstall timer */
3067 stop_pollstall_timer++;
3068 if (timer_pending(&udc_pollstall_timer))
3069 wait_for_completion(&on_pollstall_exit);
3070 del_timer_sync(&udc_pollstall_timer);
3073 EXPORT_SYMBOL_GPL(udc_remove);
3075 /* free all the dma pools */
3076 void free_dma_pools(struct udc *dev)
3078 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td,
3079 dev->ep[UDC_EP0OUT_IX].td_phys);
3080 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3081 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3082 dma_pool_destroy(dev->stp_requests);
3083 dma_pool_destroy(dev->data_requests);
3085 EXPORT_SYMBOL_GPL(free_dma_pools);
3087 /* create dma pools on init */
3088 int init_dma_pools(struct udc *dev)
3090 struct udc_stp_dma *td_stp;
3091 struct udc_data_dma *td_data;
3094 /* consistent DMA mode setting ? */
3096 use_dma_bufferfill_mode = 0;
3099 use_dma_bufferfill_mode = 1;
3103 dev->data_requests = dma_pool_create("data_requests", dev->dev,
3104 sizeof(struct udc_data_dma), 0, 0);
3105 if (!dev->data_requests) {
3106 DBG(dev, "can't get request data pool\n");
3110 /* EP0 in dma regs = dev control regs */
3111 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3113 /* dma desc for setup data */
3114 dev->stp_requests = dma_pool_create("setup requests", dev->dev,
3115 sizeof(struct udc_stp_dma), 0, 0);
3116 if (!dev->stp_requests) {
3117 DBG(dev, "can't get stp request pool\n");
3119 goto err_create_dma_pool;
3122 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3123 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3128 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3130 /* data: 0 packets !? */
3131 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3132 &dev->ep[UDC_EP0OUT_IX].td_phys);
3135 goto err_alloc_phys;
3137 dev->ep[UDC_EP0OUT_IX].td = td_data;
3141 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3142 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3144 dma_pool_destroy(dev->stp_requests);
3145 dev->stp_requests = NULL;
3146 err_create_dma_pool:
3147 dma_pool_destroy(dev->data_requests);
3148 dev->data_requests = NULL;
3151 EXPORT_SYMBOL_GPL(init_dma_pools);
3154 int udc_probe(struct udc *dev)
3160 /* device struct setup */
3161 dev->gadget.ops = &udc_ops;
3163 dev_set_name(&dev->gadget.dev, "gadget");
3164 dev->gadget.name = name;
3165 dev->gadget.max_speed = USB_SPEED_HIGH;
3167 /* init registers, interrupts, ... */
3168 startup_registers(dev);
3170 dev_info(dev->dev, "%s\n", mod_desc);
3172 snprintf(tmp, sizeof(tmp), "%d", dev->irq);
3174 /* Print this device info for AMD chips only*/
3175 if (dev->chiprev == UDC_HSA0_REV ||
3176 dev->chiprev == UDC_HSB1_REV) {
3177 dev_info(dev->dev, "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3178 tmp, dev->phys_addr, dev->chiprev,
3179 (dev->chiprev == UDC_HSA0_REV) ?
3181 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3182 if (dev->chiprev == UDC_HSA0_REV) {
3183 dev_err(dev->dev, "chip revision is A0; too old\n");
3188 "driver version: %s(for Geode5536 B1)\n", tmp);
3193 retval = usb_add_gadget_udc_release(udc->dev, &dev->gadget,
3199 timer_setup(&udc_timer, udc_timer_function, 0);
3200 timer_setup(&udc_pollstall_timer, udc_pollstall_timer_function, 0);
3203 reg = readl(&dev->regs->ctl);
3204 reg |= AMD_BIT(UDC_DEVCTL_SD);
3205 writel(reg, &dev->regs->ctl);
3207 /* print dev register info */
3215 EXPORT_SYMBOL_GPL(udc_probe);
3217 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3218 MODULE_AUTHOR("Thomas Dahlmann");
3219 MODULE_LICENSE("GPL");