drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/list.h>
  20 #include <linux/dma-mapping.h>
  21
  22 #include <linux/usb/ch9.h>
  23 #include <linux/usb/gadget.h>
  24
  25 #include "debug.h"
  26 #include "core.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 #define DWC3_ALIGN_FRAME(d, n)  (((d)->frame_number + ((d)->interval * (n))) \
  31                                         & ~((d)->interval - 1))
  32
  33 /**
  34  * dwc3_gadget_set_test_mode - enables usb2 test modes
  35  * @dwc: pointer to our context structure
  36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  37  *
  38  * Caller should take care of locking. This function will return 0 on
  39  * success or -EINVAL if wrong Test Selector is passed.
  40  */
  41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  42 {
  43         u32             reg;
  44
  45         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  46         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  47
  48         switch (mode) {
  49         case USB_TEST_J:
  50         case USB_TEST_K:
  51         case USB_TEST_SE0_NAK:
  52         case USB_TEST_PACKET:
  53         case USB_TEST_FORCE_ENABLE:
  54                 reg |= mode << 1;
  55                 break;
  56         default:
  57                 return -EINVAL;
  58         }
  59
  60         dwc3_gadget_dctl_write_safe(dwc, reg);
  61
  62         return 0;
  63 }
  64
  65 /**
  66  * dwc3_gadget_get_link_state - gets current state of usb link
  67  * @dwc: pointer to our context structure
  68  *
  69  * Caller should take care of locking. This function will
  70  * return the link state on success (>= 0) or -ETIMEDOUT.
  71  */
  72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  73 {
  74         u32             reg;
  75
  76         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  77
  78         return DWC3_DSTS_USBLNKST(reg);
  79 }
  80
  81 /**
  82  * dwc3_gadget_set_link_state - sets usb link to a particular state
  83  * @dwc: pointer to our context structure
  84  * @state: the state to put link into
  85  *
  86  * Caller should take care of locking. This function will
  87  * return 0 on success or -ETIMEDOUT.
  88  */
  89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  90 {
  91         int             retries = 10000;
  92         u32             reg;
  93
  94         /*
  95          * Wait until device controller is ready. Only applies to 1.94a and
  96          * later RTL.
  97          */
  98         if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
  99                 while (--retries) {
 100                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 101                         if (reg & DWC3_DSTS_DCNRD)
 102                                 udelay(5);
 103                         else
 104                                 break;
 105                 }
 106
 107                 if (retries <= 0)
 108                         return -ETIMEDOUT;
 109         }
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 113
 114         /* set no action before sending new link state change */
 115         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 116
 117         /* set requested state */
 118         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 119         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 120
 121         /*
 122          * The following code is racy when called from dwc3_gadget_wakeup,
 123          * and is not needed, at least on newer versions
 124          */
 125         if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
 126                 return 0;
 127
 128         /* wait for a change in DSTS */
 129         retries = 10000;
 130         while (--retries) {
 131                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 132
 133                 if (DWC3_DSTS_USBLNKST(reg) == state)
 134                         return 0;
 135
 136                 udelay(5);
 137         }
 138
 139         return -ETIMEDOUT;
 140 }
 141
 142 static void dwc3_ep0_reset_state(struct dwc3 *dwc)
 143 {
 144         unsigned int    dir;
 145
 146         if (dwc->ep0state != EP0_SETUP_PHASE) {
 147                 dir = !!dwc->ep0_expect_in;
 148                 if (dwc->ep0state == EP0_DATA_PHASE)
 149                         dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
 150                 else
 151                         dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
 152
 153                 dwc->eps[0]->trb_enqueue = 0;
 154                 dwc->eps[1]->trb_enqueue = 0;
 155
 156                 dwc3_ep0_stall_and_restart(dwc);
 157         }
 158 }
 159
 160 /**
 161  * dwc3_ep_inc_trb - increment a trb index.
 162  * @index: Pointer to the TRB index to increment.
 163  *
 164  * The index should never point to the link TRB. After incrementing,
 165  * if it is point to the link TRB, wrap around to the beginning. The
 166  * link TRB is always at the last TRB entry.
 167  */
 168 static void dwc3_ep_inc_trb(u8 *index)
 169 {
 170         (*index)++;
 171         if (*index == (DWC3_TRB_NUM - 1))
 172                 *index = 0;
 173 }
 174
 175 /**
 176  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
 177  * @dep: The endpoint whose enqueue pointer we're incrementing
 178  */
 179 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 180 {
 181         dwc3_ep_inc_trb(&dep->trb_enqueue);
 182 }
 183
 184 /**
 185  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
 186  * @dep: The endpoint whose enqueue pointer we're incrementing
 187  */
 188 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 189 {
 190         dwc3_ep_inc_trb(&dep->trb_dequeue);
 191 }
 192
 193 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
 194                 struct dwc3_request *req, int status)
 195 {
 196         struct dwc3                     *dwc = dep->dwc;
 197
 198         list_del(&req->list);
 199         req->remaining = 0;
 200         req->needs_extra_trb = false;
 201         req->num_trbs = 0;
 202
 203         if (req->request.status == -EINPROGRESS)
 204                 req->request.status = status;
 205
 206         if (req->trb)
 207                 usb_gadget_unmap_request_by_dev(dwc->sysdev,
 208                                 &req->request, req->direction);
 209
 210         req->trb = NULL;
 211         trace_dwc3_gadget_giveback(req);
 212
 213         if (dep->number > 1)
 214                 pm_runtime_put(dwc->dev);
 215 }
 216
 217 /**
 218  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
 219  * @dep: The endpoint to whom the request belongs to
 220  * @req: The request we're giving back
 221  * @status: completion code for the request
 222  *
 223  * Must be called with controller's lock held and interrupts disabled. This
 224  * function will unmap @req and call its ->complete() callback to notify upper
 225  * layers that it has completed.
 226  */
 227 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 228                 int status)
 229 {
 230         struct dwc3                     *dwc = dep->dwc;
 231
 232         dwc3_gadget_del_and_unmap_request(dep, req, status);
 233         req->status = DWC3_REQUEST_STATUS_COMPLETED;
 234
 235         spin_unlock(&dwc->lock);
 236         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 237         spin_lock(&dwc->lock);
 238 }
 239
 240 /**
 241  * dwc3_send_gadget_generic_command - issue a generic command for the controller
 242  * @dwc: pointer to the controller context
 243  * @cmd: the command to be issued
 244  * @param: command parameter
 245  *
 246  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
 247  * and wait for its completion.
 248  */
 249 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
 250                 u32 param)
 251 {
 252         u32             timeout = 500;
 253         int             status = 0;
 254         int             ret = 0;
 255         u32             reg;
 256
 257         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 258         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 259
 260         do {
 261                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 262                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 263                         status = DWC3_DGCMD_STATUS(reg);
 264                         if (status)
 265                                 ret = -EINVAL;
 266                         break;
 267                 }
 268         } while (--timeout);
 269
 270         if (!timeout) {
 271                 ret = -ETIMEDOUT;
 272                 status = -ETIMEDOUT;
 273         }
 274
 275         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 276
 277         return ret;
 278 }
 279
 280 static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
 281
 282 /**
 283  * dwc3_send_gadget_ep_cmd - issue an endpoint command
 284  * @dep: the endpoint to which the command is going to be issued
 285  * @cmd: the command to be issued
 286  * @params: parameters to the command
 287  *
 288  * Caller should handle locking. This function will issue @cmd with given
 289  * @params to @dep and wait for its completion.
 290  */
 291 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
 292                 struct dwc3_gadget_ep_cmd_params *params)
 293 {
 294         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 295         struct dwc3             *dwc = dep->dwc;
 296         u32                     timeout = 5000;
 297         u32                     saved_config = 0;
 298         u32                     reg;
 299
 300         int                     cmd_status = 0;
 301         int                     ret = -EINVAL;
 302
 303         /*
 304          * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
 305          * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
 306          * endpoint command.
 307          *
 308          * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
 309          * settings. Restore them after the command is completed.
 310          *
 311          * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
 312          */
 313         if (dwc->gadget->speed <= USB_SPEED_HIGH ||
 314             DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
 315                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 316                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 317                         saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
 318                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 319                 }
 320
 321                 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
 322                         saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 323                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 324                 }
 325
 326                 if (saved_config)
 327                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 328         }
 329
 330         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 331                 int link_state;
 332
 333                 /*
 334                  * Initiate remote wakeup if the link state is in U3 when
 335                  * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
 336                  * link state is in U1/U2, no remote wakeup is needed. The Start
 337                  * Transfer command will initiate the link recovery.
 338                  */
 339                 link_state = dwc3_gadget_get_link_state(dwc);
 340                 switch (link_state) {
 341                 case DWC3_LINK_STATE_U2:
 342                         if (dwc->gadget->speed >= USB_SPEED_SUPER)
 343                                 break;
 344
 345                         fallthrough;
 346                 case DWC3_LINK_STATE_U3:
 347                         ret = __dwc3_gadget_wakeup(dwc, false);
 348                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 349                                         ret);
 350                         break;
 351                 }
 352         }
 353
 354         /*
 355          * For some commands such as Update Transfer command, DEPCMDPARn
 356          * registers are reserved. Since the driver often sends Update Transfer
 357          * command, don't write to DEPCMDPARn to avoid register write delays and
 358          * improve performance.
 359          */
 360         if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
 361                 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 362                 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 363                 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 364         }
 365
 366         /*
 367          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
 368          * not relying on XferNotReady, we can make use of a special "No
 369          * Response Update Transfer" command where we should clear both CmdAct
 370          * and CmdIOC bits.
 371          *
 372          * With this, we don't need to wait for command completion and can
 373          * straight away issue further commands to the endpoint.
 374          *
 375          * NOTICE: We're making an assumption that control endpoints will never
 376          * make use of Update Transfer command. This is a safe assumption
 377          * because we can never have more than one request at a time with
 378          * Control Endpoints. If anybody changes that assumption, this chunk
 379          * needs to be updated accordingly.
 380          */
 381         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
 382                         !usb_endpoint_xfer_isoc(desc))
 383                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
 384         else
 385                 cmd |= DWC3_DEPCMD_CMDACT;
 386
 387         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
 388
 389         if (!(cmd & DWC3_DEPCMD_CMDACT) ||
 390                 (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
 391                 !(cmd & DWC3_DEPCMD_CMDIOC))) {
 392                 ret = 0;
 393                 goto skip_status;
 394         }
 395
 396         do {
 397                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 398                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 399                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 400
 401                         switch (cmd_status) {
 402                         case 0:
 403                                 ret = 0;
 404                                 break;
 405                         case DEPEVT_TRANSFER_NO_RESOURCE:
 406                                 dev_WARN(dwc->dev, "No resource for %s\n",
 407                                          dep->name);
 408                                 ret = -EINVAL;
 409                                 break;
 410                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 411                                 /*
 412                                  * SW issues START TRANSFER command to
 413                                  * isochronous ep with future frame interval. If
 414                                  * future interval time has already passed when
 415                                  * core receives the command, it will respond
 416                                  * with an error status of 'Bus Expiry'.
 417                                  *
 418                                  * Instead of always returning -EINVAL, let's
 419                                  * give a hint to the gadget driver that this is
 420                                  * the case by returning -EAGAIN.
 421                                  */
 422                                 ret = -EAGAIN;
 423                                 break;
 424                         default:
 425                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 426                         }
 427
 428                         break;
 429                 }
 430         } while (--timeout);
 431
 432         if (timeout == 0) {
 433                 ret = -ETIMEDOUT;
 434                 cmd_status = -ETIMEDOUT;
 435         }
 436
 437 skip_status:
 438         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 439
 440         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 441                 if (ret == 0)
 442                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
 443
 444                 if (ret != -ETIMEDOUT)
 445                         dwc3_gadget_ep_get_transfer_index(dep);
 446         }
 447
 448         if (saved_config) {
 449                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 450                 reg |= saved_config;
 451                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 452         }
 453
 454         return ret;
 455 }
 456
 457 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 458 {
 459         struct dwc3 *dwc = dep->dwc;
 460         struct dwc3_gadget_ep_cmd_params params;
 461         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 462
 463         /*
 464          * As of core revision 2.60a the recommended programming model
 465          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 466          * command for IN endpoints. This is to prevent an issue where
 467          * some (non-compliant) hosts may not send ACK TPs for pending
 468          * IN transfers due to a mishandled error condition. Synopsys
 469          * STAR 9000614252.
 470          */
 471         if (dep->direction &&
 472             !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
 473             (dwc->gadget->speed >= USB_SPEED_SUPER))
 474                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 475
 476         memset(&params, 0, sizeof(params));
 477
 478         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 479 }
 480
 481 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 482                 struct dwc3_trb *trb)
 483 {
 484         u32             offset = (char *) trb - (char *) dep->trb_pool;
 485
 486         return dep->trb_pool_dma + offset;
 487 }
 488
 489 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 490 {
 491         struct dwc3             *dwc = dep->dwc;
 492
 493         if (dep->trb_pool)
 494                 return 0;
 495
 496         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
 497                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 498                         &dep->trb_pool_dma, GFP_KERNEL);
 499         if (!dep->trb_pool) {
 500                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 501                                 dep->name);
 502                 return -ENOMEM;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 509 {
 510         struct dwc3             *dwc = dep->dwc;
 511
 512         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 513                         dep->trb_pool, dep->trb_pool_dma);
 514
 515         dep->trb_pool = NULL;
 516         dep->trb_pool_dma = 0;
 517 }
 518
 519 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
 520 {
 521         struct dwc3_gadget_ep_cmd_params params;
 522         int ret;
 523
 524         if (dep->flags & DWC3_EP_RESOURCE_ALLOCATED)
 525                 return 0;
 526
 527         memset(&params, 0x00, sizeof(params));
 528
 529         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 530
 531         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 532                         &params);
 533         if (ret)
 534                 return ret;
 535
 536         dep->flags |= DWC3_EP_RESOURCE_ALLOCATED;
 537         return 0;
 538 }
 539
 540 /**
 541  * dwc3_gadget_start_config - reset endpoint resources
 542  * @dwc: pointer to the DWC3 context
 543  * @resource_index: DEPSTARTCFG.XferRscIdx value (must be 0 or 2)
 544  *
 545  * Set resource_index=0 to reset all endpoints' resources allocation. Do this as
 546  * part of the power-on/soft-reset initialization.
 547  *
 548  * Set resource_index=2 to reset only non-control endpoints' resources. Do this
 549  * on receiving the SET_CONFIGURATION request or hibernation resume.
 550  */
 551 int dwc3_gadget_start_config(struct dwc3 *dwc, unsigned int resource_index)
 552 {
 553         struct dwc3_gadget_ep_cmd_params params;
 554         u32                     cmd;
 555         int                     i;
 556         int                     ret;
 557
 558         if (resource_index != 0 && resource_index != 2)
 559                 return -EINVAL;
 560
 561         memset(&params, 0x00, sizeof(params));
 562         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 563         cmd |= DWC3_DEPCMD_PARAM(resource_index);
 564
 565         ret = dwc3_send_gadget_ep_cmd(dwc->eps[0], cmd, &params);
 566         if (ret)
 567                 return ret;
 568
 569         /* Reset resource allocation flags */
 570         for (i = resource_index; i < dwc->num_eps && dwc->eps[i]; i++)
 571                 dwc->eps[i]->flags &= ~DWC3_EP_RESOURCE_ALLOCATED;
 572
 573         return 0;
 574 }
 575
 576 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 577 {
 578         const struct usb_ss_ep_comp_descriptor *comp_desc;
 579         const struct usb_endpoint_descriptor *desc;
 580         struct dwc3_gadget_ep_cmd_params params;
 581         struct dwc3 *dwc = dep->dwc;
 582
 583         comp_desc = dep->endpoint.comp_desc;
 584         desc = dep->endpoint.desc;
 585
 586         memset(&params, 0x00, sizeof(params));
 587
 588         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 589                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 590
 591         /* Burst size is only needed in SuperSpeed mode */
 592         if (dwc->gadget->speed >= USB_SPEED_SUPER) {
 593                 u32 burst = dep->endpoint.maxburst;
 594
 595                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 596         }
 597
 598         params.param0 |= action;
 599         if (action == DWC3_DEPCFG_ACTION_RESTORE)
 600                 params.param2 |= dep->saved_state;
 601
 602         if (usb_endpoint_xfer_control(desc))
 603                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 604
 605         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 606                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 607
 608         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 609                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 610                         | DWC3_DEPCFG_XFER_COMPLETE_EN
 611                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 612                 dep->stream_capable = true;
 613         }
 614
 615         if (!usb_endpoint_xfer_control(desc))
 616                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 617
 618         /*
 619          * We are doing 1:1 mapping for endpoints, meaning
 620          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 621          * so on. We consider the direction bit as part of the physical
 622          * endpoint number. So USB endpoint 0x81 is 0x03.
 623          */
 624         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 625
 626         /*
 627          * We must use the lower 16 TX FIFOs even though
 628          * HW might have more
 629          */
 630         if (dep->direction)
 631                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 632
 633         if (desc->bInterval) {
 634                 u8 bInterval_m1;
 635
 636                 /*
 637                  * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
 638                  *
 639                  * NOTE: The programming guide incorrectly stated bInterval_m1
 640                  * must be set to 0 when operating in fullspeed. Internally the
 641                  * controller does not have this limitation. See DWC_usb3x
 642                  * programming guide section 3.2.2.1.
 643                  */
 644                 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
 645
 646                 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
 647                     dwc->gadget->speed == USB_SPEED_FULL)
 648                         dep->interval = desc->bInterval;
 649                 else
 650                         dep->interval = 1 << (desc->bInterval - 1);
 651
 652                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
 653         }
 654
 655         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 656 }
 657
 658 /**
 659  * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
 660  * @dwc: pointer to the DWC3 context
 661  * @mult: multiplier to be used when calculating the fifo_size
 662  *
 663  * Calculates the size value based on the equation below:
 664  *
 665  * DWC3 revision 280A and prior:
 666  * fifo_size = mult * (max_packet / mdwidth) + 1;
 667  *
 668  * DWC3 revision 290A and onwards:
 669  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
 670  *
 671  * The max packet size is set to 1024, as the txfifo requirements mainly apply
 672  * to super speed USB use cases.  However, it is safe to overestimate the fifo
 673  * allocations for other scenarios, i.e. high speed USB.
 674  */
 675 static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
 676 {
 677         int max_packet = 1024;
 678         int fifo_size;
 679         int mdwidth;
 680
 681         mdwidth = dwc3_mdwidth(dwc);
 682
 683         /* MDWIDTH is represented in bits, we need it in bytes */
 684         mdwidth >>= 3;
 685
 686         if (DWC3_VER_IS_PRIOR(DWC3, 290A))
 687                 fifo_size = mult * (max_packet / mdwidth) + 1;
 688         else
 689                 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
 690         return fifo_size;
 691 }
 692
 693 /**
 694  * dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
 695  * @dwc: pointer to the DWC3 context
 696  *
 697  * Iterates through all the endpoint registers and clears the previous txfifo
 698  * allocations.
 699  */
 700 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
 701 {
 702         struct dwc3_ep *dep;
 703         int fifo_depth;
 704         int size;
 705         int num;
 706
 707         if (!dwc->do_fifo_resize)
 708                 return;
 709
 710         /* Read ep0IN related TXFIFO size */
 711         dep = dwc->eps[1];
 712         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
 713         if (DWC3_IP_IS(DWC3))
 714                 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
 715         else
 716                 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
 717
 718         dwc->last_fifo_depth = fifo_depth;
 719         /* Clear existing TXFIFO for all IN eps except ep0 */
 720         for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
 721              num += 2) {
 722                 dep = dwc->eps[num];
 723                 /* Don't change TXFRAMNUM on usb31 version */
 724                 size = DWC3_IP_IS(DWC3) ? 0 :
 725                         dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
 726                                    DWC31_GTXFIFOSIZ_TXFRAMNUM;
 727
 728                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
 729                 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
 730         }
 731         dwc->num_ep_resized = 0;
 732 }
 733
 734 /*
 735  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 736  * @dwc: pointer to our context structure
 737  *
 738  * This function will a best effort FIFO allocation in order
 739  * to improve FIFO usage and throughput, while still allowing
 740  * us to enable as many endpoints as possible.
 741  *
 742  * Keep in mind that this operation will be highly dependent
 743  * on the configured size for RAM1 - which contains TxFifo -,
 744  * the amount of endpoints enabled on coreConsultant tool, and
 745  * the width of the Master Bus.
 746  *
 747  * In general, FIFO depths are represented with the following equation:
 748  *
 749  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
 750  *
 751  * In conjunction with dwc3_gadget_check_config(), this resizing logic will
 752  * ensure that all endpoints will have enough internal memory for one max
 753  * packet per endpoint.
 754  */
 755 static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
 756 {
 757         struct dwc3 *dwc = dep->dwc;
 758         int fifo_0_start;
 759         int ram1_depth;
 760         int fifo_size;
 761         int min_depth;
 762         int num_in_ep;
 763         int remaining;
 764         int num_fifos = 1;
 765         int fifo;
 766         int tmp;
 767
 768         if (!dwc->do_fifo_resize)
 769                 return 0;
 770
 771         /* resize IN endpoints except ep0 */
 772         if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
 773                 return 0;
 774
 775         /* bail if already resized */
 776         if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
 777                 return 0;
 778
 779         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 780
 781         if ((dep->endpoint.maxburst > 1 &&
 782              usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
 783             usb_endpoint_xfer_isoc(dep->endpoint.desc))
 784                 num_fifos = 3;
 785
 786         if (dep->endpoint.maxburst > 6 &&
 787             (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
 788              usb_endpoint_xfer_isoc(dep->endpoint.desc)) && DWC3_IP_IS(DWC31))
 789                 num_fifos = dwc->tx_fifo_resize_max_num;
 790
 791         /* FIFO size for a single buffer */
 792         fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
 793
 794         /* Calculate the number of remaining EPs w/o any FIFO */
 795         num_in_ep = dwc->max_cfg_eps;
 796         num_in_ep -= dwc->num_ep_resized;
 797
 798         /* Reserve at least one FIFO for the number of IN EPs */
 799         min_depth = num_in_ep * (fifo + 1);
 800         remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
 801         remaining = max_t(int, 0, remaining);
 802         /*
 803          * We've already reserved 1 FIFO per EP, so check what we can fit in
 804          * addition to it.  If there is not enough remaining space, allocate
 805          * all the remaining space to the EP.
 806          */
 807         fifo_size = (num_fifos - 1) * fifo;
 808         if (remaining < fifo_size)
 809                 fifo_size = remaining;
 810
 811         fifo_size += fifo;
 812         /* Last increment according to the TX FIFO size equation */
 813         fifo_size++;
 814
 815         /* Check if TXFIFOs start at non-zero addr */
 816         tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
 817         fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
 818
 819         fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
 820         if (DWC3_IP_IS(DWC3))
 821                 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
 822         else
 823                 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
 824
 825         /* Check fifo size allocation doesn't exceed available RAM size. */
 826         if (dwc->last_fifo_depth >= ram1_depth) {
 827                 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
 828                         dwc->last_fifo_depth, ram1_depth,
 829                         dep->endpoint.name, fifo_size);
 830                 if (DWC3_IP_IS(DWC3))
 831                         fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
 832                 else
 833                         fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
 834
 835                 dwc->last_fifo_depth -= fifo_size;
 836                 return -ENOMEM;
 837         }
 838
 839         dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
 840         dep->flags |= DWC3_EP_TXFIFO_RESIZED;
 841         dwc->num_ep_resized++;
 842
 843         return 0;
 844 }
 845
 846 /**
 847  * __dwc3_gadget_ep_enable - initializes a hw endpoint
 848  * @dep: endpoint to be initialized
 849  * @action: one of INIT, MODIFY or RESTORE
 850  *
 851  * Caller should take care of locking. Execute all necessary commands to
 852  * initialize a HW endpoint so it can be used by a gadget driver.
 853  */
 854 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 855 {
 856         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 857         struct dwc3             *dwc = dep->dwc;
 858
 859         u32                     reg;
 860         int                     ret;
 861
 862         if (!(dep->flags & DWC3_EP_ENABLED)) {
 863                 ret = dwc3_gadget_resize_tx_fifos(dep);
 864                 if (ret)
 865                         return ret;
 866         }
 867
 868         ret = dwc3_gadget_set_ep_config(dep, action);
 869         if (ret)
 870                 return ret;
 871
 872         if (!(dep->flags & DWC3_EP_RESOURCE_ALLOCATED)) {
 873                 ret = dwc3_gadget_set_xfer_resource(dep);
 874                 if (ret)
 875                         return ret;
 876         }
 877
 878         if (!(dep->flags & DWC3_EP_ENABLED)) {
 879                 struct dwc3_trb *trb_st_hw;
 880                 struct dwc3_trb *trb_link;
 881
 882                 dep->type = usb_endpoint_type(desc);
 883                 dep->flags |= DWC3_EP_ENABLED;
 884
 885                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 886                 reg |= DWC3_DALEPENA_EP(dep->number);
 887                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 888
 889                 dep->trb_dequeue = 0;
 890                 dep->trb_enqueue = 0;
 891
 892                 if (usb_endpoint_xfer_control(desc))
 893                         goto out;
 894
 895                 /* Initialize the TRB ring */
 896                 memset(dep->trb_pool, 0,
 897                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 898
 899                 /* Link TRB. The HWO bit is never reset */
 900                 trb_st_hw = &dep->trb_pool[0];
 901
 902                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 903                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 904                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 905                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 906                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 907         }
 908
 909         /*
 910          * Issue StartTransfer here with no-op TRB so we can always rely on No
 911          * Response Update Transfer command.
 912          */
 913         if (usb_endpoint_xfer_bulk(desc) ||
 914                         usb_endpoint_xfer_int(desc)) {
 915                 struct dwc3_gadget_ep_cmd_params params;
 916                 struct dwc3_trb *trb;
 917                 dma_addr_t trb_dma;
 918                 u32 cmd;
 919
 920                 memset(&params, 0, sizeof(params));
 921                 trb = &dep->trb_pool[0];
 922                 trb_dma = dwc3_trb_dma_offset(dep, trb);
 923
 924                 params.param0 = upper_32_bits(trb_dma);
 925                 params.param1 = lower_32_bits(trb_dma);
 926
 927                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 928
 929                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 930                 if (ret < 0)
 931                         return ret;
 932
 933                 if (dep->stream_capable) {
 934                         /*
 935                          * For streams, at start, there maybe a race where the
 936                          * host primes the endpoint before the function driver
 937                          * queues a request to initiate a stream. In that case,
 938                          * the controller will not see the prime to generate the
 939                          * ERDY and start stream. To workaround this, issue a
 940                          * no-op TRB as normal, but end it immediately. As a
 941                          * result, when the function driver queues the request,
 942                          * the next START_TRANSFER command will cause the
 943                          * controller to generate an ERDY to initiate the
 944                          * stream.
 945                          */
 946                         dwc3_stop_active_transfer(dep, true, true);
 947
 948                         /*
 949                          * All stream eps will reinitiate stream on NoStream
 950                          * rejection until we can determine that the host can
 951                          * prime after the first transfer.
 952                          *
 953                          * However, if the controller is capable of
 954                          * TXF_FLUSH_BYPASS, then IN direction endpoints will
 955                          * automatically restart the stream without the driver
 956                          * initiation.
 957                          */
 958                         if (!dep->direction ||
 959                             !(dwc->hwparams.hwparams9 &
 960                               DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
 961                                 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
 962                 }
 963         }
 964
 965 out:
 966         trace_dwc3_gadget_ep_enable(dep);
 967
 968         return 0;
 969 }
 970
 971 void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
 972 {
 973         struct dwc3_request             *req;
 974
 975         dwc3_stop_active_transfer(dep, true, false);
 976
 977         /* If endxfer is delayed, avoid unmapping requests */
 978         if (dep->flags & DWC3_EP_DELAY_STOP)
 979                 return;
 980
 981         /* - giveback all requests to gadget driver */
 982         while (!list_empty(&dep->started_list)) {
 983                 req = next_request(&dep->started_list);
 984
 985                 dwc3_gadget_giveback(dep, req, status);
 986         }
 987
 988         while (!list_empty(&dep->pending_list)) {
 989                 req = next_request(&dep->pending_list);
 990
 991                 dwc3_gadget_giveback(dep, req, status);
 992         }
 993
 994         while (!list_empty(&dep->cancelled_list)) {
 995                 req = next_request(&dep->cancelled_list);
 996
 997                 dwc3_gadget_giveback(dep, req, status);
 998         }
 999 }
1000
1001 /**
1002  * __dwc3_gadget_ep_disable - disables a hw endpoint
1003  * @dep: the endpoint to disable
1004  *
1005  * This function undoes what __dwc3_gadget_ep_enable did and also removes
1006  * requests which are currently being processed by the hardware and those which
1007  * are not yet scheduled.
1008  *
1009  * Caller should take care of locking.
1010  */
1011 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1012 {
1013         struct dwc3             *dwc = dep->dwc;
1014         u32                     reg;
1015         u32                     mask;
1016
1017         trace_dwc3_gadget_ep_disable(dep);
1018
1019         /* make sure HW endpoint isn't stalled */
1020         if (dep->flags & DWC3_EP_STALL)
1021                 __dwc3_gadget_ep_set_halt(dep, 0, false);
1022
1023         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1024         reg &= ~DWC3_DALEPENA_EP(dep->number);
1025         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1026
1027         dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
1028
1029         dep->stream_capable = false;
1030         dep->type = 0;
1031         mask = DWC3_EP_TXFIFO_RESIZED | DWC3_EP_RESOURCE_ALLOCATED;
1032         /*
1033          * dwc3_remove_requests() can exit early if DWC3 EP delayed stop is
1034          * set.  Do not clear DEP flags, so that the end transfer command will
1035          * be reattempted during the next SETUP stage.
1036          */
1037         if (dep->flags & DWC3_EP_DELAY_STOP)
1038                 mask |= (DWC3_EP_DELAY_STOP | DWC3_EP_TRANSFER_STARTED);
1039         dep->flags &= mask;
1040
1041         /* Clear out the ep descriptors for non-ep0 */
1042         if (dep->number > 1) {
1043                 dep->endpoint.comp_desc = NULL;
1044                 dep->endpoint.desc = NULL;
1045         }
1046
1047         return 0;
1048 }
1049
1050 /* -------------------------------------------------------------------------- */
1051
1052 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1053                 const struct usb_endpoint_descriptor *desc)
1054 {
1055         return -EINVAL;
1056 }
1057
1058 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1059 {
1060         return -EINVAL;
1061 }
1062
1063 /* -------------------------------------------------------------------------- */
1064
1065 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1066                 const struct usb_endpoint_descriptor *desc)
1067 {
1068         struct dwc3_ep                  *dep;
1069         struct dwc3                     *dwc;
1070         unsigned long                   flags;
1071         int                             ret;
1072
1073         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1074                 pr_debug("dwc3: invalid parameters\n");
1075                 return -EINVAL;
1076         }
1077
1078         if (!desc->wMaxPacketSize) {
1079                 pr_debug("dwc3: missing wMaxPacketSize\n");
1080                 return -EINVAL;
1081         }
1082
1083         dep = to_dwc3_ep(ep);
1084         dwc = dep->dwc;
1085
1086         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1087                                         "%s is already enabled\n",
1088                                         dep->name))
1089                 return 0;
1090
1091         spin_lock_irqsave(&dwc->lock, flags);
1092         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1093         spin_unlock_irqrestore(&dwc->lock, flags);
1094
1095         return ret;
1096 }
1097
1098 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1099 {
1100         struct dwc3_ep                  *dep;
1101         struct dwc3                     *dwc;
1102         unsigned long                   flags;
1103         int                             ret;
1104
1105         if (!ep) {
1106                 pr_debug("dwc3: invalid parameters\n");
1107                 return -EINVAL;
1108         }
1109
1110         dep = to_dwc3_ep(ep);
1111         dwc = dep->dwc;
1112
1113         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1114                                         "%s is already disabled\n",
1115                                         dep->name))
1116                 return 0;
1117
1118         spin_lock_irqsave(&dwc->lock, flags);
1119         ret = __dwc3_gadget_ep_disable(dep);
1120         spin_unlock_irqrestore(&dwc->lock, flags);
1121
1122         return ret;
1123 }
1124
1125 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1126                 gfp_t gfp_flags)
1127 {
1128         struct dwc3_request             *req;
1129         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1130
1131         req = kzalloc(sizeof(*req), gfp_flags);
1132         if (!req)
1133                 return NULL;
1134
1135         req->direction  = dep->direction;
1136         req->epnum      = dep->number;
1137         req->dep        = dep;
1138         req->status     = DWC3_REQUEST_STATUS_UNKNOWN;
1139
1140         trace_dwc3_alloc_request(req);
1141
1142         return &req->request;
1143 }
1144
1145 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1146                 struct usb_request *request)
1147 {
1148         struct dwc3_request             *req = to_dwc3_request(request);
1149
1150         trace_dwc3_free_request(req);
1151         kfree(req);
1152 }
1153
1154 /**
1155  * dwc3_ep_prev_trb - returns the previous TRB in the ring
1156  * @dep: The endpoint with the TRB ring
1157  * @index: The index of the current TRB in the ring
1158  *
1159  * Returns the TRB prior to the one pointed to by the index. If the
1160  * index is 0, we will wrap backwards, skip the link TRB, and return
1161  * the one just before that.
1162  */
1163 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1164 {
1165         u8 tmp = index;
1166
1167         if (!tmp)
1168                 tmp = DWC3_TRB_NUM - 1;
1169
1170         return &dep->trb_pool[tmp - 1];
1171 }
1172
1173 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1174 {
1175         u8                      trbs_left;
1176
1177         /*
1178          * If the enqueue & dequeue are equal then the TRB ring is either full
1179          * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1180          * pending to be processed by the driver.
1181          */
1182         if (dep->trb_enqueue == dep->trb_dequeue) {
1183                 /*
1184                  * If there is any request remained in the started_list at
1185                  * this point, that means there is no TRB available.
1186                  */
1187                 if (!list_empty(&dep->started_list))
1188                         return 0;
1189
1190                 return DWC3_TRB_NUM - 1;
1191         }
1192
1193         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1194         trbs_left &= (DWC3_TRB_NUM - 1);
1195
1196         if (dep->trb_dequeue < dep->trb_enqueue)
1197                 trbs_left--;
1198
1199         return trbs_left;
1200 }
1201
1202 /**
1203  * dwc3_prepare_one_trb - setup one TRB from one request
1204  * @dep: endpoint for which this request is prepared
1205  * @req: dwc3_request pointer
1206  * @trb_length: buffer size of the TRB
1207  * @chain: should this TRB be chained to the next?
1208  * @node: only for isochronous endpoints. First TRB needs different type.
1209  * @use_bounce_buffer: set to use bounce buffer
1210  * @must_interrupt: set to interrupt on TRB completion
1211  */
1212 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1213                 struct dwc3_request *req, unsigned int trb_length,
1214                 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1215                 bool must_interrupt)
1216 {
1217         struct dwc3_trb         *trb;
1218         dma_addr_t              dma;
1219         unsigned int            stream_id = req->request.stream_id;
1220         unsigned int            short_not_ok = req->request.short_not_ok;
1221         unsigned int            no_interrupt = req->request.no_interrupt;
1222         unsigned int            is_last = req->request.is_last;
1223         struct dwc3             *dwc = dep->dwc;
1224         struct usb_gadget       *gadget = dwc->gadget;
1225         enum usb_device_speed   speed = gadget->speed;
1226
1227         if (use_bounce_buffer)
1228                 dma = dep->dwc->bounce_addr;
1229         else if (req->request.num_sgs > 0)
1230                 dma = sg_dma_address(req->start_sg);
1231         else
1232                 dma = req->request.dma;
1233
1234         trb = &dep->trb_pool[dep->trb_enqueue];
1235
1236         if (!req->trb) {
1237                 dwc3_gadget_move_started_request(req);
1238                 req->trb = trb;
1239                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1240         }
1241
1242         req->num_trbs++;
1243
1244         trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1245         trb->bpl = lower_32_bits(dma);
1246         trb->bph = upper_32_bits(dma);
1247
1248         switch (usb_endpoint_type(dep->endpoint.desc)) {
1249         case USB_ENDPOINT_XFER_CONTROL:
1250                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1251                 break;
1252
1253         case USB_ENDPOINT_XFER_ISOC:
1254                 if (!node) {
1255                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1256
1257                         /*
1258                          * USB Specification 2.0 Section 5.9.2 states that: "If
1259                          * there is only a single transaction in the microframe,
1260                          * only a DATA0 data packet PID is used.  If there are
1261                          * two transactions per microframe, DATA1 is used for
1262                          * the first transaction data packet and DATA0 is used
1263                          * for the second transaction data packet.  If there are
1264                          * three transactions per microframe, DATA2 is used for
1265                          * the first transaction data packet, DATA1 is used for
1266                          * the second, and DATA0 is used for the third."
1267                          *
1268                          * IOW, we should satisfy the following cases:
1269                          *
1270                          * 1) length <= maxpacket
1271                          *      - DATA0
1272                          *
1273                          * 2) maxpacket < length <= (2 * maxpacket)
1274                          *      - DATA1, DATA0
1275                          *
1276                          * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1277                          *      - DATA2, DATA1, DATA0
1278                          */
1279                         if (speed == USB_SPEED_HIGH) {
1280                                 struct usb_ep *ep = &dep->endpoint;
1281                                 unsigned int mult = 2;
1282                                 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1283
1284                                 if (req->request.length <= (2 * maxp))
1285                                         mult--;
1286
1287                                 if (req->request.length <= maxp)
1288                                         mult--;
1289
1290                                 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1291                         }
1292                 } else {
1293                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1294                 }
1295
1296                 if (!no_interrupt && !chain)
1297                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1298                 break;
1299
1300         case USB_ENDPOINT_XFER_BULK:
1301         case USB_ENDPOINT_XFER_INT:
1302                 trb->ctrl = DWC3_TRBCTL_NORMAL;
1303                 break;
1304         default:
1305                 /*
1306                  * This is only possible with faulty memory because we
1307                  * checked it already :)
1308                  */
1309                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1310                                 usb_endpoint_type(dep->endpoint.desc));
1311         }
1312
1313         /*
1314          * Enable Continue on Short Packet
1315          * when endpoint is not a stream capable
1316          */
1317         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1318                 if (!dep->stream_capable)
1319                         trb->ctrl |= DWC3_TRB_CTRL_CSP;
1320
1321                 if (short_not_ok)
1322                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1323         }
1324
1325         /* All TRBs setup for MST must set CSP=1 when LST=0 */
1326         if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1327                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1328
1329         if ((!no_interrupt && !chain) || must_interrupt)
1330                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1331
1332         if (chain)
1333                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1334         else if (dep->stream_capable && is_last &&
1335                  !DWC3_MST_CAPABLE(&dwc->hwparams))
1336                 trb->ctrl |= DWC3_TRB_CTRL_LST;
1337
1338         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1339                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1340
1341         /*
1342          * As per data book 4.2.3.2TRB Control Bit Rules section
1343          *
1344          * The controller autonomously checks the HWO field of a TRB to determine if the
1345          * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1346          * is valid before setting the HWO field to '1'. In most systems, this means that
1347          * software must update the fourth DWORD of a TRB last.
1348          *
1349          * However there is a possibility of CPU re-ordering here which can cause
1350          * controller to observe the HWO bit set prematurely.
1351          * Add a write memory barrier to prevent CPU re-ordering.
1352          */
1353         wmb();
1354         trb->ctrl |= DWC3_TRB_CTRL_HWO;
1355
1356         dwc3_ep_inc_enq(dep);
1357
1358         trace_dwc3_prepare_trb(dep, trb);
1359 }
1360
1361 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1362 {
1363         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1364         unsigned int rem = req->request.length % maxp;
1365
1366         if ((req->request.length && req->request.zero && !rem &&
1367                         !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1368                         (!req->direction && rem))
1369                 return true;
1370
1371         return false;
1372 }
1373
1374 /**
1375  * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1376  * @dep: The endpoint that the request belongs to
1377  * @req: The request to prepare
1378  * @entry_length: The last SG entry size
1379  * @node: Indicates whether this is not the first entry (for isoc only)
1380  *
1381  * Return the number of TRBs prepared.
1382  */
1383 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1384                 struct dwc3_request *req, unsigned int entry_length,
1385                 unsigned int node)
1386 {
1387         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1388         unsigned int rem = req->request.length % maxp;
1389         unsigned int num_trbs = 1;
1390
1391         if (dwc3_needs_extra_trb(dep, req))
1392                 num_trbs++;
1393
1394         if (dwc3_calc_trbs_left(dep) < num_trbs)
1395                 return 0;
1396
1397         req->needs_extra_trb = num_trbs > 1;
1398
1399         /* Prepare a normal TRB */
1400         if (req->direction || req->request.length)
1401                 dwc3_prepare_one_trb(dep, req, entry_length,
1402                                 req->needs_extra_trb, node, false, false);
1403
1404         /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1405         if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1406                 dwc3_prepare_one_trb(dep, req,
1407                                 req->direction ? 0 : maxp - rem,
1408                                 false, 1, true, false);
1409
1410         return num_trbs;
1411 }
1412
1413 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1414                 struct dwc3_request *req)
1415 {
1416         struct scatterlist *sg = req->start_sg;
1417         struct scatterlist *s;
1418         int             i;
1419         unsigned int length = req->request.length;
1420         unsigned int remaining = req->request.num_mapped_sgs
1421                 - req->num_queued_sgs;
1422         unsigned int num_trbs = req->num_trbs;
1423         bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1424
1425         /*
1426          * If we resume preparing the request, then get the remaining length of
1427          * the request and resume where we left off.
1428          */
1429         for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1430                 length -= sg_dma_len(s);
1431
1432         for_each_sg(sg, s, remaining, i) {
1433                 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1434                 unsigned int trb_length;
1435                 bool must_interrupt = false;
1436                 bool last_sg = false;
1437
1438                 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1439
1440                 length -= trb_length;
1441
1442                 /*
1443                  * IOMMU driver is coalescing the list of sgs which shares a
1444                  * page boundary into one and giving it to USB driver. With
1445                  * this the number of sgs mapped is not equal to the number of
1446                  * sgs passed. So mark the chain bit to false if it isthe last
1447                  * mapped sg.
1448                  */
1449                 if ((i == remaining - 1) || !length)
1450                         last_sg = true;
1451
1452                 if (!num_trbs_left)
1453                         break;
1454
1455                 if (last_sg) {
1456                         if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1457                                 break;
1458                 } else {
1459                         /*
1460                          * Look ahead to check if we have enough TRBs for the
1461                          * next SG entry. If not, set interrupt on this TRB to
1462                          * resume preparing the next SG entry when more TRBs are
1463                          * free.
1464                          */
1465                         if (num_trbs_left == 1 || (needs_extra_trb &&
1466                                         num_trbs_left <= 2 &&
1467                                         sg_dma_len(sg_next(s)) >= length)) {
1468                                 struct dwc3_request *r;
1469
1470                                 /* Check if previous requests already set IOC */
1471                                 list_for_each_entry(r, &dep->started_list, list) {
1472                                         if (r != req && !r->request.no_interrupt)
1473                                                 break;
1474
1475                                         if (r == req)
1476                                                 must_interrupt = true;
1477                                 }
1478                         }
1479
1480                         dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1481                                         must_interrupt);
1482                 }
1483
1484                 /*
1485                  * There can be a situation where all sgs in sglist are not
1486                  * queued because of insufficient trb number. To handle this
1487                  * case, update start_sg to next sg to be queued, so that
1488                  * we have free trbs we can continue queuing from where we
1489                  * previously stopped
1490                  */
1491                 if (!last_sg)
1492                         req->start_sg = sg_next(s);
1493
1494                 req->num_queued_sgs++;
1495                 req->num_pending_sgs--;
1496
1497                 /*
1498                  * The number of pending SG entries may not correspond to the
1499                  * number of mapped SG entries. If all the data are queued, then
1500                  * don't include unused SG entries.
1501                  */
1502                 if (length == 0) {
1503                         req->num_pending_sgs = 0;
1504                         break;
1505                 }
1506
1507                 if (must_interrupt)
1508                         break;
1509         }
1510
1511         return req->num_trbs - num_trbs;
1512 }
1513
1514 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1515                 struct dwc3_request *req)
1516 {
1517         return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1518 }
1519
1520 /*
1521  * dwc3_prepare_trbs - setup TRBs from requests
1522  * @dep: endpoint for which requests are being prepared
1523  *
1524  * The function goes through the requests list and sets up TRBs for the
1525  * transfers. The function returns once there are no more TRBs available or
1526  * it runs out of requests.
1527  *
1528  * Returns the number of TRBs prepared or negative errno.
1529  */
1530 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1531 {
1532         struct dwc3_request     *req, *n;
1533         int                     ret = 0;
1534
1535         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1536
1537         /*
1538          * We can get in a situation where there's a request in the started list
1539          * but there weren't enough TRBs to fully kick it in the first time
1540          * around, so it has been waiting for more TRBs to be freed up.
1541          *
1542          * In that case, we should check if we have a request with pending_sgs
1543          * in the started list and prepare TRBs for that request first,
1544          * otherwise we will prepare TRBs completely out of order and that will
1545          * break things.
1546          */
1547         list_for_each_entry(req, &dep->started_list, list) {
1548                 if (req->num_pending_sgs > 0) {
1549                         ret = dwc3_prepare_trbs_sg(dep, req);
1550                         if (!ret || req->num_pending_sgs)
1551                                 return ret;
1552                 }
1553
1554                 if (!dwc3_calc_trbs_left(dep))
1555                         return ret;
1556
1557                 /*
1558                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1559                  * burst capability may try to read and use TRBs beyond the
1560                  * active transfer instead of stopping.
1561                  */
1562                 if (dep->stream_capable && req->request.is_last &&
1563                     !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1564                         return ret;
1565         }
1566
1567         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1568                 struct dwc3     *dwc = dep->dwc;
1569
1570                 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1571                                                     dep->direction);
1572                 if (ret)
1573                         return ret;
1574
1575                 req->sg                 = req->request.sg;
1576                 req->start_sg           = req->sg;
1577                 req->num_queued_sgs     = 0;
1578                 req->num_pending_sgs    = req->request.num_mapped_sgs;
1579
1580                 if (req->num_pending_sgs > 0) {
1581                         ret = dwc3_prepare_trbs_sg(dep, req);
1582                         if (req->num_pending_sgs)
1583                                 return ret;
1584                 } else {
1585                         ret = dwc3_prepare_trbs_linear(dep, req);
1586                 }
1587
1588                 if (!ret || !dwc3_calc_trbs_left(dep))
1589                         return ret;
1590
1591                 /*
1592                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1593                  * burst capability may try to read and use TRBs beyond the
1594                  * active transfer instead of stopping.
1595                  */
1596                 if (dep->stream_capable && req->request.is_last &&
1597                     !DWC3_MST_CAPABLE(&dwc->hwparams))
1598                         return ret;
1599         }
1600
1601         return ret;
1602 }
1603
1604 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1605
1606 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1607 {
1608         struct dwc3_gadget_ep_cmd_params params;
1609         struct dwc3_request             *req;
1610         int                             starting;
1611         int                             ret;
1612         u32                             cmd;
1613
1614         /*
1615          * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1616          * This happens when we need to stop and restart a transfer such as in
1617          * the case of reinitiating a stream or retrying an isoc transfer.
1618          */
1619         ret = dwc3_prepare_trbs(dep);
1620         if (ret < 0)
1621                 return ret;
1622
1623         starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1624
1625         /*
1626          * If there's no new TRB prepared and we don't need to restart a
1627          * transfer, there's no need to update the transfer.
1628          */
1629         if (!ret && !starting)
1630                 return ret;
1631
1632         req = next_request(&dep->started_list);
1633         if (!req) {
1634                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1635                 return 0;
1636         }
1637
1638         memset(&params, 0, sizeof(params));
1639
1640         if (starting) {
1641                 params.param0 = upper_32_bits(req->trb_dma);
1642                 params.param1 = lower_32_bits(req->trb_dma);
1643                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1644
1645                 if (dep->stream_capable)
1646                         cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1647
1648                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1649                         cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1650         } else {
1651                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1652                         DWC3_DEPCMD_PARAM(dep->resource_index);
1653         }
1654
1655         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1656         if (ret < 0) {
1657                 struct dwc3_request *tmp;
1658
1659                 if (ret == -EAGAIN)
1660                         return ret;
1661
1662                 dwc3_stop_active_transfer(dep, true, true);
1663
1664                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1665                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1666
1667                 /* If ep isn't started, then there's no end transfer pending */
1668                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1669                         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1670
1671                 return ret;
1672         }
1673
1674         if (dep->stream_capable && req->request.is_last &&
1675             !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1676                 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1677
1678         return 0;
1679 }
1680
1681 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1682 {
1683         u32                     reg;
1684
1685         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1686         return DWC3_DSTS_SOFFN(reg);
1687 }
1688
1689 /**
1690  * __dwc3_stop_active_transfer - stop the current active transfer
1691  * @dep: isoc endpoint
1692  * @force: set forcerm bit in the command
1693  * @interrupt: command complete interrupt after End Transfer command
1694  *
1695  * When setting force, the ForceRM bit will be set. In that case
1696  * the controller won't update the TRB progress on command
1697  * completion. It also won't clear the HWO bit in the TRB.
1698  * The command will also not complete immediately in that case.
1699  */
1700 static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1701 {
1702         struct dwc3_gadget_ep_cmd_params params;
1703         u32 cmd;
1704         int ret;
1705
1706         cmd = DWC3_DEPCMD_ENDTRANSFER;
1707         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1708         cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1709         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1710         memset(&params, 0, sizeof(params));
1711         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1712         /*
1713          * If the End Transfer command was timed out while the device is
1714          * not in SETUP phase, it's possible that an incoming Setup packet
1715          * may prevent the command's completion. Let's retry when the
1716          * ep0state returns to EP0_SETUP_PHASE.
1717          */
1718         if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) {
1719                 dep->flags |= DWC3_EP_DELAY_STOP;
1720                 return 0;
1721         }
1722         WARN_ON_ONCE(ret);
1723         dep->resource_index = 0;
1724
1725         if (!interrupt) {
1726                 mdelay(1);
1727                 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1728         } else if (!ret) {
1729                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1730         }
1731
1732         dep->flags &= ~DWC3_EP_DELAY_STOP;
1733         return ret;
1734 }
1735
1736 /**
1737  * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1738  * @dep: isoc endpoint
1739  *
1740  * This function tests for the correct combination of BIT[15:14] from the 16-bit
1741  * microframe number reported by the XferNotReady event for the future frame
1742  * number to start the isoc transfer.
1743  *
1744  * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1745  * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1746  * XferNotReady event are invalid. The driver uses this number to schedule the
1747  * isochronous transfer and passes it to the START TRANSFER command. Because
1748  * this number is invalid, the command may fail. If BIT[15:14] matches the
1749  * internal 16-bit microframe, the START TRANSFER command will pass and the
1750  * transfer will start at the scheduled time, if it is off by 1, the command
1751  * will still pass, but the transfer will start 2 seconds in the future. For all
1752  * other conditions, the START TRANSFER command will fail with bus-expiry.
1753  *
1754  * In order to workaround this issue, we can test for the correct combination of
1755  * BIT[15:14] by sending START TRANSFER commands with different values of
1756  * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1757  * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1758  * As the result, within the 4 possible combinations for BIT[15:14], there will
1759  * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1760  * command status will result in a 2-second delay start. The smaller BIT[15:14]
1761  * value is the correct combination.
1762  *
1763  * Since there are only 4 outcomes and the results are ordered, we can simply
1764  * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1765  * deduce the smaller successful combination.
1766  *
1767  * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1768  * of BIT[15:14]. The correct combination is as follow:
1769  *
1770  * if test0 fails and test1 passes, BIT[15:14] is 'b01
1771  * if test0 fails and test1 fails, BIT[15:14] is 'b10
1772  * if test0 passes and test1 fails, BIT[15:14] is 'b11
1773  * if test0 passes and test1 passes, BIT[15:14] is 'b00
1774  *
1775  * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1776  * endpoints.
1777  */
1778 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1779 {
1780         int cmd_status = 0;
1781         bool test0;
1782         bool test1;
1783
1784         while (dep->combo_num < 2) {
1785                 struct dwc3_gadget_ep_cmd_params params;
1786                 u32 test_frame_number;
1787                 u32 cmd;
1788
1789                 /*
1790                  * Check if we can start isoc transfer on the next interval or
1791                  * 4 uframes in the future with BIT[15:14] as dep->combo_num
1792                  */
1793                 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1794                 test_frame_number |= dep->combo_num << 14;
1795                 test_frame_number += max_t(u32, 4, dep->interval);
1796
1797                 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1798                 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1799
1800                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1801                 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1802                 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1803
1804                 /* Redo if some other failure beside bus-expiry is received */
1805                 if (cmd_status && cmd_status != -EAGAIN) {
1806                         dep->start_cmd_status = 0;
1807                         dep->combo_num = 0;
1808                         return 0;
1809                 }
1810
1811                 /* Store the first test status */
1812                 if (dep->combo_num == 0)
1813                         dep->start_cmd_status = cmd_status;
1814
1815                 dep->combo_num++;
1816
1817                 /*
1818                  * End the transfer if the START_TRANSFER command is successful
1819                  * to wait for the next XferNotReady to test the command again
1820                  */
1821                 if (cmd_status == 0) {
1822                         dwc3_stop_active_transfer(dep, true, true);
1823                         return 0;
1824                 }
1825         }
1826
1827         /* test0 and test1 are both completed at this point */
1828         test0 = (dep->start_cmd_status == 0);
1829         test1 = (cmd_status == 0);
1830
1831         if (!test0 && test1)
1832                 dep->combo_num = 1;
1833         else if (!test0 && !test1)
1834                 dep->combo_num = 2;
1835         else if (test0 && !test1)
1836                 dep->combo_num = 3;
1837         else if (test0 && test1)
1838                 dep->combo_num = 0;
1839
1840         dep->frame_number &= DWC3_FRNUMBER_MASK;
1841         dep->frame_number |= dep->combo_num << 14;
1842         dep->frame_number += max_t(u32, 4, dep->interval);
1843
1844         /* Reinitialize test variables */
1845         dep->start_cmd_status = 0;
1846         dep->combo_num = 0;
1847
1848         return __dwc3_gadget_kick_transfer(dep);
1849 }
1850
1851 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1852 {
1853         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1854         struct dwc3 *dwc = dep->dwc;
1855         int ret;
1856         int i;
1857
1858         if (list_empty(&dep->pending_list) &&
1859             list_empty(&dep->started_list)) {
1860                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1861                 return -EAGAIN;
1862         }
1863
1864         if (!dwc->dis_start_transfer_quirk &&
1865             (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1866              DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1867                 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1868                         return dwc3_gadget_start_isoc_quirk(dep);
1869         }
1870
1871         if (desc->bInterval <= 14 &&
1872             dwc->gadget->speed >= USB_SPEED_HIGH) {
1873                 u32 frame = __dwc3_gadget_get_frame(dwc);
1874                 bool rollover = frame <
1875                                 (dep->frame_number & DWC3_FRNUMBER_MASK);
1876
1877                 /*
1878                  * frame_number is set from XferNotReady and may be already
1879                  * out of date. DSTS only provides the lower 14 bit of the
1880                  * current frame number. So add the upper two bits of
1881                  * frame_number and handle a possible rollover.
1882                  * This will provide the correct frame_number unless more than
1883                  * rollover has happened since XferNotReady.
1884                  */
1885
1886                 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1887                                      frame;
1888                 if (rollover)
1889                         dep->frame_number += BIT(14);
1890         }
1891
1892         for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1893                 int future_interval = i + 1;
1894
1895                 /* Give the controller at least 500us to schedule transfers */
1896                 if (desc->bInterval < 3)
1897                         future_interval += 3 - desc->bInterval;
1898
1899                 dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
1900
1901                 ret = __dwc3_gadget_kick_transfer(dep);
1902                 if (ret != -EAGAIN)
1903                         break;
1904         }
1905
1906         /*
1907          * After a number of unsuccessful start attempts due to bus-expiry
1908          * status, issue END_TRANSFER command and retry on the next XferNotReady
1909          * event.
1910          */
1911         if (ret == -EAGAIN)
1912                 ret = __dwc3_stop_active_transfer(dep, false, true);
1913
1914         return ret;
1915 }
1916
1917 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1918 {
1919         struct dwc3             *dwc = dep->dwc;
1920
1921         if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1922                 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1923                                 dep->name);
1924                 return -ESHUTDOWN;
1925         }
1926
1927         if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1928                                 &req->request, req->dep->name))
1929                 return -EINVAL;
1930
1931         if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1932                                 "%s: request %pK already in flight\n",
1933                                 dep->name, &req->request))
1934                 return -EINVAL;
1935
1936         pm_runtime_get(dwc->dev);
1937
1938         req->request.actual     = 0;
1939         req->request.status     = -EINPROGRESS;
1940
1941         trace_dwc3_ep_queue(req);
1942
1943         list_add_tail(&req->list, &dep->pending_list);
1944         req->status = DWC3_REQUEST_STATUS_QUEUED;
1945
1946         if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1947                 return 0;
1948
1949         /*
1950          * Start the transfer only after the END_TRANSFER is completed
1951          * and endpoint STALL is cleared.
1952          */
1953         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1954             (dep->flags & DWC3_EP_WEDGE) ||
1955             (dep->flags & DWC3_EP_DELAY_STOP) ||
1956             (dep->flags & DWC3_EP_STALL)) {
1957                 dep->flags |= DWC3_EP_DELAY_START;
1958                 return 0;
1959         }
1960
1961         /*
1962          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1963          * wait for a XferNotReady event so we will know what's the current
1964          * (micro-)frame number.
1965          *
1966          * Without this trick, we are very, very likely gonna get Bus Expiry
1967          * errors which will force us issue EndTransfer command.
1968          */
1969         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1970                 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1971                         if ((dep->flags & DWC3_EP_PENDING_REQUEST))
1972                                 return __dwc3_gadget_start_isoc(dep);
1973
1974                         return 0;
1975                 }
1976         }
1977
1978         __dwc3_gadget_kick_transfer(dep);
1979
1980         return 0;
1981 }
1982
1983 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1984         gfp_t gfp_flags)
1985 {
1986         struct dwc3_request             *req = to_dwc3_request(request);
1987         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1988         struct dwc3                     *dwc = dep->dwc;
1989
1990         unsigned long                   flags;
1991
1992         int                             ret;
1993
1994         spin_lock_irqsave(&dwc->lock, flags);
1995         ret = __dwc3_gadget_ep_queue(dep, req);
1996         spin_unlock_irqrestore(&dwc->lock, flags);
1997
1998         return ret;
1999 }
2000
2001 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
2002 {
2003         int i;
2004
2005         /* If req->trb is not set, then the request has not started */
2006         if (!req->trb)
2007                 return;
2008
2009         /*
2010          * If request was already started, this means we had to
2011          * stop the transfer. With that we also need to ignore
2012          * all TRBs used by the request, however TRBs can only
2013          * be modified after completion of END_TRANSFER
2014          * command. So what we do here is that we wait for
2015          * END_TRANSFER completion and only after that, we jump
2016          * over TRBs by clearing HWO and incrementing dequeue
2017          * pointer.
2018          */
2019         for (i = 0; i < req->num_trbs; i++) {
2020                 struct dwc3_trb *trb;
2021
2022                 trb = &dep->trb_pool[dep->trb_dequeue];
2023                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2024                 dwc3_ep_inc_deq(dep);
2025         }
2026
2027         req->num_trbs = 0;
2028 }
2029
2030 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
2031 {
2032         struct dwc3_request             *req;
2033         struct dwc3                     *dwc = dep->dwc;
2034
2035         while (!list_empty(&dep->cancelled_list)) {
2036                 req = next_request(&dep->cancelled_list);
2037                 dwc3_gadget_ep_skip_trbs(dep, req);
2038                 switch (req->status) {
2039                 case DWC3_REQUEST_STATUS_DISCONNECTED:
2040                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
2041                         break;
2042                 case DWC3_REQUEST_STATUS_DEQUEUED:
2043                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
2044                         break;
2045                 case DWC3_REQUEST_STATUS_STALLED:
2046                         dwc3_gadget_giveback(dep, req, -EPIPE);
2047                         break;
2048                 default:
2049                         dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
2050                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
2051                         break;
2052                 }
2053                 /*
2054                  * The endpoint is disabled, let the dwc3_remove_requests()
2055                  * handle the cleanup.
2056                  */
2057                 if (!dep->endpoint.desc)
2058                         break;
2059         }
2060 }
2061
2062 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2063                 struct usb_request *request)
2064 {
2065         struct dwc3_request             *req = to_dwc3_request(request);
2066         struct dwc3_request             *r = NULL;
2067
2068         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2069         struct dwc3                     *dwc = dep->dwc;
2070
2071         unsigned long                   flags;
2072         int                             ret = 0;
2073
2074         trace_dwc3_ep_dequeue(req);
2075
2076         spin_lock_irqsave(&dwc->lock, flags);
2077
2078         list_for_each_entry(r, &dep->cancelled_list, list) {
2079                 if (r == req)
2080                         goto out;
2081         }
2082
2083         list_for_each_entry(r, &dep->pending_list, list) {
2084                 if (r == req) {
2085                         /*
2086                          * Explicitly check for EP0/1 as dequeue for those
2087                          * EPs need to be handled differently.  Control EP
2088                          * only deals with one USB req, and giveback will
2089                          * occur during dwc3_ep0_stall_and_restart().  EP0
2090                          * requests are never added to started_list.
2091                          */
2092                         if (dep->number > 1)
2093                                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2094                         else
2095                                 dwc3_ep0_reset_state(dwc);
2096                         goto out;
2097                 }
2098         }
2099
2100         list_for_each_entry(r, &dep->started_list, list) {
2101                 if (r == req) {
2102                         struct dwc3_request *t;
2103
2104                         /* wait until it is processed */
2105                         dwc3_stop_active_transfer(dep, true, true);
2106
2107                         /*
2108                          * Remove any started request if the transfer is
2109                          * cancelled.
2110                          */
2111                         list_for_each_entry_safe(r, t, &dep->started_list, list)
2112                                 dwc3_gadget_move_cancelled_request(r,
2113                                                 DWC3_REQUEST_STATUS_DEQUEUED);
2114
2115                         dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2116
2117                         goto out;
2118                 }
2119         }
2120
2121         dev_err(dwc->dev, "request %pK was not queued to %s\n",
2122                 request, ep->name);
2123         ret = -EINVAL;
2124 out:
2125         spin_unlock_irqrestore(&dwc->lock, flags);
2126
2127         return ret;
2128 }
2129
2130 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2131 {
2132         struct dwc3_gadget_ep_cmd_params        params;
2133         struct dwc3                             *dwc = dep->dwc;
2134         struct dwc3_request                     *req;
2135         struct dwc3_request                     *tmp;
2136         int                                     ret;
2137
2138         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2139                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2140                 return -EINVAL;
2141         }
2142
2143         memset(&params, 0x00, sizeof(params));
2144
2145         if (value) {
2146                 struct dwc3_trb *trb;
2147
2148                 unsigned int transfer_in_flight;
2149                 unsigned int started;
2150
2151                 if (dep->number > 1)
2152                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2153                 else
2154                         trb = &dwc->ep0_trb[dep->trb_enqueue];
2155
2156                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2157                 started = !list_empty(&dep->started_list);
2158
2159                 if (!protocol && ((dep->direction && transfer_in_flight) ||
2160                                 (!dep->direction && started))) {
2161                         return -EAGAIN;
2162                 }
2163
2164                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2165                                 &params);
2166                 if (ret)
2167                         dev_err(dwc->dev, "failed to set STALL on %s\n",
2168                                         dep->name);
2169                 else
2170                         dep->flags |= DWC3_EP_STALL;
2171         } else {
2172                 /*
2173                  * Don't issue CLEAR_STALL command to control endpoints. The
2174                  * controller automatically clears the STALL when it receives
2175                  * the SETUP token.
2176                  */
2177                 if (dep->number <= 1) {
2178                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2179                         return 0;
2180                 }
2181
2182                 dwc3_stop_active_transfer(dep, true, true);
2183
2184                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2185                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2186
2187                 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
2188                     (dep->flags & DWC3_EP_DELAY_STOP)) {
2189                         dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2190                         if (protocol)
2191                                 dwc->clear_stall_protocol = dep->number;
2192
2193                         return 0;
2194                 }
2195
2196                 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2197
2198                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2199                 if (ret) {
2200                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
2201                                         dep->name);
2202                         return ret;
2203                 }
2204
2205                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2206
2207                 if ((dep->flags & DWC3_EP_DELAY_START) &&
2208                     !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2209                         __dwc3_gadget_kick_transfer(dep);
2210
2211                 dep->flags &= ~DWC3_EP_DELAY_START;
2212         }
2213
2214         return ret;
2215 }
2216
2217 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2218 {
2219         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2220         struct dwc3                     *dwc = dep->dwc;
2221
2222         unsigned long                   flags;
2223
2224         int                             ret;
2225
2226         spin_lock_irqsave(&dwc->lock, flags);
2227         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2228         spin_unlock_irqrestore(&dwc->lock, flags);
2229
2230         return ret;
2231 }
2232
2233 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2234 {
2235         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2236         struct dwc3                     *dwc = dep->dwc;
2237         unsigned long                   flags;
2238         int                             ret;
2239
2240         spin_lock_irqsave(&dwc->lock, flags);
2241         dep->flags |= DWC3_EP_WEDGE;
2242
2243         if (dep->number == 0 || dep->number == 1)
2244                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2245         else
2246                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2247         spin_unlock_irqrestore(&dwc->lock, flags);
2248
2249         return ret;
2250 }
2251
2252 /* -------------------------------------------------------------------------- */
2253
2254 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2255         .bLength        = USB_DT_ENDPOINT_SIZE,
2256         .bDescriptorType = USB_DT_ENDPOINT,
2257         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
2258 };
2259
2260 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2261         .enable         = dwc3_gadget_ep0_enable,
2262         .disable        = dwc3_gadget_ep0_disable,
2263         .alloc_request  = dwc3_gadget_ep_alloc_request,
2264         .free_request   = dwc3_gadget_ep_free_request,
2265         .queue          = dwc3_gadget_ep0_queue,
2266         .dequeue        = dwc3_gadget_ep_dequeue,
2267         .set_halt       = dwc3_gadget_ep0_set_halt,
2268         .set_wedge      = dwc3_gadget_ep_set_wedge,
2269 };
2270
2271 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2272         .enable         = dwc3_gadget_ep_enable,
2273         .disable        = dwc3_gadget_ep_disable,
2274         .alloc_request  = dwc3_gadget_ep_alloc_request,
2275         .free_request   = dwc3_gadget_ep_free_request,
2276         .queue          = dwc3_gadget_ep_queue,
2277         .dequeue        = dwc3_gadget_ep_dequeue,
2278         .set_halt       = dwc3_gadget_ep_set_halt,
2279         .set_wedge      = dwc3_gadget_ep_set_wedge,
2280 };
2281
2282 /* -------------------------------------------------------------------------- */
2283
2284 static void dwc3_gadget_enable_linksts_evts(struct dwc3 *dwc, bool set)
2285 {
2286         u32 reg;
2287
2288         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2289                 return;
2290
2291         reg = dwc3_readl(dwc->regs, DWC3_DEVTEN);
2292         if (set)
2293                 reg |= DWC3_DEVTEN_ULSTCNGEN;
2294         else
2295                 reg &= ~DWC3_DEVTEN_ULSTCNGEN;
2296
2297         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2298 }
2299
2300 static int dwc3_gadget_get_frame(struct usb_gadget *g)
2301 {
2302         struct dwc3             *dwc = gadget_to_dwc(g);
2303
2304         return __dwc3_gadget_get_frame(dwc);
2305 }
2306
2307 static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async)
2308 {
2309         int                     retries;
2310
2311         int                     ret;
2312         u32                     reg;
2313
2314         u8                      link_state;
2315
2316         /*
2317          * According to the Databook Remote wakeup request should
2318          * be issued only when the device is in early suspend state.
2319          *
2320          * We can check that via USB Link State bits in DSTS register.
2321          */
2322         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2323
2324         link_state = DWC3_DSTS_USBLNKST(reg);
2325
2326         switch (link_state) {
2327         case DWC3_LINK_STATE_RESET:
2328         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
2329         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
2330         case DWC3_LINK_STATE_U2:        /* in HS, means Sleep (L1) */
2331         case DWC3_LINK_STATE_U1:
2332         case DWC3_LINK_STATE_RESUME:
2333                 break;
2334         default:
2335                 return -EINVAL;
2336         }
2337
2338         if (async)
2339                 dwc3_gadget_enable_linksts_evts(dwc, true);
2340
2341         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2342         if (ret < 0) {
2343                 dev_err(dwc->dev, "failed to put link in Recovery\n");
2344                 dwc3_gadget_enable_linksts_evts(dwc, false);
2345                 return ret;
2346         }
2347
2348         /* Recent versions do this automatically */
2349         if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2350                 /* write zeroes to Link Change Request */
2351                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2352                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2353                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2354         }
2355
2356         /*
2357          * Since link status change events are enabled we will receive
2358          * an U0 event when wakeup is successful. So bail out.
2359          */
2360         if (async)
2361                 return 0;
2362
2363         /* poll until Link State changes to ON */
2364         retries = 20000;
2365
2366         while (retries--) {
2367                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2368
2369                 /* in HS, means ON */
2370                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2371                         break;
2372         }
2373
2374         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2375                 dev_err(dwc->dev, "failed to send remote wakeup\n");
2376                 return -EINVAL;
2377         }
2378
2379         return 0;
2380 }
2381
2382 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2383 {
2384         struct dwc3             *dwc = gadget_to_dwc(g);
2385         unsigned long           flags;
2386         int                     ret;
2387
2388         if (!dwc->wakeup_configured) {
2389                 dev_err(dwc->dev, "remote wakeup not configured\n");
2390                 return -EINVAL;
2391         }
2392
2393         spin_lock_irqsave(&dwc->lock, flags);
2394         if (!dwc->gadget->wakeup_armed) {
2395                 dev_err(dwc->dev, "not armed for remote wakeup\n");
2396                 spin_unlock_irqrestore(&dwc->lock, flags);
2397                 return -EINVAL;
2398         }
2399         ret = __dwc3_gadget_wakeup(dwc, true);
2400
2401         spin_unlock_irqrestore(&dwc->lock, flags);
2402
2403         return ret;
2404 }
2405
2406 static void dwc3_resume_gadget(struct dwc3 *dwc);
2407
2408 static int dwc3_gadget_func_wakeup(struct usb_gadget *g, int intf_id)
2409 {
2410         struct  dwc3            *dwc = gadget_to_dwc(g);
2411         unsigned long           flags;
2412         int                     ret;
2413         int                     link_state;
2414
2415         if (!dwc->wakeup_configured) {
2416                 dev_err(dwc->dev, "remote wakeup not configured\n");
2417                 return -EINVAL;
2418         }
2419
2420         spin_lock_irqsave(&dwc->lock, flags);
2421         /*
2422          * If the link is in U3, signal for remote wakeup and wait for the
2423          * link to transition to U0 before sending device notification.
2424          */
2425         link_state = dwc3_gadget_get_link_state(dwc);
2426         if (link_state == DWC3_LINK_STATE_U3) {
2427                 ret = __dwc3_gadget_wakeup(dwc, false);
2428                 if (ret) {
2429                         spin_unlock_irqrestore(&dwc->lock, flags);
2430                         return -EINVAL;
2431                 }
2432                 dwc3_resume_gadget(dwc);
2433                 dwc->suspended = false;
2434                 dwc->link_state = DWC3_LINK_STATE_U0;
2435         }
2436
2437         ret = dwc3_send_gadget_generic_command(dwc, DWC3_DGCMD_DEV_NOTIFICATION,
2438                                                DWC3_DGCMDPAR_DN_FUNC_WAKE |
2439                                                DWC3_DGCMDPAR_INTF_SEL(intf_id));
2440         if (ret)
2441                 dev_err(dwc->dev, "function remote wakeup failed, ret:%d\n", ret);
2442
2443         spin_unlock_irqrestore(&dwc->lock, flags);
2444
2445         return ret;
2446 }
2447
2448 static int dwc3_gadget_set_remote_wakeup(struct usb_gadget *g, int set)
2449 {
2450         struct dwc3             *dwc = gadget_to_dwc(g);
2451         unsigned long           flags;
2452
2453         spin_lock_irqsave(&dwc->lock, flags);
2454         dwc->wakeup_configured = !!set;
2455         spin_unlock_irqrestore(&dwc->lock, flags);
2456
2457         return 0;
2458 }
2459
2460 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2461                 int is_selfpowered)
2462 {
2463         struct dwc3             *dwc = gadget_to_dwc(g);
2464         unsigned long           flags;
2465
2466         spin_lock_irqsave(&dwc->lock, flags);
2467         g->is_selfpowered = !!is_selfpowered;
2468         spin_unlock_irqrestore(&dwc->lock, flags);
2469
2470         return 0;
2471 }
2472
2473 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2474 {
2475         u32 epnum;
2476
2477         for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2478                 struct dwc3_ep *dep;
2479
2480                 dep = dwc->eps[epnum];
2481                 if (!dep)
2482                         continue;
2483
2484                 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
2485         }
2486 }
2487
2488 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2489 {
2490         enum usb_ssp_rate       ssp_rate = dwc->gadget_ssp_rate;
2491         u32                     reg;
2492
2493         if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2494                 ssp_rate = dwc->max_ssp_rate;
2495
2496         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2497         reg &= ~DWC3_DCFG_SPEED_MASK;
2498         reg &= ~DWC3_DCFG_NUMLANES(~0);
2499
2500         if (ssp_rate == USB_SSP_GEN_1x2)
2501                 reg |= DWC3_DCFG_SUPERSPEED;
2502         else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2503                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2504
2505         if (ssp_rate != USB_SSP_GEN_2x1 &&
2506             dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2507                 reg |= DWC3_DCFG_NUMLANES(1);
2508
2509         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2510 }
2511
2512 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2513 {
2514         enum usb_device_speed   speed;
2515         u32                     reg;
2516
2517         speed = dwc->gadget_max_speed;
2518         if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2519                 speed = dwc->maximum_speed;
2520
2521         if (speed == USB_SPEED_SUPER_PLUS &&
2522             DWC3_IP_IS(DWC32)) {
2523                 __dwc3_gadget_set_ssp_rate(dwc);
2524                 return;
2525         }
2526
2527         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2528         reg &= ~(DWC3_DCFG_SPEED_MASK);
2529
2530         /*
2531          * WORKAROUND: DWC3 revision < 2.20a have an issue
2532          * which would cause metastability state on Run/Stop
2533          * bit if we try to force the IP to USB2-only mode.
2534          *
2535          * Because of that, we cannot configure the IP to any
2536          * speed other than the SuperSpeed
2537          *
2538          * Refers to:
2539          *
2540          * STAR#9000525659: Clock Domain Crossing on DCTL in
2541          * USB 2.0 Mode
2542          */
2543         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2544             !dwc->dis_metastability_quirk) {
2545                 reg |= DWC3_DCFG_SUPERSPEED;
2546         } else {
2547                 switch (speed) {
2548                 case USB_SPEED_FULL:
2549                         reg |= DWC3_DCFG_FULLSPEED;
2550                         break;
2551                 case USB_SPEED_HIGH:
2552                         reg |= DWC3_DCFG_HIGHSPEED;
2553                         break;
2554                 case USB_SPEED_SUPER:
2555                         reg |= DWC3_DCFG_SUPERSPEED;
2556                         break;
2557                 case USB_SPEED_SUPER_PLUS:
2558                         if (DWC3_IP_IS(DWC3))
2559                                 reg |= DWC3_DCFG_SUPERSPEED;
2560                         else
2561                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2562                         break;
2563                 default:
2564                         dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2565
2566                         if (DWC3_IP_IS(DWC3))
2567                                 reg |= DWC3_DCFG_SUPERSPEED;
2568                         else
2569                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2570                 }
2571         }
2572
2573         if (DWC3_IP_IS(DWC32) &&
2574             speed > USB_SPEED_UNKNOWN &&
2575             speed < USB_SPEED_SUPER_PLUS)
2576                 reg &= ~DWC3_DCFG_NUMLANES(~0);
2577
2578         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2579 }
2580
2581 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
2582 {
2583         u32                     reg;
2584         u32                     timeout = 2000;
2585
2586         if (pm_runtime_suspended(dwc->dev))
2587                 return 0;
2588
2589         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2590         if (is_on) {
2591                 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2592                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
2593                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
2594                 }
2595
2596                 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2597                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2598                 reg |= DWC3_DCTL_RUN_STOP;
2599
2600                 __dwc3_gadget_set_speed(dwc);
2601                 dwc->pullups_connected = true;
2602         } else {
2603                 reg &= ~DWC3_DCTL_RUN_STOP;
2604
2605                 dwc->pullups_connected = false;
2606         }
2607
2608         dwc3_gadget_dctl_write_safe(dwc, reg);
2609
2610         do {
2611                 usleep_range(1000, 2000);
2612                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2613                 reg &= DWC3_DSTS_DEVCTRLHLT;
2614         } while (--timeout && !(!is_on ^ !reg));
2615
2616         if (!timeout)
2617                 return -ETIMEDOUT;
2618
2619         return 0;
2620 }
2621
2622 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2623 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2624 static int __dwc3_gadget_start(struct dwc3 *dwc);
2625
2626 static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2627 {
2628         unsigned long flags;
2629         int ret;
2630
2631         spin_lock_irqsave(&dwc->lock, flags);
2632         if (!dwc->pullups_connected) {
2633                 spin_unlock_irqrestore(&dwc->lock, flags);
2634                 return 0;
2635         }
2636
2637         dwc->connected = false;
2638
2639         /*
2640          * Attempt to end pending SETUP status phase, and not wait for the
2641          * function to do so.
2642          */
2643         if (dwc->delayed_status)
2644                 dwc3_ep0_send_delayed_status(dwc);
2645
2646         /*
2647          * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2648          * Section 4.1.8 Table 4-7, it states that for a device-initiated
2649          * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2650          * command for any active transfers" before clearing the RunStop
2651          * bit.
2652          */
2653         dwc3_stop_active_transfers(dwc);
2654         spin_unlock_irqrestore(&dwc->lock, flags);
2655
2656         /*
2657          * Per databook, when we want to stop the gadget, if a control transfer
2658          * is still in process, complete it and get the core into setup phase.
2659          * In case the host is unresponsive to a SETUP transaction, forcefully
2660          * stall the transfer, and move back to the SETUP phase, so that any
2661          * pending endxfers can be executed.
2662          */
2663         if (dwc->ep0state != EP0_SETUP_PHASE) {
2664                 reinit_completion(&dwc->ep0_in_setup);
2665
2666                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2667                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2668                 if (ret == 0) {
2669                         dev_warn(dwc->dev, "wait for SETUP phase timed out\n");
2670                         spin_lock_irqsave(&dwc->lock, flags);
2671                         dwc3_ep0_reset_state(dwc);
2672                         spin_unlock_irqrestore(&dwc->lock, flags);
2673                 }
2674         }
2675
2676         /*
2677          * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2678          * driver needs to acknowledge them before the controller can halt.
2679          * Simply let the interrupt handler acknowledges and handle the
2680          * remaining event generated by the controller while polling for
2681          * DSTS.DEVCTLHLT.
2682          */
2683         ret = dwc3_gadget_run_stop(dwc, false);
2684
2685         /*
2686          * Stop the gadget after controller is halted, so that if needed, the
2687          * events to update EP0 state can still occur while the run/stop
2688          * routine polls for the halted state.  DEVTEN is cleared as part of
2689          * gadget stop.
2690          */
2691         spin_lock_irqsave(&dwc->lock, flags);
2692         __dwc3_gadget_stop(dwc);
2693         spin_unlock_irqrestore(&dwc->lock, flags);
2694
2695         return ret;
2696 }
2697
2698 static int dwc3_gadget_soft_connect(struct dwc3 *dwc)
2699 {
2700         int ret;
2701
2702         /*
2703          * In the Synopsys DWC_usb31 1.90a programming guide section
2704          * 4.1.9, it specifies that for a reconnect after a
2705          * device-initiated disconnect requires a core soft reset
2706          * (DCTL.CSftRst) before enabling the run/stop bit.
2707          */
2708         ret = dwc3_core_soft_reset(dwc);
2709         if (ret)
2710                 return ret;
2711
2712         dwc3_event_buffers_setup(dwc);
2713         __dwc3_gadget_start(dwc);
2714         return dwc3_gadget_run_stop(dwc, true);
2715 }
2716
2717 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2718 {
2719         struct dwc3             *dwc = gadget_to_dwc(g);
2720         int                     ret;
2721
2722         is_on = !!is_on;
2723
2724         dwc->softconnect = is_on;
2725
2726         /*
2727          * Avoid issuing a runtime resume if the device is already in the
2728          * suspended state during gadget disconnect.  DWC3 gadget was already
2729          * halted/stopped during runtime suspend.
2730          */
2731         if (!is_on) {
2732                 pm_runtime_barrier(dwc->dev);
2733                 if (pm_runtime_suspended(dwc->dev))
2734                         return 0;
2735         }
2736
2737         /*
2738          * Check the return value for successful resume, or error.  For a
2739          * successful resume, the DWC3 runtime PM resume routine will handle
2740          * the run stop sequence, so avoid duplicate operations here.
2741          */
2742         ret = pm_runtime_get_sync(dwc->dev);
2743         if (!ret || ret < 0) {
2744                 pm_runtime_put(dwc->dev);
2745                 if (ret < 0)
2746                         pm_runtime_set_suspended(dwc->dev);
2747                 return ret;
2748         }
2749
2750         if (dwc->pullups_connected == is_on) {
2751                 pm_runtime_put(dwc->dev);
2752                 return 0;
2753         }
2754
2755         synchronize_irq(dwc->irq_gadget);
2756
2757         if (!is_on)
2758                 ret = dwc3_gadget_soft_disconnect(dwc);
2759         else
2760                 ret = dwc3_gadget_soft_connect(dwc);
2761
2762         pm_runtime_put(dwc->dev);
2763
2764         return ret;
2765 }
2766
2767 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2768 {
2769         u32                     reg;
2770
2771         /* Enable all but Start and End of Frame IRQs */
2772         reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2773                         DWC3_DEVTEN_CMDCMPLTEN |
2774                         DWC3_DEVTEN_ERRTICERREN |
2775                         DWC3_DEVTEN_WKUPEVTEN |
2776                         DWC3_DEVTEN_CONNECTDONEEN |
2777                         DWC3_DEVTEN_USBRSTEN |
2778                         DWC3_DEVTEN_DISCONNEVTEN);
2779
2780         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2781                 reg |= DWC3_DEVTEN_ULSTCNGEN;
2782
2783         /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2784         if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2785                 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2786
2787         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2788 }
2789
2790 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2791 {
2792         /* mask all interrupts */
2793         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2794 }
2795
2796 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2797 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2798
2799 /**
2800  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2801  * @dwc: pointer to our context structure
2802  *
2803  * The following looks like complex but it's actually very simple. In order to
2804  * calculate the number of packets we can burst at once on OUT transfers, we're
2805  * gonna use RxFIFO size.
2806  *
2807  * To calculate RxFIFO size we need two numbers:
2808  * MDWIDTH = size, in bits, of the internal memory bus
2809  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2810  *
2811  * Given these two numbers, the formula is simple:
2812  *
2813  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2814  *
2815  * 24 bytes is for 3x SETUP packets
2816  * 16 bytes is a clock domain crossing tolerance
2817  *
2818  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2819  */
2820 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2821 {
2822         u32 ram2_depth;
2823         u32 mdwidth;
2824         u32 nump;
2825         u32 reg;
2826
2827         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2828         mdwidth = dwc3_mdwidth(dwc);
2829
2830         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2831         nump = min_t(u32, nump, 16);
2832
2833         /* update NumP */
2834         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2835         reg &= ~DWC3_DCFG_NUMP_MASK;
2836         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2837         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2838 }
2839
2840 static int __dwc3_gadget_start(struct dwc3 *dwc)
2841 {
2842         struct dwc3_ep          *dep;
2843         int                     ret = 0;
2844         u32                     reg;
2845
2846         /*
2847          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2848          * the core supports IMOD, disable it.
2849          */
2850         if (dwc->imod_interval) {
2851                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2852                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2853         } else if (dwc3_has_imod(dwc)) {
2854                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2855         }
2856
2857         /*
2858          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2859          * field instead of letting dwc3 itself calculate that automatically.
2860          *
2861          * This way, we maximize the chances that we'll be able to get several
2862          * bursts of data without going through any sort of endpoint throttling.
2863          */
2864         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2865         if (DWC3_IP_IS(DWC3))
2866                 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2867         else
2868                 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2869
2870         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2871
2872         dwc3_gadget_setup_nump(dwc);
2873
2874         /*
2875          * Currently the controller handles single stream only. So, Ignore
2876          * Packet Pending bit for stream selection and don't search for another
2877          * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2878          * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2879          * the stream performance.
2880          */
2881         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2882         reg |= DWC3_DCFG_IGNSTRMPP;
2883         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2884
2885         /* Enable MST by default if the device is capable of MST */
2886         if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2887                 reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2888                 reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2889                 dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2890         }
2891
2892         /* Start with SuperSpeed Default */
2893         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2894
2895         ret = dwc3_gadget_start_config(dwc, 0);
2896         if (ret) {
2897                 dev_err(dwc->dev, "failed to config endpoints\n");
2898                 return ret;
2899         }
2900
2901         dep = dwc->eps[0];
2902         dep->flags = 0;
2903         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2904         if (ret) {
2905                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2906                 goto err0;
2907         }
2908
2909         dep = dwc->eps[1];
2910         dep->flags = 0;
2911         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2912         if (ret) {
2913                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2914                 goto err1;
2915         }
2916
2917         /* begin to receive SETUP packets */
2918         dwc->ep0state = EP0_SETUP_PHASE;
2919         dwc->ep0_bounced = false;
2920         dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2921         dwc->delayed_status = false;
2922         dwc3_ep0_out_start(dwc);
2923
2924         dwc3_gadget_enable_irq(dwc);
2925         dwc3_enable_susphy(dwc, true);
2926
2927         return 0;
2928
2929 err1:
2930         __dwc3_gadget_ep_disable(dwc->eps[0]);
2931
2932 err0:
2933         return ret;
2934 }
2935
2936 static int dwc3_gadget_start(struct usb_gadget *g,
2937                 struct usb_gadget_driver *driver)
2938 {
2939         struct dwc3             *dwc = gadget_to_dwc(g);
2940         unsigned long           flags;
2941         int                     ret;
2942         int                     irq;
2943
2944         irq = dwc->irq_gadget;
2945         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2946                         IRQF_SHARED, "dwc3", dwc->ev_buf);
2947         if (ret) {
2948                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2949                                 irq, ret);
2950                 return ret;
2951         }
2952
2953         spin_lock_irqsave(&dwc->lock, flags);
2954         dwc->gadget_driver      = driver;
2955         spin_unlock_irqrestore(&dwc->lock, flags);
2956
2957         if (dwc->sys_wakeup)
2958                 device_wakeup_enable(dwc->sysdev);
2959
2960         return 0;
2961 }
2962
2963 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2964 {
2965         dwc3_gadget_disable_irq(dwc);
2966         __dwc3_gadget_ep_disable(dwc->eps[0]);
2967         __dwc3_gadget_ep_disable(dwc->eps[1]);
2968 }
2969
2970 static int dwc3_gadget_stop(struct usb_gadget *g)
2971 {
2972         struct dwc3             *dwc = gadget_to_dwc(g);
2973         unsigned long           flags;
2974
2975         if (dwc->sys_wakeup)
2976                 device_wakeup_disable(dwc->sysdev);
2977
2978         spin_lock_irqsave(&dwc->lock, flags);
2979         dwc->gadget_driver      = NULL;
2980         dwc->max_cfg_eps = 0;
2981         spin_unlock_irqrestore(&dwc->lock, flags);
2982
2983         free_irq(dwc->irq_gadget, dwc->ev_buf);
2984
2985         return 0;
2986 }
2987
2988 static void dwc3_gadget_config_params(struct usb_gadget *g,
2989                                       struct usb_dcd_config_params *params)
2990 {
2991         struct dwc3             *dwc = gadget_to_dwc(g);
2992
2993         params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2994         params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2995
2996         /* Recommended BESL */
2997         if (!dwc->dis_enblslpm_quirk) {
2998                 /*
2999                  * If the recommended BESL baseline is 0 or if the BESL deep is
3000                  * less than 2, Microsoft's Windows 10 host usb stack will issue
3001                  * a usb reset immediately after it receives the extended BOS
3002                  * descriptor and the enumeration will fail. To maintain
3003                  * compatibility with the Windows' usb stack, let's set the
3004                  * recommended BESL baseline to 1 and clamp the BESL deep to be
3005                  * within 2 to 15.
3006                  */
3007                 params->besl_baseline = 1;
3008                 if (dwc->is_utmi_l1_suspend)
3009                         params->besl_deep =
3010                                 clamp_t(u8, dwc->hird_threshold, 2, 15);
3011         }
3012
3013         /* U1 Device exit Latency */
3014         if (dwc->dis_u1_entry_quirk)
3015                 params->bU1devExitLat = 0;
3016         else
3017                 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
3018
3019         /* U2 Device exit Latency */
3020         if (dwc->dis_u2_entry_quirk)
3021                 params->bU2DevExitLat = 0;
3022         else
3023                 params->bU2DevExitLat =
3024                                 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
3025 }
3026
3027 static void dwc3_gadget_set_speed(struct usb_gadget *g,
3028                                   enum usb_device_speed speed)
3029 {
3030         struct dwc3             *dwc = gadget_to_dwc(g);
3031         unsigned long           flags;
3032
3033         spin_lock_irqsave(&dwc->lock, flags);
3034         dwc->gadget_max_speed = speed;
3035         spin_unlock_irqrestore(&dwc->lock, flags);
3036 }
3037
3038 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
3039                                      enum usb_ssp_rate rate)
3040 {
3041         struct dwc3             *dwc = gadget_to_dwc(g);
3042         unsigned long           flags;
3043
3044         spin_lock_irqsave(&dwc->lock, flags);
3045         dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
3046         dwc->gadget_ssp_rate = rate;
3047         spin_unlock_irqrestore(&dwc->lock, flags);
3048 }
3049
3050 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
3051 {
3052         struct dwc3             *dwc = gadget_to_dwc(g);
3053         union power_supply_propval      val = {0};
3054         int                             ret;
3055
3056         if (dwc->usb2_phy)
3057                 return usb_phy_set_power(dwc->usb2_phy, mA);
3058
3059         if (!dwc->usb_psy)
3060                 return -EOPNOTSUPP;
3061
3062         val.intval = 1000 * mA;
3063         ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
3064
3065         return ret;
3066 }
3067
3068 /**
3069  * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
3070  * @g: pointer to the USB gadget
3071  *
3072  * Used to record the maximum number of endpoints being used in a USB composite
3073  * device. (across all configurations)  This is to be used in the calculation
3074  * of the TXFIFO sizes when resizing internal memory for individual endpoints.
3075  * It will help ensured that the resizing logic reserves enough space for at
3076  * least one max packet.
3077  */
3078 static int dwc3_gadget_check_config(struct usb_gadget *g)
3079 {
3080         struct dwc3 *dwc = gadget_to_dwc(g);
3081         struct usb_ep *ep;
3082         int fifo_size = 0;
3083         int ram1_depth;
3084         int ep_num = 0;
3085
3086         if (!dwc->do_fifo_resize)
3087                 return 0;
3088
3089         list_for_each_entry(ep, &g->ep_list, ep_list) {
3090                 /* Only interested in the IN endpoints */
3091                 if (ep->claimed && (ep->address & USB_DIR_IN))
3092                         ep_num++;
3093         }
3094
3095         if (ep_num <= dwc->max_cfg_eps)
3096                 return 0;
3097
3098         /* Update the max number of eps in the composition */
3099         dwc->max_cfg_eps = ep_num;
3100
3101         fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
3102         /* Based on the equation, increment by one for every ep */
3103         fifo_size += dwc->max_cfg_eps;
3104
3105         /* Check if we can fit a single fifo per endpoint */
3106         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
3107         if (fifo_size > ram1_depth)
3108                 return -ENOMEM;
3109
3110         return 0;
3111 }
3112
3113 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
3114 {
3115         struct dwc3             *dwc = gadget_to_dwc(g);
3116         unsigned long           flags;
3117
3118         spin_lock_irqsave(&dwc->lock, flags);
3119         dwc->async_callbacks = enable;
3120         spin_unlock_irqrestore(&dwc->lock, flags);
3121 }
3122
3123 static const struct usb_gadget_ops dwc3_gadget_ops = {
3124         .get_frame              = dwc3_gadget_get_frame,
3125         .wakeup                 = dwc3_gadget_wakeup,
3126         .func_wakeup            = dwc3_gadget_func_wakeup,
3127         .set_remote_wakeup      = dwc3_gadget_set_remote_wakeup,
3128         .set_selfpowered        = dwc3_gadget_set_selfpowered,
3129         .pullup                 = dwc3_gadget_pullup,
3130         .udc_start              = dwc3_gadget_start,
3131         .udc_stop               = dwc3_gadget_stop,
3132         .udc_set_speed          = dwc3_gadget_set_speed,
3133         .udc_set_ssp_rate       = dwc3_gadget_set_ssp_rate,
3134         .get_config_params      = dwc3_gadget_config_params,
3135         .vbus_draw              = dwc3_gadget_vbus_draw,
3136         .check_config           = dwc3_gadget_check_config,
3137         .udc_async_callbacks    = dwc3_gadget_async_callbacks,
3138 };
3139
3140 /* -------------------------------------------------------------------------- */
3141
3142 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
3143 {
3144         struct dwc3 *dwc = dep->dwc;
3145
3146         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
3147         dep->endpoint.maxburst = 1;
3148         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
3149         if (!dep->direction)
3150                 dwc->gadget->ep0 = &dep->endpoint;
3151
3152         dep->endpoint.caps.type_control = true;
3153
3154         return 0;
3155 }
3156
3157 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
3158 {
3159         struct dwc3 *dwc = dep->dwc;
3160         u32 mdwidth;
3161         int size;
3162         int maxpacket;
3163
3164         mdwidth = dwc3_mdwidth(dwc);
3165
3166         /* MDWIDTH is represented in bits, we need it in bytes */
3167         mdwidth /= 8;
3168
3169         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
3170         if (DWC3_IP_IS(DWC3))
3171                 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
3172         else
3173                 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
3174
3175         /*
3176          * maxpacket size is determined as part of the following, after assuming
3177          * a mult value of one maxpacket:
3178          * DWC3 revision 280A and prior:
3179          * fifo_size = mult * (max_packet / mdwidth) + 1;
3180          * maxpacket = mdwidth * (fifo_size - 1);
3181          *
3182          * DWC3 revision 290A and onwards:
3183          * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
3184          * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
3185          */
3186         if (DWC3_VER_IS_PRIOR(DWC3, 290A))
3187                 maxpacket = mdwidth * (size - 1);
3188         else
3189                 maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
3190
3191         /* Functionally, space for one max packet is sufficient */
3192         size = min_t(int, maxpacket, 1024);
3193         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3194
3195         dep->endpoint.max_streams = 16;
3196         dep->endpoint.ops = &dwc3_gadget_ep_ops;
3197         list_add_tail(&dep->endpoint.ep_list,
3198                         &dwc->gadget->ep_list);
3199         dep->endpoint.caps.type_iso = true;
3200         dep->endpoint.caps.type_bulk = true;
3201         dep->endpoint.caps.type_int = true;
3202
3203         return dwc3_alloc_trb_pool(dep);
3204 }
3205
3206 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
3207 {
3208         struct dwc3 *dwc = dep->dwc;
3209         u32 mdwidth;
3210         int size;
3211
3212         mdwidth = dwc3_mdwidth(dwc);
3213
3214         /* MDWIDTH is represented in bits, convert to bytes */
3215         mdwidth /= 8;
3216
3217         /* All OUT endpoints share a single RxFIFO space */
3218         size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3219         if (DWC3_IP_IS(DWC3))
3220                 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3221         else
3222                 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
3223
3224         /* FIFO depth is in MDWDITH bytes */
3225         size *= mdwidth;
3226
3227         /*
3228          * To meet performance requirement, a minimum recommended RxFIFO size
3229          * is defined as follow:
3230          * RxFIFO size >= (3 x MaxPacketSize) +
3231          * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3232          *
3233          * Then calculate the max packet limit as below.
3234          */
3235         size -= (3 * 8) + 16;
3236         if (size < 0)
3237                 size = 0;
3238         else
3239                 size /= 3;
3240
3241         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3242         dep->endpoint.max_streams = 16;
3243         dep->endpoint.ops = &dwc3_gadget_ep_ops;
3244         list_add_tail(&dep->endpoint.ep_list,
3245                         &dwc->gadget->ep_list);
3246         dep->endpoint.caps.type_iso = true;
3247         dep->endpoint.caps.type_bulk = true;
3248         dep->endpoint.caps.type_int = true;
3249
3250         return dwc3_alloc_trb_pool(dep);
3251 }
3252
3253 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3254 {
3255         struct dwc3_ep                  *dep;
3256         bool                            direction = epnum & 1;
3257         int                             ret;
3258         u8                              num = epnum >> 1;
3259
3260         dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3261         if (!dep)
3262                 return -ENOMEM;
3263
3264         dep->dwc = dwc;
3265         dep->number = epnum;
3266         dep->direction = direction;
3267         dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3268         dwc->eps[epnum] = dep;
3269         dep->combo_num = 0;
3270         dep->start_cmd_status = 0;
3271
3272         snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3273                         direction ? "in" : "out");
3274
3275         dep->endpoint.name = dep->name;
3276
3277         if (!(dep->number > 1)) {
3278                 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3279                 dep->endpoint.comp_desc = NULL;
3280         }
3281
3282         if (num == 0)
3283                 ret = dwc3_gadget_init_control_endpoint(dep);
3284         else if (direction)
3285                 ret = dwc3_gadget_init_in_endpoint(dep);
3286         else
3287                 ret = dwc3_gadget_init_out_endpoint(dep);
3288
3289         if (ret)
3290                 return ret;
3291
3292         dep->endpoint.caps.dir_in = direction;
3293         dep->endpoint.caps.dir_out = !direction;
3294
3295         INIT_LIST_HEAD(&dep->pending_list);
3296         INIT_LIST_HEAD(&dep->started_list);
3297         INIT_LIST_HEAD(&dep->cancelled_list);
3298
3299         dwc3_debugfs_create_endpoint_dir(dep);
3300
3301         return 0;
3302 }
3303
3304 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3305 {
3306         u8                              epnum;
3307
3308         INIT_LIST_HEAD(&dwc->gadget->ep_list);
3309
3310         for (epnum = 0; epnum < total; epnum++) {
3311                 int                     ret;
3312
3313                 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3314                 if (ret)
3315                         return ret;
3316         }
3317
3318         return 0;
3319 }
3320
3321 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3322 {
3323         struct dwc3_ep                  *dep;
3324         u8                              epnum;
3325
3326         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3327                 dep = dwc->eps[epnum];
3328                 if (!dep)
3329                         continue;
3330                 /*
3331                  * Physical endpoints 0 and 1 are special; they form the
3332                  * bi-directional USB endpoint 0.
3333                  *
3334                  * For those two physical endpoints, we don't allocate a TRB
3335                  * pool nor do we add them the endpoints list. Due to that, we
3336                  * shouldn't do these two operations otherwise we would end up
3337                  * with all sorts of bugs when removing dwc3.ko.
3338                  */
3339                 if (epnum != 0 && epnum != 1) {
3340                         dwc3_free_trb_pool(dep);
3341                         list_del(&dep->endpoint.ep_list);
3342                 }
3343
3344                 dwc3_debugfs_remove_endpoint_dir(dep);
3345                 kfree(dep);
3346         }
3347 }
3348
3349 /* -------------------------------------------------------------------------- */
3350
3351 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3352                 struct dwc3_request *req, struct dwc3_trb *trb,
3353                 const struct dwc3_event_depevt *event, int status, int chain)
3354 {
3355         unsigned int            count;
3356
3357         dwc3_ep_inc_deq(dep);
3358
3359         trace_dwc3_complete_trb(dep, trb);
3360         req->num_trbs--;
3361
3362         /*
3363          * If we're in the middle of series of chained TRBs and we
3364          * receive a short transfer along the way, DWC3 will skip
3365          * through all TRBs including the last TRB in the chain (the
3366          * where CHN bit is zero. DWC3 will also avoid clearing HWO
3367          * bit and SW has to do it manually.
3368          *
3369          * We're going to do that here to avoid problems of HW trying
3370          * to use bogus TRBs for transfers.
3371          */
3372         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3373                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3374
3375         /*
3376          * For isochronous transfers, the first TRB in a service interval must
3377          * have the Isoc-First type. Track and report its interval frame number.
3378          */
3379         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3380             (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3381                 unsigned int frame_number;
3382
3383                 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3384                 frame_number &= ~(dep->interval - 1);
3385                 req->request.frame_number = frame_number;
3386         }
3387
3388         /*
3389          * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3390          * this TRB points to the bounce buffer address, it's a MPS alignment
3391          * TRB. Don't add it to req->remaining calculation.
3392          */
3393         if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3394             trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3395                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3396                 return 1;
3397         }
3398
3399         count = trb->size & DWC3_TRB_SIZE_MASK;
3400         req->remaining += count;
3401
3402         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3403                 return 1;
3404
3405         if (event->status & DEPEVT_STATUS_SHORT && !chain)
3406                 return 1;
3407
3408         if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
3409             DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
3410                 return 1;
3411
3412         if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3413             (trb->ctrl & DWC3_TRB_CTRL_LST))
3414                 return 1;
3415
3416         return 0;
3417 }
3418
3419 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3420                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3421                 int status)
3422 {
3423         struct dwc3_trb *trb;
3424         struct scatterlist *sg = req->sg;
3425         struct scatterlist *s;
3426         unsigned int num_queued = req->num_queued_sgs;
3427         unsigned int i;
3428         int ret = 0;
3429
3430         for_each_sg(sg, s, num_queued, i) {
3431                 trb = &dep->trb_pool[dep->trb_dequeue];
3432
3433                 req->sg = sg_next(s);
3434                 req->num_queued_sgs--;
3435
3436                 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3437                                 trb, event, status, true);
3438                 if (ret)
3439                         break;
3440         }
3441
3442         return ret;
3443 }
3444
3445 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3446                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3447                 int status)
3448 {
3449         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3450
3451         return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3452                         event, status, false);
3453 }
3454
3455 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3456 {
3457         return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3458 }
3459
3460 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3461                 const struct dwc3_event_depevt *event,
3462                 struct dwc3_request *req, int status)
3463 {
3464         int request_status;
3465         int ret;
3466
3467         if (req->request.num_mapped_sgs)
3468                 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3469                                 status);
3470         else
3471                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3472                                 status);
3473
3474         req->request.actual = req->request.length - req->remaining;
3475
3476         if (!dwc3_gadget_ep_request_completed(req))
3477                 goto out;
3478
3479         if (req->needs_extra_trb) {
3480                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3481                                 status);
3482                 req->needs_extra_trb = false;
3483         }
3484
3485         /*
3486          * The event status only reflects the status of the TRB with IOC set.
3487          * For the requests that don't set interrupt on completion, the driver
3488          * needs to check and return the status of the completed TRBs associated
3489          * with the request. Use the status of the last TRB of the request.
3490          */
3491         if (req->request.no_interrupt) {
3492                 struct dwc3_trb *trb;
3493
3494                 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3495                 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3496                 case DWC3_TRBSTS_MISSED_ISOC:
3497                         /* Isoc endpoint only */
3498                         request_status = -EXDEV;
3499                         break;
3500                 case DWC3_TRB_STS_XFER_IN_PROG:
3501                         /* Applicable when End Transfer with ForceRM=0 */
3502                 case DWC3_TRBSTS_SETUP_PENDING:
3503                         /* Control endpoint only */
3504                 case DWC3_TRBSTS_OK:
3505                 default:
3506                         request_status = 0;
3507                         break;
3508                 }
3509         } else {
3510                 request_status = status;
3511         }
3512
3513         dwc3_gadget_giveback(dep, req, request_status);
3514
3515 out:
3516         return ret;
3517 }
3518
3519 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3520                 const struct dwc3_event_depevt *event, int status)
3521 {
3522         struct dwc3_request     *req;
3523
3524         while (!list_empty(&dep->started_list)) {
3525                 int ret;
3526
3527                 req = next_request(&dep->started_list);
3528                 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3529                                 req, status);
3530                 if (ret)
3531                         break;
3532                 /*
3533                  * The endpoint is disabled, let the dwc3_remove_requests()
3534                  * handle the cleanup.
3535                  */
3536                 if (!dep->endpoint.desc)
3537                         break;
3538         }
3539 }
3540
3541 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3542 {
3543         struct dwc3_request     *req;
3544         struct dwc3             *dwc = dep->dwc;
3545
3546         if (!dep->endpoint.desc || !dwc->pullups_connected ||
3547             !dwc->connected)
3548                 return false;
3549
3550         if (!list_empty(&dep->pending_list))
3551                 return true;
3552
3553         /*
3554          * We only need to check the first entry of the started list. We can
3555          * assume the completed requests are removed from the started list.
3556          */
3557         req = next_request(&dep->started_list);
3558         if (!req)
3559                 return false;
3560
3561         return !dwc3_gadget_ep_request_completed(req);
3562 }
3563
3564 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3565                 const struct dwc3_event_depevt *event)
3566 {
3567         dep->frame_number = event->parameters;
3568 }
3569
3570 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3571                 const struct dwc3_event_depevt *event, int status)
3572 {
3573         struct dwc3             *dwc = dep->dwc;
3574         bool                    no_started_trb = true;
3575
3576         dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3577
3578         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3579                 goto out;
3580
3581         if (!dep->endpoint.desc)
3582                 return no_started_trb;
3583
3584         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3585                 list_empty(&dep->started_list) &&
3586                 (list_empty(&dep->pending_list) || status == -EXDEV))
3587                 dwc3_stop_active_transfer(dep, true, true);
3588         else if (dwc3_gadget_ep_should_continue(dep))
3589                 if (__dwc3_gadget_kick_transfer(dep) == 0)
3590                         no_started_trb = false;
3591
3592 out:
3593         /*
3594          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3595          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3596          */
3597         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3598                 u32             reg;
3599                 int             i;
3600
3601                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3602                         dep = dwc->eps[i];
3603
3604                         if (!(dep->flags & DWC3_EP_ENABLED))
3605                                 continue;
3606
3607                         if (!list_empty(&dep->started_list))
3608                                 return no_started_trb;
3609                 }
3610
3611                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3612                 reg |= dwc->u1u2;
3613                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3614
3615                 dwc->u1u2 = 0;
3616         }
3617
3618         return no_started_trb;
3619 }
3620
3621 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3622                 const struct dwc3_event_depevt *event)
3623 {
3624         int status = 0;
3625
3626         if (!dep->endpoint.desc)
3627                 return;
3628
3629         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3630                 dwc3_gadget_endpoint_frame_from_event(dep, event);
3631
3632         if (event->status & DEPEVT_STATUS_BUSERR)
3633                 status = -ECONNRESET;
3634
3635         if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3636                 status = -EXDEV;
3637
3638         dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3639 }
3640
3641 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3642                 const struct dwc3_event_depevt *event)
3643 {
3644         int status = 0;
3645
3646         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3647
3648         if (event->status & DEPEVT_STATUS_BUSERR)
3649                 status = -ECONNRESET;
3650
3651         if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3652                 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3653 }
3654
3655 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3656                 const struct dwc3_event_depevt *event)
3657 {
3658         dwc3_gadget_endpoint_frame_from_event(dep, event);
3659
3660         /*
3661          * The XferNotReady event is generated only once before the endpoint
3662          * starts. It will be generated again when END_TRANSFER command is
3663          * issued. For some controller versions, the XferNotReady event may be
3664          * generated while the END_TRANSFER command is still in process. Ignore
3665          * it and wait for the next XferNotReady event after the command is
3666          * completed.
3667          */
3668         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3669                 return;
3670
3671         (void) __dwc3_gadget_start_isoc(dep);
3672 }
3673
3674 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3675                 const struct dwc3_event_depevt *event)
3676 {
3677         u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3678
3679         if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3680                 return;
3681
3682         /*
3683          * The END_TRANSFER command will cause the controller to generate a
3684          * NoStream Event, and it's not due to the host DP NoStream rejection.
3685          * Ignore the next NoStream event.
3686          */
3687         if (dep->stream_capable)
3688                 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3689
3690         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3691         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3692         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3693
3694         if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3695                 struct dwc3 *dwc = dep->dwc;
3696
3697                 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3698                 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3699                         struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3700
3701                         dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3702                         if (dwc->delayed_status)
3703                                 __dwc3_gadget_ep0_set_halt(ep0, 1);
3704                         return;
3705                 }
3706
3707                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3708                 if (dwc->clear_stall_protocol == dep->number)
3709                         dwc3_ep0_send_delayed_status(dwc);
3710         }
3711
3712         if ((dep->flags & DWC3_EP_DELAY_START) &&
3713             !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3714                 __dwc3_gadget_kick_transfer(dep);
3715
3716         dep->flags &= ~DWC3_EP_DELAY_START;
3717 }
3718
3719 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3720                 const struct dwc3_event_depevt *event)
3721 {
3722         struct dwc3 *dwc = dep->dwc;
3723
3724         if (event->status == DEPEVT_STREAMEVT_FOUND) {
3725                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3726                 goto out;
3727         }
3728
3729         /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3730         switch (event->parameters) {
3731         case DEPEVT_STREAM_PRIME:
3732                 /*
3733                  * If the host can properly transition the endpoint state from
3734                  * idle to prime after a NoStream rejection, there's no need to
3735                  * force restarting the endpoint to reinitiate the stream. To
3736                  * simplify the check, assume the host follows the USB spec if
3737                  * it primed the endpoint more than once.
3738                  */
3739                 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3740                         if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3741                                 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3742                         else
3743                                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3744                 }
3745
3746                 break;
3747         case DEPEVT_STREAM_NOSTREAM:
3748                 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3749                     !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3750                     (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3751                      !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3752                         break;
3753
3754                 /*
3755                  * If the host rejects a stream due to no active stream, by the
3756                  * USB and xHCI spec, the endpoint will be put back to idle
3757                  * state. When the host is ready (buffer added/updated), it will
3758                  * prime the endpoint to inform the usb device controller. This
3759                  * triggers the device controller to issue ERDY to restart the
3760                  * stream. However, some hosts don't follow this and keep the
3761                  * endpoint in the idle state. No prime will come despite host
3762                  * streams are updated, and the device controller will not be
3763                  * triggered to generate ERDY to move the next stream data. To
3764                  * workaround this and maintain compatibility with various
3765                  * hosts, force to reinitiate the stream until the host is ready
3766                  * instead of waiting for the host to prime the endpoint.
3767                  */
3768                 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3769                         unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3770
3771                         dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3772                 } else {
3773                         dep->flags |= DWC3_EP_DELAY_START;
3774                         dwc3_stop_active_transfer(dep, true, true);
3775                         return;
3776                 }
3777                 break;
3778         }
3779
3780 out:
3781         dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3782 }
3783
3784 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3785                 const struct dwc3_event_depevt *event)
3786 {
3787         struct dwc3_ep          *dep;
3788         u8                      epnum = event->endpoint_number;
3789
3790         dep = dwc->eps[epnum];
3791
3792         if (!(dep->flags & DWC3_EP_ENABLED)) {
3793                 if ((epnum > 1) && !(dep->flags & DWC3_EP_TRANSFER_STARTED))
3794                         return;
3795
3796                 /* Handle only EPCMDCMPLT when EP disabled */
3797                 if ((event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) &&
3798                         !(epnum <= 1 && event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE))
3799                         return;
3800         }
3801
3802         if (epnum == 0 || epnum == 1) {
3803                 dwc3_ep0_interrupt(dwc, event);
3804                 return;
3805         }
3806
3807         switch (event->endpoint_event) {
3808         case DWC3_DEPEVT_XFERINPROGRESS:
3809                 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3810                 break;
3811         case DWC3_DEPEVT_XFERNOTREADY:
3812                 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3813                 break;
3814         case DWC3_DEPEVT_EPCMDCMPLT:
3815                 dwc3_gadget_endpoint_command_complete(dep, event);
3816                 break;
3817         case DWC3_DEPEVT_XFERCOMPLETE:
3818                 dwc3_gadget_endpoint_transfer_complete(dep, event);
3819                 break;
3820         case DWC3_DEPEVT_STREAMEVT:
3821                 dwc3_gadget_endpoint_stream_event(dep, event);
3822                 break;
3823         case DWC3_DEPEVT_RXTXFIFOEVT:
3824                 break;
3825         default:
3826                 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
3827                 break;
3828         }
3829 }
3830
3831 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3832 {
3833         if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3834                 spin_unlock(&dwc->lock);
3835                 dwc->gadget_driver->disconnect(dwc->gadget);
3836                 spin_lock(&dwc->lock);
3837         }
3838 }
3839
3840 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3841 {
3842         if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3843                 spin_unlock(&dwc->lock);
3844                 dwc->gadget_driver->suspend(dwc->gadget);
3845                 spin_lock(&dwc->lock);
3846         }
3847 }
3848
3849 static void dwc3_resume_gadget(struct dwc3 *dwc)
3850 {
3851         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3852                 spin_unlock(&dwc->lock);
3853                 dwc->gadget_driver->resume(dwc->gadget);
3854                 spin_lock(&dwc->lock);
3855         }
3856 }
3857
3858 static void dwc3_reset_gadget(struct dwc3 *dwc)
3859 {
3860         if (!dwc->gadget_driver)
3861                 return;
3862
3863         if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3864                 spin_unlock(&dwc->lock);
3865                 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3866                 spin_lock(&dwc->lock);
3867         }
3868 }
3869
3870 void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3871         bool interrupt)
3872 {
3873         struct dwc3 *dwc = dep->dwc;
3874
3875         /*
3876          * Only issue End Transfer command to the control endpoint of a started
3877          * Data Phase. Typically we should only do so in error cases such as
3878          * invalid/unexpected direction as described in the control transfer
3879          * flow of the programming guide.
3880          */
3881         if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
3882                 return;
3883
3884         if (interrupt && (dep->flags & DWC3_EP_DELAY_STOP))
3885                 return;
3886
3887         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3888             (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3889                 return;
3890
3891         /*
3892          * If a Setup packet is received but yet to DMA out, the controller will
3893          * not process the End Transfer command of any endpoint. Polling of its
3894          * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
3895          * timeout. Delay issuing the End Transfer command until the Setup TRB is
3896          * prepared.
3897          */
3898         if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
3899                 dep->flags |= DWC3_EP_DELAY_STOP;
3900                 return;
3901         }
3902
3903         /*
3904          * NOTICE: We are violating what the Databook says about the
3905          * EndTransfer command. Ideally we would _always_ wait for the
3906          * EndTransfer Command Completion IRQ, but that's causing too
3907          * much trouble synchronizing between us and gadget driver.
3908          *
3909          * We have discussed this with the IP Provider and it was
3910          * suggested to giveback all requests here.
3911          *
3912          * Note also that a similar handling was tested by Synopsys
3913          * (thanks a lot Paul) and nothing bad has come out of it.
3914          * In short, what we're doing is issuing EndTransfer with
3915          * CMDIOC bit set and delay kicking transfer until the
3916          * EndTransfer command had completed.
3917          *
3918          * As of IP version 3.10a of the DWC_usb3 IP, the controller
3919          * supports a mode to work around the above limitation. The
3920          * software can poll the CMDACT bit in the DEPCMD register
3921          * after issuing a EndTransfer command. This mode is enabled
3922          * by writing GUCTL2[14]. This polling is already done in the
3923          * dwc3_send_gadget_ep_cmd() function so if the mode is
3924          * enabled, the EndTransfer command will have completed upon
3925          * returning from this function.
3926          *
3927          * This mode is NOT available on the DWC_usb31 IP.  In this
3928          * case, if the IOC bit is not set, then delay by 1ms
3929          * after issuing the EndTransfer command.  This allows for the
3930          * controller to handle the command completely before DWC3
3931          * remove requests attempts to unmap USB request buffers.
3932          */
3933
3934         __dwc3_stop_active_transfer(dep, force, interrupt);
3935 }
3936
3937 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3938 {
3939         u32 epnum;
3940
3941         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3942                 struct dwc3_ep *dep;
3943                 int ret;
3944
3945                 dep = dwc->eps[epnum];
3946                 if (!dep)
3947                         continue;
3948
3949                 if (!(dep->flags & DWC3_EP_STALL))
3950                         continue;
3951
3952                 dep->flags &= ~DWC3_EP_STALL;
3953
3954                 ret = dwc3_send_clear_stall_ep_cmd(dep);
3955                 WARN_ON_ONCE(ret);
3956         }
3957 }
3958
3959 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3960 {
3961         int                     reg;
3962
3963         dwc->suspended = false;
3964
3965         dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3966
3967         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3968         reg &= ~DWC3_DCTL_INITU1ENA;
3969         reg &= ~DWC3_DCTL_INITU2ENA;
3970         dwc3_gadget_dctl_write_safe(dwc, reg);
3971
3972         dwc->connected = false;
3973
3974         dwc3_disconnect_gadget(dwc);
3975
3976         dwc->gadget->speed = USB_SPEED_UNKNOWN;
3977         dwc->setup_packet_pending = false;
3978         dwc->gadget->wakeup_armed = false;
3979         dwc3_gadget_enable_linksts_evts(dwc, false);
3980         usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3981
3982         dwc3_ep0_reset_state(dwc);
3983
3984         /*
3985          * Request PM idle to address condition where usage count is
3986          * already decremented to zero, but waiting for the disconnect
3987          * interrupt to set dwc->connected to FALSE.
3988          */
3989         pm_request_idle(dwc->dev);
3990 }
3991
3992 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3993 {
3994         u32                     reg;
3995
3996         dwc->suspended = false;
3997
3998         /*
3999          * Ideally, dwc3_reset_gadget() would trigger the function
4000          * drivers to stop any active transfers through ep disable.
4001          * However, for functions which defer ep disable, such as mass
4002          * storage, we will need to rely on the call to stop active
4003          * transfers here, and avoid allowing of request queuing.
4004          */
4005         dwc->connected = false;
4006
4007         /*
4008          * WORKAROUND: DWC3 revisions <1.88a have an issue which
4009          * would cause a missing Disconnect Event if there's a
4010          * pending Setup Packet in the FIFO.
4011          *
4012          * There's no suggested workaround on the official Bug
4013          * report, which states that "unless the driver/application
4014          * is doing any special handling of a disconnect event,
4015          * there is no functional issue".
4016          *
4017          * Unfortunately, it turns out that we _do_ some special
4018          * handling of a disconnect event, namely complete all
4019          * pending transfers, notify gadget driver of the
4020          * disconnection, and so on.
4021          *
4022          * Our suggested workaround is to follow the Disconnect
4023          * Event steps here, instead, based on a setup_packet_pending
4024          * flag. Such flag gets set whenever we have a SETUP_PENDING
4025          * status for EP0 TRBs and gets cleared on XferComplete for the
4026          * same endpoint.
4027          *
4028          * Refers to:
4029          *
4030          * STAR#9000466709: RTL: Device : Disconnect event not
4031          * generated if setup packet pending in FIFO
4032          */
4033         if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
4034                 if (dwc->setup_packet_pending)
4035                         dwc3_gadget_disconnect_interrupt(dwc);
4036         }
4037
4038         dwc3_reset_gadget(dwc);
4039
4040         /*
4041          * From SNPS databook section 8.1.2, the EP0 should be in setup
4042          * phase. So ensure that EP0 is in setup phase by issuing a stall
4043          * and restart if EP0 is not in setup phase.
4044          */
4045         dwc3_ep0_reset_state(dwc);
4046
4047         /*
4048          * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
4049          * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
4050          * needs to ensure that it sends "a DEPENDXFER command for any active
4051          * transfers."
4052          */
4053         dwc3_stop_active_transfers(dwc);
4054         dwc->connected = true;
4055
4056         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4057         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
4058         dwc3_gadget_dctl_write_safe(dwc, reg);
4059         dwc->test_mode = false;
4060         dwc->gadget->wakeup_armed = false;
4061         dwc3_gadget_enable_linksts_evts(dwc, false);
4062         dwc3_clear_stall_all_ep(dwc);
4063
4064         /* Reset device address to zero */
4065         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4066         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
4067         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4068 }
4069
4070 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
4071 {
4072         struct dwc3_ep          *dep;
4073         int                     ret;
4074         u32                     reg;
4075         u8                      lanes = 1;
4076         u8                      speed;
4077
4078         if (!dwc->softconnect)
4079                 return;
4080
4081         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
4082         speed = reg & DWC3_DSTS_CONNECTSPD;
4083         dwc->speed = speed;
4084
4085         if (DWC3_IP_IS(DWC32))
4086                 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
4087
4088         dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4089
4090         /*
4091          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
4092          * each time on Connect Done.
4093          *
4094          * Currently we always use the reset value. If any platform
4095          * wants to set this to a different value, we need to add a
4096          * setting and update GCTL.RAMCLKSEL here.
4097          */
4098
4099         switch (speed) {
4100         case DWC3_DSTS_SUPERSPEED_PLUS:
4101                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4102                 dwc->gadget->ep0->maxpacket = 512;
4103                 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4104
4105                 if (lanes > 1)
4106                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
4107                 else
4108                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
4109                 break;
4110         case DWC3_DSTS_SUPERSPEED:
4111                 /*
4112                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
4113                  * would cause a missing USB3 Reset event.
4114                  *
4115                  * In such situations, we should force a USB3 Reset
4116                  * event by calling our dwc3_gadget_reset_interrupt()
4117                  * routine.
4118                  *
4119                  * Refers to:
4120                  *
4121                  * STAR#9000483510: RTL: SS : USB3 reset event may
4122                  * not be generated always when the link enters poll
4123                  */
4124                 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4125                         dwc3_gadget_reset_interrupt(dwc);
4126
4127                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4128                 dwc->gadget->ep0->maxpacket = 512;
4129                 dwc->gadget->speed = USB_SPEED_SUPER;
4130
4131                 if (lanes > 1) {
4132                         dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4133                         dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
4134                 }
4135                 break;
4136         case DWC3_DSTS_HIGHSPEED:
4137                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4138                 dwc->gadget->ep0->maxpacket = 64;
4139                 dwc->gadget->speed = USB_SPEED_HIGH;
4140                 break;
4141         case DWC3_DSTS_FULLSPEED:
4142                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4143                 dwc->gadget->ep0->maxpacket = 64;
4144                 dwc->gadget->speed = USB_SPEED_FULL;
4145                 break;
4146         }
4147
4148         dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
4149
4150         /* Enable USB2 LPM Capability */
4151
4152         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
4153             !dwc->usb2_gadget_lpm_disable &&
4154             (speed != DWC3_DSTS_SUPERSPEED) &&
4155             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
4156                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4157                 reg |= DWC3_DCFG_LPM_CAP;
4158                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4159
4160                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4161                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
4162
4163                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
4164                                             (dwc->is_utmi_l1_suspend << 4));
4165
4166                 /*
4167                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
4168                  * DCFG.LPMCap is set, core responses with an ACK and the
4169                  * BESL value in the LPM token is less than or equal to LPM
4170                  * NYET threshold.
4171                  */
4172                 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
4173                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
4174
4175                 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
4176                         reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
4177
4178                 dwc3_gadget_dctl_write_safe(dwc, reg);
4179         } else {
4180                 if (dwc->usb2_gadget_lpm_disable) {
4181                         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4182                         reg &= ~DWC3_DCFG_LPM_CAP;
4183                         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4184                 }
4185
4186                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4187                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
4188                 dwc3_gadget_dctl_write_safe(dwc, reg);
4189         }
4190
4191         dep = dwc->eps[0];
4192         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4193         if (ret) {
4194                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4195                 return;
4196         }
4197
4198         dep = dwc->eps[1];
4199         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4200         if (ret) {
4201                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4202                 return;
4203         }
4204
4205         /*
4206          * Configure PHY via GUSB3PIPECTLn if required.
4207          *
4208          * Update GTXFIFOSIZn
4209          *
4210          * In both cases reset values should be sufficient.
4211          */
4212 }
4213
4214 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc, unsigned int evtinfo)
4215 {
4216         dwc->suspended = false;
4217
4218         /*
4219          * TODO take core out of low power mode when that's
4220          * implemented.
4221          */
4222
4223         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
4224                 spin_unlock(&dwc->lock);
4225                 dwc->gadget_driver->resume(dwc->gadget);
4226                 spin_lock(&dwc->lock);
4227         }
4228
4229         dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
4230 }
4231
4232 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
4233                 unsigned int evtinfo)
4234 {
4235         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
4236         unsigned int            pwropt;
4237
4238         /*
4239          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
4240          * Hibernation mode enabled which would show up when device detects
4241          * host-initiated U3 exit.
4242          *
4243          * In that case, device will generate a Link State Change Interrupt
4244          * from U3 to RESUME which is only necessary if Hibernation is
4245          * configured in.
4246          *
4247          * There are no functional changes due to such spurious event and we
4248          * just need to ignore it.
4249          *
4250          * Refers to:
4251          *
4252          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
4253          * operational mode
4254          */
4255         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
4256         if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
4257                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
4258                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
4259                                 (next == DWC3_LINK_STATE_RESUME)) {
4260                         return;
4261                 }
4262         }
4263
4264         /*
4265          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
4266          * on the link partner, the USB session might do multiple entry/exit
4267          * of low power states before a transfer takes place.
4268          *
4269          * Due to this problem, we might experience lower throughput. The
4270          * suggested workaround is to disable DCTL[12:9] bits if we're
4271          * transitioning from U1/U2 to U0 and enable those bits again
4272          * after a transfer completes and there are no pending transfers
4273          * on any of the enabled endpoints.
4274          *
4275          * This is the first half of that workaround.
4276          *
4277          * Refers to:
4278          *
4279          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
4280          * core send LGO_Ux entering U0
4281          */
4282         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
4283                 if (next == DWC3_LINK_STATE_U0) {
4284                         u32     u1u2;
4285                         u32     reg;
4286
4287                         switch (dwc->link_state) {
4288                         case DWC3_LINK_STATE_U1:
4289                         case DWC3_LINK_STATE_U2:
4290                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4291                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
4292                                                 | DWC3_DCTL_ACCEPTU2ENA
4293                                                 | DWC3_DCTL_INITU1ENA
4294                                                 | DWC3_DCTL_ACCEPTU1ENA);
4295
4296                                 if (!dwc->u1u2)
4297                                         dwc->u1u2 = reg & u1u2;
4298
4299                                 reg &= ~u1u2;
4300
4301                                 dwc3_gadget_dctl_write_safe(dwc, reg);
4302                                 break;
4303                         default:
4304                                 /* do nothing */
4305                                 break;
4306                         }
4307                 }
4308         }
4309
4310         switch (next) {
4311         case DWC3_LINK_STATE_U0:
4312                 if (dwc->gadget->wakeup_armed) {
4313                         dwc3_gadget_enable_linksts_evts(dwc, false);
4314                         dwc3_resume_gadget(dwc);
4315                         dwc->suspended = false;
4316                 }
4317                 break;
4318         case DWC3_LINK_STATE_U1:
4319                 if (dwc->speed == USB_SPEED_SUPER)
4320                         dwc3_suspend_gadget(dwc);
4321                 break;
4322         case DWC3_LINK_STATE_U2:
4323         case DWC3_LINK_STATE_U3:
4324                 dwc3_suspend_gadget(dwc);
4325                 break;
4326         case DWC3_LINK_STATE_RESUME:
4327                 dwc3_resume_gadget(dwc);
4328                 break;
4329         default:
4330                 /* do nothing */
4331                 break;
4332         }
4333
4334         dwc->link_state = next;
4335 }
4336
4337 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4338                                           unsigned int evtinfo)
4339 {
4340         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4341
4342         if (!dwc->suspended && next == DWC3_LINK_STATE_U3) {
4343                 dwc->suspended = true;
4344                 dwc3_suspend_gadget(dwc);
4345         }
4346
4347         dwc->link_state = next;
4348 }
4349
4350 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4351                 const struct dwc3_event_devt *event)
4352 {
4353         switch (event->type) {
4354         case DWC3_DEVICE_EVENT_DISCONNECT:
4355                 dwc3_gadget_disconnect_interrupt(dwc);
4356                 break;
4357         case DWC3_DEVICE_EVENT_RESET:
4358                 dwc3_gadget_reset_interrupt(dwc);
4359                 break;
4360         case DWC3_DEVICE_EVENT_CONNECT_DONE:
4361                 dwc3_gadget_conndone_interrupt(dwc);
4362                 break;
4363         case DWC3_DEVICE_EVENT_WAKEUP:
4364                 dwc3_gadget_wakeup_interrupt(dwc, event->event_info);
4365                 break;
4366         case DWC3_DEVICE_EVENT_HIBER_REQ:
4367                 dev_WARN_ONCE(dwc->dev, true, "unexpected hibernation event\n");
4368                 break;
4369         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4370                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4371                 break;
4372         case DWC3_DEVICE_EVENT_SUSPEND:
4373                 /* It changed to be suspend event for version 2.30a and above */
4374                 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
4375                         dwc3_gadget_suspend_interrupt(dwc, event->event_info);
4376                 break;
4377         case DWC3_DEVICE_EVENT_SOF:
4378         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4379         case DWC3_DEVICE_EVENT_CMD_CMPL:
4380         case DWC3_DEVICE_EVENT_OVERFLOW:
4381                 break;
4382         default:
4383                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4384         }
4385 }
4386
4387 static void dwc3_process_event_entry(struct dwc3 *dwc,
4388                 const union dwc3_event *event)
4389 {
4390         trace_dwc3_event(event->raw, dwc);
4391
4392         if (!event->type.is_devspec)
4393                 dwc3_endpoint_interrupt(dwc, &event->depevt);
4394         else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4395                 dwc3_gadget_interrupt(dwc, &event->devt);
4396         else
4397                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4398 }
4399
4400 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4401 {
4402         struct dwc3 *dwc = evt->dwc;
4403         irqreturn_t ret = IRQ_NONE;
4404         int left;
4405
4406         left = evt->count;
4407
4408         if (!(evt->flags & DWC3_EVENT_PENDING))
4409                 return IRQ_NONE;
4410
4411         while (left > 0) {
4412                 union dwc3_event event;
4413
4414                 event.raw = *(u32 *) (evt->cache + evt->lpos);
4415
4416                 dwc3_process_event_entry(dwc, &event);
4417
4418                 /*
4419                  * FIXME we wrap around correctly to the next entry as
4420                  * almost all entries are 4 bytes in size. There is one
4421                  * entry which has 12 bytes which is a regular entry
4422                  * followed by 8 bytes data. ATM I don't know how
4423                  * things are organized if we get next to the a
4424                  * boundary so I worry about that once we try to handle
4425                  * that.
4426                  */
4427                 evt->lpos = (evt->lpos + 4) % evt->length;
4428                 left -= 4;
4429         }
4430
4431         evt->count = 0;
4432         ret = IRQ_HANDLED;
4433
4434         /* Unmask interrupt */
4435         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4436                     DWC3_GEVNTSIZ_SIZE(evt->length));
4437
4438         if (dwc->imod_interval) {
4439                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4440                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4441         }
4442
4443         /* Keep the clearing of DWC3_EVENT_PENDING at the end */
4444         evt->flags &= ~DWC3_EVENT_PENDING;
4445
4446         return ret;
4447 }
4448
4449 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4450 {
4451         struct dwc3_event_buffer *evt = _evt;
4452         struct dwc3 *dwc = evt->dwc;
4453         unsigned long flags;
4454         irqreturn_t ret = IRQ_NONE;
4455
4456         local_bh_disable();
4457         spin_lock_irqsave(&dwc->lock, flags);
4458         ret = dwc3_process_event_buf(evt);
4459         spin_unlock_irqrestore(&dwc->lock, flags);
4460         local_bh_enable();
4461
4462         return ret;
4463 }
4464
4465 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4466 {
4467         struct dwc3 *dwc = evt->dwc;
4468         u32 amount;
4469         u32 count;
4470
4471         if (pm_runtime_suspended(dwc->dev)) {
4472                 dwc->pending_events = true;
4473                 /*
4474                  * Trigger runtime resume. The get() function will be balanced
4475                  * after processing the pending events in dwc3_process_pending
4476                  * events().
4477                  */
4478                 pm_runtime_get(dwc->dev);
4479                 disable_irq_nosync(dwc->irq_gadget);
4480                 return IRQ_HANDLED;
4481         }
4482
4483         /*
4484          * With PCIe legacy interrupt, test shows that top-half irq handler can
4485          * be called again after HW interrupt deassertion. Check if bottom-half
4486          * irq event handler completes before caching new event to prevent
4487          * losing events.
4488          */
4489         if (evt->flags & DWC3_EVENT_PENDING)
4490                 return IRQ_HANDLED;
4491
4492         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4493         count &= DWC3_GEVNTCOUNT_MASK;
4494         if (!count)
4495                 return IRQ_NONE;
4496
4497         evt->count = count;
4498         evt->flags |= DWC3_EVENT_PENDING;
4499
4500         /* Mask interrupt */
4501         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4502                     DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4503
4504         amount = min(count, evt->length - evt->lpos);
4505         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4506
4507         if (amount < count)
4508                 memcpy(evt->cache, evt->buf, count - amount);
4509
4510         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4511
4512         return IRQ_WAKE_THREAD;
4513 }
4514
4515 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4516 {
4517         struct dwc3_event_buffer        *evt = _evt;
4518
4519         return dwc3_check_event_buf(evt);
4520 }
4521
4522 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4523 {
4524         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4525         int irq;
4526
4527         irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4528         if (irq > 0)
4529                 goto out;
4530
4531         if (irq == -EPROBE_DEFER)
4532                 goto out;
4533
4534         irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4535         if (irq > 0)
4536                 goto out;
4537
4538         if (irq == -EPROBE_DEFER)
4539                 goto out;
4540
4541         irq = platform_get_irq(dwc3_pdev, 0);
4542
4543 out:
4544         return irq;
4545 }
4546
4547 static void dwc_gadget_release(struct device *dev)
4548 {
4549         struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4550
4551         kfree(gadget);
4552 }
4553
4554 /**
4555  * dwc3_gadget_init - initializes gadget related registers
4556  * @dwc: pointer to our controller context structure
4557  *
4558  * Returns 0 on success otherwise negative errno.
4559  */
4560 int dwc3_gadget_init(struct dwc3 *dwc)
4561 {
4562         int ret;
4563         int irq;
4564         struct device *dev;
4565
4566         irq = dwc3_gadget_get_irq(dwc);
4567         if (irq < 0) {
4568                 ret = irq;
4569                 goto err0;
4570         }
4571
4572         dwc->irq_gadget = irq;
4573
4574         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4575                                           sizeof(*dwc->ep0_trb) * 2,
4576                                           &dwc->ep0_trb_addr, GFP_KERNEL);
4577         if (!dwc->ep0_trb) {
4578                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4579                 ret = -ENOMEM;
4580                 goto err0;
4581         }
4582
4583         dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4584         if (!dwc->setup_buf) {
4585                 ret = -ENOMEM;
4586                 goto err1;
4587         }
4588
4589         dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4590                         &dwc->bounce_addr, GFP_KERNEL);
4591         if (!dwc->bounce) {
4592                 ret = -ENOMEM;
4593                 goto err2;
4594         }
4595
4596         init_completion(&dwc->ep0_in_setup);
4597         dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4598         if (!dwc->gadget) {
4599                 ret = -ENOMEM;
4600                 goto err3;
4601         }
4602
4603
4604         usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4605         dev                             = &dwc->gadget->dev;
4606         dev->platform_data              = dwc;
4607         dwc->gadget->ops                = &dwc3_gadget_ops;
4608         dwc->gadget->speed              = USB_SPEED_UNKNOWN;
4609         dwc->gadget->ssp_rate           = USB_SSP_GEN_UNKNOWN;
4610         dwc->gadget->sg_supported       = true;
4611         dwc->gadget->name               = "dwc3-gadget";
4612         dwc->gadget->lpm_capable        = !dwc->usb2_gadget_lpm_disable;
4613         dwc->gadget->wakeup_capable     = true;
4614
4615         /*
4616          * FIXME We might be setting max_speed to <SUPER, however versions
4617          * <2.20a of dwc3 have an issue with metastability (documented
4618          * elsewhere in this driver) which tells us we can't set max speed to
4619          * anything lower than SUPER.
4620          *
4621          * Because gadget.max_speed is only used by composite.c and function
4622          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4623          * to happen so we avoid sending SuperSpeed Capability descriptor
4624          * together with our BOS descriptor as that could confuse host into
4625          * thinking we can handle super speed.
4626          *
4627          * Note that, in fact, we won't even support GetBOS requests when speed
4628          * is less than super speed because we don't have means, yet, to tell
4629          * composite.c that we are USB 2.0 + LPM ECN.
4630          */
4631         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4632             !dwc->dis_metastability_quirk)
4633                 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4634                                 dwc->revision);
4635
4636         dwc->gadget->max_speed          = dwc->maximum_speed;
4637         dwc->gadget->max_ssp_rate       = dwc->max_ssp_rate;
4638
4639         /*
4640          * REVISIT: Here we should clear all pending IRQs to be
4641          * sure we're starting from a well known location.
4642          */
4643
4644         ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4645         if (ret)
4646                 goto err4;
4647
4648         ret = usb_add_gadget(dwc->gadget);
4649         if (ret) {
4650                 dev_err(dwc->dev, "failed to add gadget\n");
4651                 goto err5;
4652         }
4653
4654         if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4655                 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4656         else
4657                 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4658
4659         /* No system wakeup if no gadget driver bound */
4660         if (dwc->sys_wakeup)
4661                 device_wakeup_disable(dwc->sysdev);
4662
4663         return 0;
4664
4665 err5:
4666         dwc3_gadget_free_endpoints(dwc);
4667 err4:
4668         usb_put_gadget(dwc->gadget);
4669         dwc->gadget = NULL;
4670 err3:
4671         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4672                         dwc->bounce_addr);
4673
4674 err2:
4675         kfree(dwc->setup_buf);
4676
4677 err1:
4678         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4679                         dwc->ep0_trb, dwc->ep0_trb_addr);
4680
4681 err0:
4682         return ret;
4683 }
4684
4685 /* -------------------------------------------------------------------------- */
4686
4687 void dwc3_gadget_exit(struct dwc3 *dwc)
4688 {
4689         if (!dwc->gadget)
4690                 return;
4691
4692         dwc3_enable_susphy(dwc, false);
4693         usb_del_gadget(dwc->gadget);
4694         dwc3_gadget_free_endpoints(dwc);
4695         usb_put_gadget(dwc->gadget);
4696         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4697                           dwc->bounce_addr);
4698         kfree(dwc->setup_buf);
4699         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4700                           dwc->ep0_trb, dwc->ep0_trb_addr);
4701 }
4702
4703 int dwc3_gadget_suspend(struct dwc3 *dwc)
4704 {
4705         unsigned long flags;
4706         int ret;
4707
4708         ret = dwc3_gadget_soft_disconnect(dwc);
4709         if (ret)
4710                 goto err;
4711
4712         spin_lock_irqsave(&dwc->lock, flags);
4713         if (dwc->gadget_driver)
4714                 dwc3_disconnect_gadget(dwc);
4715         spin_unlock_irqrestore(&dwc->lock, flags);
4716
4717         return 0;
4718
4719 err:
4720         /*
4721          * Attempt to reset the controller's state. Likely no
4722          * communication can be established until the host
4723          * performs a port reset.
4724          */
4725         if (dwc->softconnect)
4726                 dwc3_gadget_soft_connect(dwc);
4727
4728         return ret;
4729 }
4730
4731 int dwc3_gadget_resume(struct dwc3 *dwc)
4732 {
4733         if (!dwc->gadget_driver || !dwc->softconnect)
4734                 return 0;
4735
4736         return dwc3_gadget_soft_connect(dwc);
4737 }
4738
4739 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4740 {
4741         if (dwc->pending_events) {
4742                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4743                 dwc3_thread_interrupt(dwc->irq_gadget, dwc->ev_buf);
4744                 pm_runtime_put(dwc->dev);
4745                 dwc->pending_events = false;
4746                 enable_irq(dwc->irq_gadget);
4747         }
4748 }