1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
5 * Copyright (C) 2014 GridPoint
6 * Author: Jon Ringle <jringle@gridpoint.com>
7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
10 #undef DEFAULT_SYMBOL_NAMESPACE
11 #define DEFAULT_SYMBOL_NAMESPACE SERIAL_NXP_SC16IS7XX
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/export.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/idr.h>
19 #include <linux/kthread.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/property.h>
23 #include <linux/regmap.h>
24 #include <linux/sched.h>
25 #include <linux/serial_core.h>
26 #include <linux/serial.h>
27 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/uaccess.h>
31 #include <linux/units.h>
33 #include "sc16is7xx.h"
35 #define SC16IS7XX_MAX_DEVS 8
37 /* SC16IS7XX register definitions */
38 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
39 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
40 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
41 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
42 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
43 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
44 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
45 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
46 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
47 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
48 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
49 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
50 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
53 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
56 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
59 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
62 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
64 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
65 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
66 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
68 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
69 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
70 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
72 /* Enhanced Register set: Only if (LCR == 0xBF) */
73 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
74 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
75 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
76 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
77 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
79 /* IER register bits */
80 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
81 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
83 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
85 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
88 /* IER register bits - write only if (EFR[4] == 1) */
89 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
90 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
91 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
92 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
94 /* FCR register bits */
95 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
96 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
97 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
98 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
99 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
101 /* FCR register bits - write only if (EFR[4] == 1) */
102 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
103 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
105 /* IIR register bits */
106 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
107 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
108 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
109 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
110 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
111 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
112 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
115 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
118 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
119 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
123 /* LCR register bits */
124 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
125 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
127 * Word length bits table:
133 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
135 * STOP length bit table:
137 * 1 -> 1-1.5 stop bits if
139 * 2 stop bits otherwise
141 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
142 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
143 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
144 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
145 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
146 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
147 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
148 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
149 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
150 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
152 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
155 /* MCR register bits */
156 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
159 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
160 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
161 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
162 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
166 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
170 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
175 /* LSR register bits */
176 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
177 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
178 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
179 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
180 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
181 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
182 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
183 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
184 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
186 /* MSR register bits */
187 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
188 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
192 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
196 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
200 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
201 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
204 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
207 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
210 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
214 * TCR trigger levels are available from 0 to 60 characters with a granularity
216 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
217 * no built-in hardware check to make sure this condition is met. Also, the TCR
218 * must be programmed with this condition before auto RTS or software flow
219 * control is enabled to avoid spurious operation of the device.
221 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
222 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
226 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
227 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
228 * trigger levels. Trigger levels from 4 characters to 60 characters are
229 * available with a granularity of four.
231 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the
232 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
233 * the trigger level defined in FCR is discarded. This applies to both transmit
234 * FIFO and receive FIFO trigger level setting.
236 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
237 * default state, that is, '00'.
239 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
240 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
242 /* IOControl register bits (Only 75x/76x) */
243 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
244 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */
245 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */
246 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
248 /* EFCR register bits */
249 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
251 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
252 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
253 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
254 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
255 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
256 * 0 = rate upto 115.2 kbit/s
258 * 1 = rate upto 1.152 Mbit/s
262 /* EFR register bits */
263 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
264 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
265 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
266 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
267 * and writing to IER[7:4],
270 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
271 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
273 * SWFLOW bits 3 & 2 table:
274 * 00 -> no transmitter flow
276 * 01 -> transmitter generates
278 * 10 -> transmitter generates
280 * 11 -> transmitter generates
281 * XON1, XON2, XOFF1 and
284 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
285 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
287 * SWFLOW bits 3 & 2 table:
288 * 00 -> no received flow
290 * 01 -> receiver compares
292 * 10 -> receiver compares
294 * 11 -> receiver compares
295 * XON1, XON2, XOFF1 and
298 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
299 SC16IS7XX_EFR_AUTOCTS_BIT | \
300 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
301 SC16IS7XX_EFR_SWFLOW3_BIT | \
302 SC16IS7XX_EFR_SWFLOW2_BIT | \
303 SC16IS7XX_EFR_SWFLOW1_BIT | \
304 SC16IS7XX_EFR_SWFLOW0_BIT)
307 /* Misc definitions */
308 #define SC16IS7XX_FIFO_SIZE (64)
309 #define SC16IS7XX_GPIOS_PER_BANK 4
311 #define SC16IS7XX_RECONF_MD (1 << 0)
312 #define SC16IS7XX_RECONF_IER (1 << 1)
313 #define SC16IS7XX_RECONF_RS485 (1 << 2)
315 struct sc16is7xx_one_config {
321 struct sc16is7xx_one {
322 struct uart_port port;
323 struct regmap *regmap;
324 struct mutex efr_lock; /* EFR registers access */
325 struct kthread_work tx_work;
326 struct kthread_work reg_work;
327 struct kthread_delayed_work ms_work;
328 struct sc16is7xx_one_config config;
329 unsigned int old_mctrl;
330 u8 old_lcr; /* Value before EFR access. */
334 struct sc16is7xx_port {
335 const struct sc16is7xx_devtype *devtype;
337 #ifdef CONFIG_GPIOLIB
338 struct gpio_chip gpio;
339 unsigned long gpio_valid_mask;
342 unsigned char buf[SC16IS7XX_FIFO_SIZE];
343 struct kthread_worker kworker;
344 struct task_struct *kworker_task;
345 struct sc16is7xx_one p[];
348 static DEFINE_IDA(sc16is7xx_lines);
350 static struct uart_driver sc16is7xx_uart = {
351 .owner = THIS_MODULE,
352 .driver_name = SC16IS7XX_NAME,
354 .nr = SC16IS7XX_MAX_DEVS,
357 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
359 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
361 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
362 unsigned int val = 0;
364 regmap_read(one->regmap, reg, &val);
369 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
371 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
373 regmap_write(one->regmap, reg, val);
376 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen)
378 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
380 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen);
383 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send)
385 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
388 * Don't send zero-length data, at least on SPI it confuses the chip
389 * delivering wrong TXLVL data.
391 if (unlikely(!to_send))
394 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send);
397 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
400 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
402 regmap_update_bits(one->regmap, reg, mask, val);
405 static void sc16is7xx_power(struct uart_port *port, int on)
407 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
408 SC16IS7XX_IER_SLEEP_BIT,
409 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
413 * In an amazing feat of design, the Enhanced Features Register (EFR)
414 * shares the address of the Interrupt Identification Register (IIR).
415 * Access to EFR is switched on by writing a magic value (0xbf) to the
416 * Line Control Register (LCR). Any interrupt firing during this time will
417 * see the EFR where it expects the IIR to be, leading to
418 * "Unexpected interrupt" messages.
420 * Prevent this possibility by claiming a mutex while accessing the EFR,
421 * and claiming the same mutex from within the interrupt handler. This is
422 * similar to disabling the interrupt, but that doesn't work because the
423 * bulk of the interrupt processing is run as a workqueue job in thread
426 static void sc16is7xx_efr_lock(struct uart_port *port)
428 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
430 mutex_lock(&one->efr_lock);
432 /* Backup content of LCR. */
433 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
435 /* Enable access to Enhanced register set */
436 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B);
438 /* Disable cache updates when writing to EFR registers */
439 regcache_cache_bypass(one->regmap, true);
442 static void sc16is7xx_efr_unlock(struct uart_port *port)
444 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
446 /* Re-enable cache updates when writing to normal registers */
447 regcache_cache_bypass(one->regmap, false);
449 /* Restore original content of LCR */
450 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr);
452 mutex_unlock(&one->efr_lock);
455 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
457 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
458 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
460 lockdep_assert_held_once(&port->lock);
462 one->config.flags |= SC16IS7XX_RECONF_IER;
463 one->config.ier_mask |= bit;
464 one->config.ier_val &= ~bit;
465 kthread_queue_work(&s->kworker, &one->reg_work);
468 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
470 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
471 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
473 lockdep_assert_held_once(&port->lock);
475 one->config.flags |= SC16IS7XX_RECONF_IER;
476 one->config.ier_mask |= bit;
477 one->config.ier_val |= bit;
478 kthread_queue_work(&s->kworker, &one->reg_work);
481 static void sc16is7xx_stop_tx(struct uart_port *port)
483 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
486 static void sc16is7xx_stop_rx(struct uart_port *port)
488 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
491 const struct sc16is7xx_devtype sc16is74x_devtype = {
496 EXPORT_SYMBOL_GPL(sc16is74x_devtype);
498 const struct sc16is7xx_devtype sc16is750_devtype = {
503 EXPORT_SYMBOL_GPL(sc16is750_devtype);
505 const struct sc16is7xx_devtype sc16is752_devtype = {
510 EXPORT_SYMBOL_GPL(sc16is752_devtype);
512 const struct sc16is7xx_devtype sc16is760_devtype = {
517 EXPORT_SYMBOL_GPL(sc16is760_devtype);
519 const struct sc16is7xx_devtype sc16is762_devtype = {
524 EXPORT_SYMBOL_GPL(sc16is762_devtype);
526 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
529 case SC16IS7XX_RHR_REG:
530 case SC16IS7XX_IIR_REG:
531 case SC16IS7XX_LSR_REG:
532 case SC16IS7XX_MSR_REG:
533 case SC16IS7XX_TXLVL_REG:
534 case SC16IS7XX_RXLVL_REG:
535 case SC16IS7XX_IOSTATE_REG:
536 case SC16IS7XX_IOCONTROL_REG:
543 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
546 case SC16IS7XX_RHR_REG:
553 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
555 return reg == SC16IS7XX_RHR_REG;
559 * Configure programmable baud rate generator (divisor) according to the
562 * From the datasheet, the divisor is computed according to:
564 * XTAL1 input frequency
565 * -----------------------
567 * divisor = ---------------------------
568 * baud-rate x sampling-rate
570 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
572 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
574 unsigned int prescaler = 1;
575 unsigned long clk = port->uartclk, div = clk / 16 / baud;
577 if (div >= BIT(16)) {
582 /* Enable enhanced features */
583 sc16is7xx_efr_lock(port);
584 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
585 SC16IS7XX_EFR_ENABLE_BIT,
586 SC16IS7XX_EFR_ENABLE_BIT);
587 sc16is7xx_efr_unlock(port);
589 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */
590 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
591 SC16IS7XX_MCR_CLKSEL_BIT,
592 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
594 /* Backup LCR and access special register set (DLL/DLH) */
595 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
596 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
597 SC16IS7XX_LCR_CONF_MODE_A);
599 /* Write the new divisor */
600 regcache_cache_bypass(one->regmap, true);
601 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
602 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
603 regcache_cache_bypass(one->regmap, false);
605 /* Restore LCR and access to general register set */
606 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
608 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
611 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
614 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
615 unsigned int lsr = 0, bytes_read, i;
616 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
619 if (unlikely(rxlen >= sizeof(s->buf))) {
620 dev_warn_ratelimited(port->dev,
621 "ttySC%i: Possible RX FIFO overrun: %d\n",
623 port->icount.buf_overrun++;
624 /* Ensure sanity of RX level */
625 rxlen = sizeof(s->buf);
629 /* Only read lsr if there are possible errors in FIFO */
631 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
632 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
633 read_lsr = false; /* No errors left in FIFO */
638 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
641 sc16is7xx_fifo_read(port, s->buf, rxlen);
645 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
651 if (lsr & SC16IS7XX_LSR_BI_BIT) {
653 if (uart_handle_break(port))
655 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
656 port->icount.parity++;
657 else if (lsr & SC16IS7XX_LSR_FE_BIT)
658 port->icount.frame++;
659 else if (lsr & SC16IS7XX_LSR_OE_BIT)
660 port->icount.overrun++;
662 lsr &= port->read_status_mask;
663 if (lsr & SC16IS7XX_LSR_BI_BIT)
665 else if (lsr & SC16IS7XX_LSR_PE_BIT)
667 else if (lsr & SC16IS7XX_LSR_FE_BIT)
669 else if (lsr & SC16IS7XX_LSR_OE_BIT)
673 for (i = 0; i < bytes_read; ++i) {
675 if (uart_handle_sysrq_char(port, ch))
678 if (lsr & port->ignore_status_mask)
681 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
687 tty_flip_buffer_push(&port->state->port);
690 static void sc16is7xx_handle_tx(struct uart_port *port)
692 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
693 struct tty_port *tport = &port->state->port;
697 if (unlikely(port->x_char)) {
698 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
704 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
705 uart_port_lock_irqsave(port, &flags);
706 sc16is7xx_stop_tx(port);
707 uart_port_unlock_irqrestore(port, flags);
711 /* Limit to space available in TX FIFO */
712 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
713 if (txlen > SC16IS7XX_FIFO_SIZE) {
714 dev_err_ratelimited(port->dev,
715 "chip reports %d free bytes in TX fifo, but it only has %d",
716 txlen, SC16IS7XX_FIFO_SIZE);
720 txlen = uart_fifo_out(port, s->buf, txlen);
721 sc16is7xx_fifo_write(port, s->buf, txlen);
723 uart_port_lock_irqsave(port, &flags);
724 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
725 uart_write_wakeup(port);
727 if (kfifo_is_empty(&tport->xmit_fifo))
728 sc16is7xx_stop_tx(port);
730 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
731 uart_port_unlock_irqrestore(port, flags);
734 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
736 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
737 unsigned int mctrl = 0;
739 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
740 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
741 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;
742 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;
746 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
748 struct uart_port *port = &one->port;
750 unsigned int status, changed;
752 lockdep_assert_held_once(&one->efr_lock);
754 status = sc16is7xx_get_hwmctrl(port);
755 changed = status ^ one->old_mctrl;
760 one->old_mctrl = status;
762 uart_port_lock_irqsave(port, &flags);
763 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
765 if (changed & TIOCM_DSR)
767 if (changed & TIOCM_CAR)
768 uart_handle_dcd_change(port, status & TIOCM_CAR);
769 if (changed & TIOCM_CTS)
770 uart_handle_cts_change(port, status & TIOCM_CTS);
772 wake_up_interruptible(&port->state->port.delta_msr_wait);
773 uart_port_unlock_irqrestore(port, flags);
776 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
779 unsigned int iir, rxlen;
780 struct uart_port *port = &s->p[portno].port;
781 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
783 mutex_lock(&one->efr_lock);
785 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
786 if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
791 iir &= SC16IS7XX_IIR_ID_MASK;
794 case SC16IS7XX_IIR_RDI_SRC:
795 case SC16IS7XX_IIR_RLSE_SRC:
796 case SC16IS7XX_IIR_RTOI_SRC:
797 case SC16IS7XX_IIR_XOFFI_SRC:
798 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
801 * There is a silicon bug that makes the chip report a
802 * time-out interrupt but no data in the FIFO. This is
803 * described in errata section 18.1.4.
805 * When this happens, read one byte from the FIFO to
806 * clear the interrupt.
808 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
812 sc16is7xx_handle_rx(port, rxlen, iir);
814 /* CTSRTS interrupt comes only when CTS goes inactive */
815 case SC16IS7XX_IIR_CTSRTS_SRC:
816 case SC16IS7XX_IIR_MSI_SRC:
817 sc16is7xx_update_mlines(one);
819 case SC16IS7XX_IIR_THRI_SRC:
820 sc16is7xx_handle_tx(port);
823 dev_err_ratelimited(port->dev,
824 "ttySC%i: Unexpected interrupt: %x",
830 mutex_unlock(&one->efr_lock);
835 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
839 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
844 keep_polling = false;
846 for (i = 0; i < s->devtype->nr_uart; ++i)
847 keep_polling |= sc16is7xx_port_irq(s, i);
848 } while (keep_polling);
853 static void sc16is7xx_tx_proc(struct kthread_work *ws)
855 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
856 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
858 if ((port->rs485.flags & SER_RS485_ENABLED) &&
859 (port->rs485.delay_rts_before_send > 0))
860 msleep(port->rs485.delay_rts_before_send);
862 mutex_lock(&one->efr_lock);
863 sc16is7xx_handle_tx(port);
864 mutex_unlock(&one->efr_lock);
867 static void sc16is7xx_reconf_rs485(struct uart_port *port)
869 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
870 SC16IS7XX_EFCR_RTS_INVERT_BIT;
872 struct serial_rs485 *rs485 = &port->rs485;
873 unsigned long irqflags;
875 uart_port_lock_irqsave(port, &irqflags);
876 if (rs485->flags & SER_RS485_ENABLED) {
877 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
879 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
880 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
882 uart_port_unlock_irqrestore(port, irqflags);
884 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
887 static void sc16is7xx_reg_proc(struct kthread_work *ws)
889 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
890 struct sc16is7xx_one_config config;
891 unsigned long irqflags;
893 uart_port_lock_irqsave(&one->port, &irqflags);
894 config = one->config;
895 memset(&one->config, 0, sizeof(one->config));
896 uart_port_unlock_irqrestore(&one->port, irqflags);
898 if (config.flags & SC16IS7XX_RECONF_MD) {
901 /* Device ignores RTS setting when hardware flow is enabled */
902 if (one->port.mctrl & TIOCM_RTS)
903 mcr |= SC16IS7XX_MCR_RTS_BIT;
905 if (one->port.mctrl & TIOCM_DTR)
906 mcr |= SC16IS7XX_MCR_DTR_BIT;
908 if (one->port.mctrl & TIOCM_LOOP)
909 mcr |= SC16IS7XX_MCR_LOOP_BIT;
910 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
911 SC16IS7XX_MCR_RTS_BIT |
912 SC16IS7XX_MCR_DTR_BIT |
913 SC16IS7XX_MCR_LOOP_BIT,
917 if (config.flags & SC16IS7XX_RECONF_IER)
918 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
919 config.ier_mask, config.ier_val);
921 if (config.flags & SC16IS7XX_RECONF_RS485)
922 sc16is7xx_reconf_rs485(&one->port);
925 static void sc16is7xx_ms_proc(struct kthread_work *ws)
927 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
928 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
930 if (one->port.state) {
931 mutex_lock(&one->efr_lock);
932 sc16is7xx_update_mlines(one);
933 mutex_unlock(&one->efr_lock);
935 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
939 static void sc16is7xx_enable_ms(struct uart_port *port)
941 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
942 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
944 lockdep_assert_held_once(&port->lock);
946 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
949 static void sc16is7xx_start_tx(struct uart_port *port)
951 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
952 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
954 kthread_queue_work(&s->kworker, &one->tx_work);
957 static void sc16is7xx_throttle(struct uart_port *port)
962 * Hardware flow control is enabled and thus the device ignores RTS
963 * value set in MCR register. Stop reading data from RX FIFO so the
964 * AutoRTS feature will de-activate RTS output.
966 uart_port_lock_irqsave(port, &flags);
967 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
968 uart_port_unlock_irqrestore(port, flags);
971 static void sc16is7xx_unthrottle(struct uart_port *port)
975 uart_port_lock_irqsave(port, &flags);
976 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
977 uart_port_unlock_irqrestore(port, flags);
980 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
984 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
986 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
989 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
991 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
993 /* Called with port lock taken so we can only return cached value */
994 return one->old_mctrl;
997 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
999 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1000 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1002 one->config.flags |= SC16IS7XX_RECONF_MD;
1003 kthread_queue_work(&s->kworker, &one->reg_work);
1006 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1008 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1009 SC16IS7XX_LCR_TXBREAK_BIT,
1010 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1013 static void sc16is7xx_set_termios(struct uart_port *port,
1014 struct ktermios *termios,
1015 const struct ktermios *old)
1017 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1018 unsigned int lcr, flow = 0;
1020 unsigned long flags;
1022 kthread_cancel_delayed_work_sync(&one->ms_work);
1024 /* Mask termios capabilities we don't support */
1025 termios->c_cflag &= ~CMSPAR;
1028 switch (termios->c_cflag & CSIZE) {
1030 lcr = SC16IS7XX_LCR_WORD_LEN_5;
1033 lcr = SC16IS7XX_LCR_WORD_LEN_6;
1036 lcr = SC16IS7XX_LCR_WORD_LEN_7;
1039 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1042 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1043 termios->c_cflag &= ~CSIZE;
1044 termios->c_cflag |= CS8;
1049 if (termios->c_cflag & PARENB) {
1050 lcr |= SC16IS7XX_LCR_PARITY_BIT;
1051 if (!(termios->c_cflag & PARODD))
1052 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1056 if (termios->c_cflag & CSTOPB)
1057 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1059 /* Set read status mask */
1060 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1061 if (termios->c_iflag & INPCK)
1062 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1063 SC16IS7XX_LSR_FE_BIT;
1064 if (termios->c_iflag & (BRKINT | PARMRK))
1065 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1067 /* Set status ignore mask */
1068 port->ignore_status_mask = 0;
1069 if (termios->c_iflag & IGNBRK)
1070 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1071 if (!(termios->c_cflag & CREAD))
1072 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1074 /* Configure flow control */
1075 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1076 if (termios->c_cflag & CRTSCTS) {
1077 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1078 SC16IS7XX_EFR_AUTORTS_BIT;
1079 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1081 if (termios->c_iflag & IXON)
1082 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1083 if (termios->c_iflag & IXOFF)
1084 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1086 /* Update LCR register */
1087 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1089 /* Update EFR registers */
1090 sc16is7xx_efr_lock(port);
1091 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1092 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1093 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1094 SC16IS7XX_EFR_FLOWCTRL_BITS, flow);
1095 sc16is7xx_efr_unlock(port);
1097 /* Get baud rate generator configuration */
1098 baud = uart_get_baud_rate(port, termios, old,
1099 port->uartclk / 16 / 4 / 0xffff,
1100 port->uartclk / 16);
1102 /* Setup baudrate generator */
1103 baud = sc16is7xx_set_baud(port, baud);
1105 uart_port_lock_irqsave(port, &flags);
1107 /* Update timeout according to new baud rate */
1108 uart_update_timeout(port, termios->c_cflag, baud);
1110 if (UART_ENABLE_MS(port, termios->c_cflag))
1111 sc16is7xx_enable_ms(port);
1113 uart_port_unlock_irqrestore(port, flags);
1116 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1117 struct serial_rs485 *rs485)
1119 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1120 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1122 if (rs485->flags & SER_RS485_ENABLED) {
1124 * RTS signal is handled by HW, it's timing can't be influenced.
1125 * However, it's sometimes useful to delay TX even without RTS
1126 * control therefore we try to handle .delay_rts_before_send.
1128 if (rs485->delay_rts_after_send)
1132 one->config.flags |= SC16IS7XX_RECONF_RS485;
1133 kthread_queue_work(&s->kworker, &one->reg_work);
1138 static int sc16is7xx_startup(struct uart_port *port)
1140 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1142 unsigned long flags;
1144 sc16is7xx_power(port, 1);
1147 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1148 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1150 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1151 SC16IS7XX_FCR_FIFO_BIT);
1154 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1155 SC16IS7XX_LCR_CONF_MODE_B);
1157 regcache_cache_bypass(one->regmap, true);
1159 /* Enable write access to enhanced features and internal clock div */
1160 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1161 SC16IS7XX_EFR_ENABLE_BIT,
1162 SC16IS7XX_EFR_ENABLE_BIT);
1164 /* Enable TCR/TLR */
1165 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1166 SC16IS7XX_MCR_TCRTLR_BIT,
1167 SC16IS7XX_MCR_TCRTLR_BIT);
1169 /* Configure flow control levels */
1170 /* Flow control halt level 48, resume level 24 */
1171 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1172 SC16IS7XX_TCR_RX_RESUME(24) |
1173 SC16IS7XX_TCR_RX_HALT(48));
1175 regcache_cache_bypass(one->regmap, false);
1177 /* Now, initialize the UART */
1178 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1180 /* Enable IrDA mode if requested in DT */
1181 /* This bit must be written with LCR[7] = 0 */
1182 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1183 SC16IS7XX_MCR_IRDA_BIT,
1185 SC16IS7XX_MCR_IRDA_BIT : 0);
1187 /* Enable the Rx and Tx FIFO */
1188 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1189 SC16IS7XX_EFCR_RXDISABLE_BIT |
1190 SC16IS7XX_EFCR_TXDISABLE_BIT,
1193 /* Enable RX, CTS change and modem lines interrupts */
1194 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1195 SC16IS7XX_IER_MSI_BIT;
1196 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1198 /* Enable modem status polling */
1199 uart_port_lock_irqsave(port, &flags);
1200 sc16is7xx_enable_ms(port);
1201 uart_port_unlock_irqrestore(port, flags);
1206 static void sc16is7xx_shutdown(struct uart_port *port)
1208 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1209 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1211 kthread_cancel_delayed_work_sync(&one->ms_work);
1213 /* Disable all interrupts */
1214 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1216 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1217 SC16IS7XX_EFCR_RXDISABLE_BIT |
1218 SC16IS7XX_EFCR_TXDISABLE_BIT,
1219 SC16IS7XX_EFCR_RXDISABLE_BIT |
1220 SC16IS7XX_EFCR_TXDISABLE_BIT);
1222 sc16is7xx_power(port, 0);
1224 kthread_flush_worker(&s->kworker);
1227 static const char *sc16is7xx_type(struct uart_port *port)
1229 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1231 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1234 static int sc16is7xx_request_port(struct uart_port *port)
1240 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1242 if (flags & UART_CONFIG_TYPE)
1243 port->type = PORT_SC16IS7XX;
1246 static int sc16is7xx_verify_port(struct uart_port *port,
1247 struct serial_struct *s)
1249 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1251 if (s->irq != port->irq)
1257 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1258 unsigned int oldstate)
1260 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1263 static void sc16is7xx_null_void(struct uart_port *port)
1268 static const struct uart_ops sc16is7xx_ops = {
1269 .tx_empty = sc16is7xx_tx_empty,
1270 .set_mctrl = sc16is7xx_set_mctrl,
1271 .get_mctrl = sc16is7xx_get_mctrl,
1272 .stop_tx = sc16is7xx_stop_tx,
1273 .start_tx = sc16is7xx_start_tx,
1274 .throttle = sc16is7xx_throttle,
1275 .unthrottle = sc16is7xx_unthrottle,
1276 .stop_rx = sc16is7xx_stop_rx,
1277 .enable_ms = sc16is7xx_enable_ms,
1278 .break_ctl = sc16is7xx_break_ctl,
1279 .startup = sc16is7xx_startup,
1280 .shutdown = sc16is7xx_shutdown,
1281 .set_termios = sc16is7xx_set_termios,
1282 .type = sc16is7xx_type,
1283 .request_port = sc16is7xx_request_port,
1284 .release_port = sc16is7xx_null_void,
1285 .config_port = sc16is7xx_config_port,
1286 .verify_port = sc16is7xx_verify_port,
1290 #ifdef CONFIG_GPIOLIB
1291 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1294 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1295 struct uart_port *port = &s->p[0].port;
1297 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1299 return !!(val & BIT(offset));
1302 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1304 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1305 struct uart_port *port = &s->p[0].port;
1307 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1308 val ? BIT(offset) : 0);
1311 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1314 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1315 struct uart_port *port = &s->p[0].port;
1317 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1322 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1323 unsigned offset, int val)
1325 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1326 struct uart_port *port = &s->p[0].port;
1327 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1330 state |= BIT(offset);
1332 state &= ~BIT(offset);
1335 * If we write IOSTATE first, and then IODIR, the output value is not
1336 * transferred to the corresponding I/O pin.
1337 * The datasheet states that each register bit will be transferred to
1338 * the corresponding I/O pin programmed as output when writing to
1339 * IOSTATE. Therefore, configure direction first with IODIR, and then
1340 * set value after with IOSTATE.
1342 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1344 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1349 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
1350 unsigned long *valid_mask,
1351 unsigned int ngpios)
1353 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1355 *valid_mask = s->gpio_valid_mask;
1360 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
1362 struct device *dev = s->p[0].port.dev;
1364 if (!s->devtype->nr_gpio)
1367 switch (s->mctrl_mask) {
1369 s->gpio_valid_mask = GENMASK(7, 0);
1371 case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
1372 s->gpio_valid_mask = GENMASK(3, 0);
1374 case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
1375 s->gpio_valid_mask = GENMASK(7, 4);
1381 if (s->gpio_valid_mask == 0)
1384 s->gpio.owner = THIS_MODULE;
1385 s->gpio.parent = dev;
1386 s->gpio.label = dev_name(dev);
1387 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask;
1388 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1389 s->gpio.get = sc16is7xx_gpio_get;
1390 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1391 s->gpio.set = sc16is7xx_gpio_set;
1393 s->gpio.ngpio = s->devtype->nr_gpio;
1394 s->gpio.can_sleep = 1;
1396 return gpiochip_add_data(&s->gpio, s);
1400 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s)
1405 u32 irda_port[SC16IS7XX_MAX_PORTS];
1406 struct device *dev = s->p[0].port.dev;
1408 count = device_property_count_u32(dev, "irda-mode-ports");
1409 if (count < 0 || count > ARRAY_SIZE(irda_port))
1412 ret = device_property_read_u32_array(dev, "irda-mode-ports",
1417 for (i = 0; i < count; i++) {
1418 if (irda_port[i] < s->devtype->nr_uart)
1419 s->p[irda_port[i]].irda_mode = true;
1424 * Configure ports designated to operate as modem control lines.
1426 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
1427 struct regmap *regmap)
1432 u32 mctrl_port[SC16IS7XX_MAX_PORTS];
1433 struct device *dev = s->p[0].port.dev;
1435 count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
1436 if (count < 0 || count > ARRAY_SIZE(mctrl_port))
1439 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
1446 for (i = 0; i < count; i++) {
1447 /* Use GPIO lines as modem control lines */
1448 if (mctrl_port[i] == 0)
1449 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
1450 else if (mctrl_port[i] == 1)
1451 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
1457 SC16IS7XX_IOCONTROL_REG,
1458 SC16IS7XX_IOCONTROL_MODEM_A_BIT |
1459 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);
1464 static const struct serial_rs485 sc16is7xx_rs485_supported = {
1465 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND,
1466 .delay_rts_before_send = 1,
1467 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */
1470 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype,
1471 struct regmap *regmaps[], int irq)
1473 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1477 struct sc16is7xx_port *s;
1478 bool port_registered[SC16IS7XX_MAX_PORTS];
1480 for (i = 0; i < devtype->nr_uart; i++)
1481 if (IS_ERR(regmaps[i]))
1482 return PTR_ERR(regmaps[i]);
1485 * This device does not have an identification register that would
1486 * tell us if we are really connected to the correct device.
1487 * The best we can do is to check if communication is at all possible.
1489 * Note: regmap[0] is used in the probe function to access registers
1490 * common to all channels/ports, as it is guaranteed to be present on
1493 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
1495 return -EPROBE_DEFER;
1497 /* Alloc port structure */
1498 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1500 dev_err(dev, "Error allocating port structure\n");
1504 /* Always ask for fixed clock rate from a property. */
1505 device_property_read_u32(dev, "clock-frequency", &uartclk);
1507 s->clk = devm_clk_get_optional(dev, NULL);
1509 return PTR_ERR(s->clk);
1511 ret = clk_prepare_enable(s->clk);
1515 freq = clk_get_rate(s->clk);
1522 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1527 s->devtype = devtype;
1528 dev_set_drvdata(dev, s);
1530 kthread_init_worker(&s->kworker);
1531 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1533 if (IS_ERR(s->kworker_task)) {
1534 ret = PTR_ERR(s->kworker_task);
1537 sched_set_fifo(s->kworker_task);
1539 /* reset device, purging any pending irq / data */
1540 regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG,
1541 SC16IS7XX_IOCONTROL_SRESET_BIT);
1543 /* Mark each port line and status as uninitialised. */
1544 for (i = 0; i < devtype->nr_uart; ++i) {
1545 s->p[i].port.line = SC16IS7XX_MAX_DEVS;
1546 port_registered[i] = false;
1549 for (i = 0; i < devtype->nr_uart; ++i) {
1550 ret = ida_alloc_max(&sc16is7xx_lines,
1551 SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL);
1555 s->p[i].port.line = ret;
1557 /* Initialize port data */
1558 s->p[i].port.dev = dev;
1559 s->p[i].port.irq = irq;
1560 s->p[i].port.type = PORT_SC16IS7XX;
1561 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1562 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1563 s->p[i].port.iobase = i;
1565 * Use all ones as membase to make sure uart_configure_port() in
1566 * serial_core.c does not abort for SPI/I2C devices where the
1567 * membase address is not applicable.
1569 s->p[i].port.membase = (void __iomem *)~0;
1570 s->p[i].port.iotype = UPIO_PORT;
1571 s->p[i].port.uartclk = freq;
1572 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1573 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
1574 s->p[i].port.ops = &sc16is7xx_ops;
1575 s->p[i].old_mctrl = 0;
1576 s->p[i].regmap = regmaps[i];
1578 mutex_init(&s->p[i].efr_lock);
1580 ret = uart_get_rs485_mode(&s->p[i].port);
1584 /* Disable all interrupts */
1585 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1587 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1588 SC16IS7XX_EFCR_RXDISABLE_BIT |
1589 SC16IS7XX_EFCR_TXDISABLE_BIT);
1591 /* Initialize kthread work structs */
1592 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1593 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1594 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1597 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1601 port_registered[i] = true;
1604 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1605 SC16IS7XX_LCR_CONF_MODE_B);
1607 regcache_cache_bypass(regmaps[i], true);
1609 /* Enable write access to enhanced features */
1610 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1611 SC16IS7XX_EFR_ENABLE_BIT);
1613 regcache_cache_bypass(regmaps[i], false);
1615 /* Restore access to general registers */
1616 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1618 /* Go to suspend mode */
1619 sc16is7xx_power(&s->p[i].port, 0);
1622 sc16is7xx_setup_irda_ports(s);
1624 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
1628 #ifdef CONFIG_GPIOLIB
1629 ret = sc16is7xx_setup_gpio_chip(s);
1635 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1636 * If that succeeds, we can allow sharing the interrupt as well.
1637 * In case the interrupt controller doesn't support that, we fall
1638 * back to a non-shared falling-edge trigger.
1640 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1641 IRQF_TRIGGER_LOW | IRQF_SHARED |
1647 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1648 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1653 #ifdef CONFIG_GPIOLIB
1654 if (s->gpio_valid_mask)
1655 gpiochip_remove(&s->gpio);
1659 for (i = 0; i < devtype->nr_uart; i++) {
1660 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS)
1661 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1662 if (port_registered[i])
1663 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1666 kthread_stop(s->kworker_task);
1669 clk_disable_unprepare(s->clk);
1673 EXPORT_SYMBOL_GPL(sc16is7xx_probe);
1675 void sc16is7xx_remove(struct device *dev)
1677 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1680 #ifdef CONFIG_GPIOLIB
1681 if (s->gpio_valid_mask)
1682 gpiochip_remove(&s->gpio);
1685 for (i = 0; i < s->devtype->nr_uart; i++) {
1686 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1687 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1688 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1689 sc16is7xx_power(&s->p[i].port, 0);
1692 kthread_flush_worker(&s->kworker);
1693 kthread_stop(s->kworker_task);
1695 clk_disable_unprepare(s->clk);
1697 EXPORT_SYMBOL_GPL(sc16is7xx_remove);
1699 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1700 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1701 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1702 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1703 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1704 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1705 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1708 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids);
1709 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1711 const struct regmap_config sc16is7xx_regcfg = {
1715 .cache_type = REGCACHE_MAPLE,
1716 .volatile_reg = sc16is7xx_regmap_volatile,
1717 .precious_reg = sc16is7xx_regmap_precious,
1718 .writeable_noinc_reg = sc16is7xx_regmap_noinc,
1719 .readable_noinc_reg = sc16is7xx_regmap_noinc,
1720 .max_raw_read = SC16IS7XX_FIFO_SIZE,
1721 .max_raw_write = SC16IS7XX_FIFO_SIZE,
1722 .max_register = SC16IS7XX_EFCR_REG,
1724 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg);
1726 const char *sc16is7xx_regmap_name(u8 port_id)
1729 case 0: return "port0";
1730 case 1: return "port1";
1736 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name);
1738 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
1740 /* CH1,CH0 are at bits 2:1. */
1741 return port_id << 1;
1743 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask);
1745 static int __init sc16is7xx_init(void)
1747 return uart_register_driver(&sc16is7xx_uart);
1749 module_init(sc16is7xx_init);
1751 static void __exit sc16is7xx_exit(void)
1753 uart_unregister_driver(&sc16is7xx_uart);
1755 module_exit(sc16is7xx_exit);
1757 MODULE_LICENSE("GPL");
1758 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1759 MODULE_DESCRIPTION("SC16IS7xx tty serial core driver");