drivers/staging/wilc1000/wilc_spi.c

   1 /* ////////////////////////////////////////////////////////////////////////// */
   2 /*  */
   3 /* Copyright (c) Atmel Corporation.  All rights reserved. */
   4 /*  */
   5 /* Module Name:  wilc_spi.c */
   6 /*  */
   7 /*  */
   8 /* //////////////////////////////////////////////////////////////////////////// */
   9
  10 #include "wilc_wlan_if.h"
  11 #include "wilc_wlan.h"
  12
  13 extern unsigned int int_clrd;
  14
  15 /*
  16  * #include <linux/kernel.h>
  17  * #include <linux/string.h>
  18  */
  19 typedef struct {
  20         void *os_context;
  21         int (*spi_tx)(uint8_t *, uint32_t);
  22         int (*spi_rx)(uint8_t *, uint32_t);
  23         int (*spi_trx)(uint8_t *, uint8_t *, uint32_t);
  24         int (*spi_max_speed)(void);
  25         wilc_debug_func dPrint;
  26         int crc_off;
  27         int nint;
  28         int has_thrpt_enh;
  29 } wilc_spi_t;
  30
  31 static wilc_spi_t g_spi;
  32
  33 static int spi_read(uint32_t, uint8_t *, uint32_t);
  34 static int spi_write(uint32_t, uint8_t *, uint32_t);
  35
  36 /********************************************
  37  *
  38  *      Crc7
  39  *
  40  ********************************************/
  41
  42 static const uint8_t crc7_syndrome_table[256] = {
  43         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  44         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  45         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  46         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  47         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  48         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  49         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  50         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  51         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  52         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  53         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  54         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  55         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  56         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  57         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  58         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  59         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  60         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  61         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  62         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  63         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  64         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  65         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  66         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  67         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  68         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  69         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  70         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  71         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  72         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  73         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  74         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  75 };
  76
  77 static uint8_t crc7_byte(uint8_t crc, uint8_t data)
  78 {
  79         return crc7_syndrome_table[(crc << 1) ^ data];
  80 }
  81
  82 static uint8_t crc7(uint8_t crc, const uint8_t *buffer, uint32_t len)
  83 {
  84         while (len--)
  85                 crc = crc7_byte(crc, *buffer++);
  86         return crc;
  87 }
  88
  89 /********************************************
  90  *
  91  *      Spi protocol Function
  92  *
  93  ********************************************/
  94
  95 #define CMD_DMA_WRITE                           0xc1
  96 #define CMD_DMA_READ                            0xc2
  97 #define CMD_INTERNAL_WRITE              0xc3
  98 #define CMD_INTERNAL_READ               0xc4
  99 #define CMD_TERMINATE                           0xc5
 100 #define CMD_REPEAT                                      0xc6
 101 #define CMD_DMA_EXT_WRITE               0xc7
 102 #define CMD_DMA_EXT_READ                0xc8
 103 #define CMD_SINGLE_WRITE                        0xc9
 104 #define CMD_SINGLE_READ                 0xca
 105 #define CMD_RESET                                               0xcf
 106
 107 #define N_OK                                                            1
 108 #define N_FAIL                                                          0
 109 #define N_RESET                                                 -1
 110 #define N_RETRY                                                 -2
 111
 112 #define DATA_PKT_SZ_256                         256
 113 #define DATA_PKT_SZ_512                 512
 114 #define DATA_PKT_SZ_1K                          1024
 115 #define DATA_PKT_SZ_4K                          (4 * 1024)
 116 #define DATA_PKT_SZ_8K                          (8 * 1024)
 117 #define DATA_PKT_SZ                                     DATA_PKT_SZ_8K
 118
 119 static int spi_cmd(uint8_t cmd, uint32_t adr, uint32_t data, uint32_t sz, uint8_t clockless)
 120 {
 121         uint8_t bc[9];
 122         int len = 5;
 123         int result = N_OK;
 124
 125         bc[0] = cmd;
 126         switch (cmd) {
 127         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 128                 bc[1] = (uint8_t)(adr >> 16);
 129                 bc[2] = (uint8_t)(adr >> 8);
 130                 bc[3] = (uint8_t)adr;
 131                 len = 5;
 132                 break;
 133
 134         case CMD_INTERNAL_READ:                 /* internal register read */
 135                 bc[1] = (uint8_t)(adr >> 8);
 136                 if (clockless)
 137                         bc[1] |= (1 << 7);
 138                 bc[2] = (uint8_t)adr;
 139                 bc[3] = 0x00;
 140                 len = 5;
 141                 break;
 142
 143         case CMD_TERMINATE:                                     /* termination */
 144                 bc[1] = 0x00;
 145                 bc[2] = 0x00;
 146                 bc[3] = 0x00;
 147                 len = 5;
 148                 break;
 149
 150         case CMD_REPEAT:                                                /* repeat */
 151                 bc[1] = 0x00;
 152                 bc[2] = 0x00;
 153                 bc[3] = 0x00;
 154                 len = 5;
 155                 break;
 156
 157         case CMD_RESET:                                                 /* reset */
 158                 bc[1] = 0xff;
 159                 bc[2] = 0xff;
 160                 bc[3] = 0xff;
 161                 len = 5;
 162                 break;
 163
 164         case CMD_DMA_WRITE:                                     /* dma write */
 165         case CMD_DMA_READ:                                      /* dma read */
 166                 bc[1] = (uint8_t)(adr >> 16);
 167                 bc[2] = (uint8_t)(adr >> 8);
 168                 bc[3] = (uint8_t)adr;
 169                 bc[4] = (uint8_t)(sz >> 8);
 170                 bc[5] = (uint8_t)(sz);
 171                 len = 7;
 172                 break;
 173
 174         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 175         case CMD_DMA_EXT_READ:                  /* dma extended read */
 176                 bc[1] = (uint8_t)(adr >> 16);
 177                 bc[2] = (uint8_t)(adr >> 8);
 178                 bc[3] = (uint8_t)adr;
 179                 bc[4] = (uint8_t)(sz >> 16);
 180                 bc[5] = (uint8_t)(sz >> 8);
 181                 bc[6] = (uint8_t)(sz);
 182                 len = 8;
 183                 break;
 184
 185         case CMD_INTERNAL_WRITE:                /* internal register write */
 186                 bc[1] = (uint8_t)(adr >> 8);
 187                 if (clockless)
 188                         bc[1] |= (1 << 7);
 189                 bc[2] = (uint8_t)(adr);
 190                 bc[3] = (uint8_t)(data >> 24);
 191                 bc[4] = (uint8_t)(data >> 16);
 192                 bc[5] = (uint8_t)(data >> 8);
 193                 bc[6] = (uint8_t)(data);
 194                 len = 8;
 195                 break;
 196
 197         case CMD_SINGLE_WRITE:                  /* single word write */
 198                 bc[1] = (uint8_t)(adr >> 16);
 199                 bc[2] = (uint8_t)(adr >> 8);
 200                 bc[3] = (uint8_t)(adr);
 201                 bc[4] = (uint8_t)(data >> 24);
 202                 bc[5] = (uint8_t)(data >> 16);
 203                 bc[6] = (uint8_t)(data >> 8);
 204                 bc[7] = (uint8_t)(data);
 205                 len = 9;
 206                 break;
 207
 208         default:
 209                 result = N_FAIL;
 210                 break;
 211         }
 212
 213         if (result) {
 214                 if (!g_spi.crc_off)
 215                         bc[len - 1] = (crc7(0x7f, (const uint8_t *)&bc[0], len - 1)) << 1;
 216                 else
 217                         len -= 1;
 218
 219                 if (!g_spi.spi_tx(bc, len)) {
 220                         PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
 221                         result = N_FAIL;
 222                 }
 223         }
 224
 225         return result;
 226 }
 227
 228 static int spi_cmd_rsp(uint8_t cmd)
 229 {
 230         uint8_t rsp;
 231         int result = N_OK;
 232
 233         /**
 234          *      Command/Control response
 235          **/
 236         if ((cmd == CMD_RESET) ||
 237             (cmd == CMD_TERMINATE) ||
 238             (cmd == CMD_REPEAT)) {
 239                 if (!g_spi.spi_rx(&rsp, 1)) {
 240                         result = N_FAIL;
 241                         goto _fail_;
 242                 }
 243         }
 244
 245         if (!g_spi.spi_rx(&rsp, 1)) {
 246                 PRINT_ER("[wilc spi]: Failed cmd response read, bus error...\n");
 247                 result = N_FAIL;
 248                 goto _fail_;
 249         }
 250
 251         if (rsp != cmd) {
 252                 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x), resp (%02x)\n", cmd, rsp);
 253                 result = N_FAIL;
 254                 goto _fail_;
 255         }
 256
 257         /**
 258          *      State response
 259          **/
 260         if (!g_spi.spi_rx(&rsp, 1)) {
 261                 PRINT_ER("[wilc spi]: Failed cmd state read, bus error...\n");
 262                 result = N_FAIL;
 263                 goto _fail_;
 264         }
 265
 266         if (rsp != 0x00) {
 267                 PRINT_ER("[wilc spi]: Failed cmd state response state (%02x)\n", rsp);
 268                 result = N_FAIL;
 269         }
 270
 271 _fail_:
 272
 273         return result;
 274 }
 275
 276 static int spi_cmd_complete(uint8_t cmd, uint32_t adr, uint8_t *b, uint32_t sz, uint8_t clockless)
 277 {
 278         uint8_t wb[32], rb[32];
 279         uint8_t wix, rix;
 280         uint32_t len2;
 281         uint8_t rsp;
 282         int len = 0;
 283         int result = N_OK;
 284
 285         wb[0] = cmd;
 286         switch (cmd) {
 287         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 288                 wb[1] = (uint8_t)(adr >> 16);
 289                 wb[2] = (uint8_t)(adr >> 8);
 290                 wb[3] = (uint8_t)adr;
 291                 len = 5;
 292                 break;
 293
 294         case CMD_INTERNAL_READ:                 /* internal register read */
 295                 wb[1] = (uint8_t)(adr >> 8);
 296                 if (clockless == 1)
 297                         wb[1] |= (1 << 7);
 298                 wb[2] = (uint8_t)adr;
 299                 wb[3] = 0x00;
 300                 len = 5;
 301                 break;
 302
 303         case CMD_TERMINATE:                                     /* termination */
 304                 wb[1] = 0x00;
 305                 wb[2] = 0x00;
 306                 wb[3] = 0x00;
 307                 len = 5;
 308                 break;
 309
 310         case CMD_REPEAT:                                                /* repeat */
 311                 wb[1] = 0x00;
 312                 wb[2] = 0x00;
 313                 wb[3] = 0x00;
 314                 len = 5;
 315                 break;
 316
 317         case CMD_RESET:                                                 /* reset */
 318                 wb[1] = 0xff;
 319                 wb[2] = 0xff;
 320                 wb[3] = 0xff;
 321                 len = 5;
 322                 break;
 323
 324         case CMD_DMA_WRITE:                                     /* dma write */
 325         case CMD_DMA_READ:                                      /* dma read */
 326                 wb[1] = (uint8_t)(adr >> 16);
 327                 wb[2] = (uint8_t)(adr >> 8);
 328                 wb[3] = (uint8_t)adr;
 329                 wb[4] = (uint8_t)(sz >> 8);
 330                 wb[5] = (uint8_t)(sz);
 331                 len = 7;
 332                 break;
 333
 334         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 335         case CMD_DMA_EXT_READ:                  /* dma extended read */
 336                 wb[1] = (uint8_t)(adr >> 16);
 337                 wb[2] = (uint8_t)(adr >> 8);
 338                 wb[3] = (uint8_t)adr;
 339                 wb[4] = (uint8_t)(sz >> 16);
 340                 wb[5] = (uint8_t)(sz >> 8);
 341                 wb[6] = (uint8_t)(sz);
 342                 len = 8;
 343                 break;
 344
 345         case CMD_INTERNAL_WRITE:                /* internal register write */
 346                 wb[1] = (uint8_t)(adr >> 8);
 347                 if (clockless == 1)
 348                         wb[1] |= (1 << 7);
 349                 wb[2] = (uint8_t)(adr);
 350                 wb[3] = b[3];
 351                 wb[4] = b[2];
 352                 wb[5] = b[1];
 353                 wb[6] = b[0];
 354                 len = 8;
 355                 break;
 356
 357         case CMD_SINGLE_WRITE:                  /* single word write */
 358                 wb[1] = (uint8_t)(adr >> 16);
 359                 wb[2] = (uint8_t)(adr >> 8);
 360                 wb[3] = (uint8_t)(adr);
 361                 wb[4] = b[3];
 362                 wb[5] = b[2];
 363                 wb[6] = b[1];
 364                 wb[7] = b[0];
 365                 len = 9;
 366                 break;
 367
 368         default:
 369                 result = N_FAIL;
 370                 break;
 371         }
 372
 373         if (result != N_OK) {
 374                 return result;
 375         }
 376
 377         if (!g_spi.crc_off)
 378                 wb[len - 1] = (crc7(0x7f, (const uint8_t *)&wb[0], len - 1)) << 1;
 379         else
 380                 len -= 1;
 381
 382 #define NUM_SKIP_BYTES (1)
 383 #define NUM_RSP_BYTES (2)
 384 #define NUM_DATA_HDR_BYTES (1)
 385 #define NUM_DATA_BYTES (4)
 386 #define NUM_CRC_BYTES (2)
 387 #define NUM_DUMMY_BYTES (3)
 388         if ((cmd == CMD_RESET) ||
 389             (cmd == CMD_TERMINATE) ||
 390             (cmd == CMD_REPEAT)) {
 391                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 392         } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 393                 if (!g_spi.crc_off) {
 394                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 395                                       + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
 396                 } else {
 397                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 398                                       + NUM_DUMMY_BYTES);
 399                 }
 400         } else {
 401                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 402         }
 403 #undef NUM_DUMMY_BYTES
 404
 405         if (len2 > (sizeof(wb) / sizeof(wb[0]))) {
 406                 PRINT_ER("[wilc spi]: spi buffer size too small (%d) (%zu)\n",
 407                          len2, (sizeof(wb) / sizeof(wb[0])));
 408                 result = N_FAIL;
 409                 return result;
 410         }
 411         /* zero spi write buffers. */
 412         for (wix = len; wix < len2; wix++) {
 413                 wb[wix] = 0;
 414         }
 415         rix = len;
 416
 417         if (!g_spi.spi_trx(wb, rb, len2)) {
 418                 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
 419                 result = N_FAIL;
 420                 return result;
 421         }
 422
 423         /**
 424          * Command/Control response
 425          **/
 426         if ((cmd == CMD_RESET) ||
 427             (cmd == CMD_TERMINATE) ||
 428             (cmd == CMD_REPEAT)) {
 429                 rix++;         /* skip 1 byte */
 430         }
 431
 432         /* do { */
 433         rsp = rb[rix++];
 434         /*      if(rsp == cmd) break; */
 435         /* } while(&rptr[1] <= &rb[len2]); */
 436
 437         if (rsp != cmd) {
 438                 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x)"
 439                          ", resp (%02x)\n", cmd, rsp);
 440                 result = N_FAIL;
 441                 return result;
 442         }
 443
 444         /**
 445          * State response
 446          **/
 447         rsp = rb[rix++];
 448         if (rsp != 0x00) {
 449                 PRINT_ER("[wilc spi]: Failed cmd state response "
 450                          "state (%02x)\n", rsp);
 451                 result = N_FAIL;
 452                 return result;
 453         }
 454
 455         if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
 456             || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 457                 int retry;
 458                 /* uint16_t crc1, crc2; */
 459                 uint8_t crc[2];
 460                 /**
 461                  * Data Respnose header
 462                  **/
 463                 retry = 100;
 464                 do {
 465                         /* ensure there is room in buffer later to read data and crc */
 466                         if (rix < len2) {
 467                                 rsp = rb[rix++];
 468                         } else {
 469                                 retry = 0;
 470                                 break;
 471                         }
 472                         if (((rsp >> 4) & 0xf) == 0xf)
 473                                 break;
 474                 } while (retry--);
 475
 476                 if (retry <= 0) {
 477                         PRINT_ER("[wilc spi]: Error, data read "
 478                                  "response (%02x)\n", rsp);
 479                         result = N_RESET;
 480                         return result;
 481                 }
 482
 483                 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 484                         /**
 485                          * Read bytes
 486                          **/
 487                         if ((rix + 3) < len2) {
 488                                 b[0] = rb[rix++];
 489                                 b[1] = rb[rix++];
 490                                 b[2] = rb[rix++];
 491                                 b[3] = rb[rix++];
 492                         } else {
 493                                 PRINT_ER("[wilc spi]: buffer overrun when reading data.\n");
 494                                 result = N_FAIL;
 495                                 return result;
 496                         }
 497
 498                         if (!g_spi.crc_off) {
 499                                 /**
 500                                  * Read Crc
 501                                  **/
 502                                 if ((rix + 1) < len2) {
 503                                         crc[0] = rb[rix++];
 504                                         crc[1] = rb[rix++];
 505                                 } else {
 506                                         PRINT_ER("[wilc spi]: buffer overrun when reading crc.\n");
 507                                         result = N_FAIL;
 508                                         return result;
 509                                 }
 510                         }
 511                 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 512                         int ix;
 513
 514                         /* some data may be read in response to dummy bytes. */
 515                         for (ix = 0; (rix < len2) && (ix < sz); ) {
 516                                 b[ix++] = rb[rix++];
 517                         }
 518
 519                         sz -= ix;
 520
 521                         if (sz > 0) {
 522                                 int nbytes;
 523
 524                                 if (sz <= (DATA_PKT_SZ - ix))
 525                                         nbytes = sz;
 526                                 else
 527                                         nbytes = DATA_PKT_SZ - ix;
 528
 529                                 /**
 530                                  * Read bytes
 531                                  **/
 532                                 if (!g_spi.spi_rx(&b[ix], nbytes)) {
 533                                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 534                                         result = N_FAIL;
 535                                         goto _error_;
 536                                 }
 537
 538                                 /**
 539                                  * Read Crc
 540                                  **/
 541                                 if (!g_spi.crc_off) {
 542                                         if (!g_spi.spi_rx(crc, 2)) {
 543                                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 544                                                 result = N_FAIL;
 545                                                 goto _error_;
 546                                         }
 547                                 }
 548
 549
 550                                 ix += nbytes;
 551                                 sz -= nbytes;
 552                         }
 553
 554                         /*  if any data in left unread, then read the rest using normal DMA code.*/
 555                         while (sz > 0) {
 556                                 int nbytes;
 557
 558                                 if (sz <= DATA_PKT_SZ)
 559                                         nbytes = sz;
 560                                 else
 561                                         nbytes = DATA_PKT_SZ;
 562
 563                                 /**
 564                                  * read data response only on the next DMA cycles not
 565                                  * the first DMA since data response header is already
 566                                  * handled above for the first DMA.
 567                                  **/
 568                                 /**
 569                                  * Data Respnose header
 570                                  **/
 571                                 retry = 10;
 572                                 do {
 573                                         if (!g_spi.spi_rx(&rsp, 1)) {
 574                                                 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
 575                                                 result = N_FAIL;
 576                                                 break;
 577                                         }
 578                                         if (((rsp >> 4) & 0xf) == 0xf)
 579                                                 break;
 580                                 } while (retry--);
 581
 582                                 if (result == N_FAIL)
 583                                         break;
 584
 585
 586                                 /**
 587                                  * Read bytes
 588                                  **/
 589                                 if (!g_spi.spi_rx(&b[ix], nbytes)) {
 590                                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 591                                         result = N_FAIL;
 592                                         break;
 593                                 }
 594
 595                                 /**
 596                                  * Read Crc
 597                                  **/
 598                                 if (!g_spi.crc_off) {
 599                                         if (!g_spi.spi_rx(crc, 2)) {
 600                                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 601                                                 result = N_FAIL;
 602                                                 break;
 603                                         }
 604                                 }
 605
 606                                 ix += nbytes;
 607                                 sz -= nbytes;
 608                         }
 609                 }
 610         }
 611 _error_:
 612         return result;
 613 }
 614
 615 static int spi_data_read(uint8_t *b, uint32_t sz)
 616 {
 617         int retry, ix, nbytes;
 618         int result = N_OK;
 619         uint8_t crc[2];
 620         uint8_t rsp;
 621
 622         /**
 623          *      Data
 624          **/
 625         ix = 0;
 626         do {
 627                 if (sz <= DATA_PKT_SZ)
 628                         nbytes = sz;
 629                 else
 630                         nbytes = DATA_PKT_SZ;
 631
 632                 /**
 633                  *      Data Respnose header
 634                  **/
 635                 retry = 10;
 636                 do {
 637                         if (!g_spi.spi_rx(&rsp, 1)) {
 638                                 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
 639                                 result = N_FAIL;
 640                                 break;
 641                         }
 642                         if (((rsp >> 4) & 0xf) == 0xf)
 643                                 break;
 644                 } while (retry--);
 645
 646                 if (result == N_FAIL)
 647                         break;
 648
 649                 if (retry <= 0) {
 650                         PRINT_ER("[wilc spi]: Failed data response read...(%02x)\n", rsp);
 651                         result = N_FAIL;
 652                         break;
 653                 }
 654
 655                 /**
 656                  *      Read bytes
 657                  **/
 658                 if (!g_spi.spi_rx(&b[ix], nbytes)) {
 659                         PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
 660                         result = N_FAIL;
 661                         break;
 662                 }
 663
 664                 /**
 665                  *      Read Crc
 666                  **/
 667                 if (!g_spi.crc_off) {
 668                         if (!g_spi.spi_rx(crc, 2)) {
 669                                 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
 670                                 result = N_FAIL;
 671                                 break;
 672                         }
 673                 }
 674
 675                 ix += nbytes;
 676                 sz -= nbytes;
 677
 678         } while (sz);
 679
 680         return result;
 681 }
 682
 683 static int spi_data_write(uint8_t *b, uint32_t sz)
 684 {
 685         int ix, nbytes;
 686         int result = 1;
 687         uint8_t cmd, order, crc[2] = {0};
 688         /* uint8_t rsp; */
 689
 690         /**
 691          *      Data
 692          **/
 693         ix = 0;
 694         do {
 695                 if (sz <= DATA_PKT_SZ)
 696                         nbytes = sz;
 697                 else
 698                         nbytes = DATA_PKT_SZ;
 699
 700                 /**
 701                  *      Write command
 702                  **/
 703                 cmd = 0xf0;
 704                 if (ix == 0) {
 705                         if (sz <= DATA_PKT_SZ)
 706
 707                                 order = 0x3;
 708                         else
 709                                 order = 0x1;
 710                 } else {
 711                         if (sz <= DATA_PKT_SZ)
 712                                 order = 0x3;
 713                         else
 714                                 order = 0x2;
 715                 }
 716                 cmd |= order;
 717                 if (!g_spi.spi_tx(&cmd, 1)) {
 718                         PRINT_ER("[wilc spi]: Failed data block cmd write, bus error...\n");
 719                         result = N_FAIL;
 720                         break;
 721                 }
 722
 723                 /**
 724                  *      Write data
 725                  **/
 726                 if (!g_spi.spi_tx(&b[ix], nbytes)) {
 727                         PRINT_ER("[wilc spi]: Failed data block write, bus error...\n");
 728                         result = N_FAIL;
 729                         break;
 730                 }
 731
 732                 /**
 733                  *      Write Crc
 734                  **/
 735                 if (!g_spi.crc_off) {
 736                         if (!g_spi.spi_tx(crc, 2)) {
 737                                 PRINT_ER("[wilc spi]: Failed data block crc write, bus error...\n");
 738                                 result = N_FAIL;
 739                                 break;
 740                         }
 741                 }
 742
 743                 /**
 744                  *      No need to wait for response
 745                  **/
 746                 ix += nbytes;
 747                 sz -= nbytes;
 748         } while (sz);
 749
 750
 751         return result;
 752 }
 753
 754 /********************************************
 755  *
 756  *      Spi Internal Read/Write Function
 757  *
 758  ********************************************/
 759
 760 static int spi_internal_write(uint32_t adr, uint32_t dat)
 761 {
 762         int result;
 763
 764 #if defined USE_OLD_SPI_SW
 765         /**
 766          *      Command
 767          **/
 768         result = spi_cmd(CMD_INTERNAL_WRITE, adr, dat, 4, 0);
 769         if (result != N_OK) {
 770                 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
 771                 return 0;
 772         }
 773
 774         result = spi_cmd_rsp(CMD_INTERNAL_WRITE, 0);
 775         if (result != N_OK) {
 776                 PRINT_ER("[wilc spi]: Failed internal write cmd response...\n");
 777         }
 778 #else
 779
 780 #ifdef BIG_ENDIAN
 781         dat = BYTE_SWAP(dat);
 782 #endif
 783         result = spi_cmd_complete(CMD_INTERNAL_WRITE, adr, (uint8_t *)&dat, 4, 0);
 784         if (result != N_OK) {
 785                 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
 786         }
 787
 788 #endif
 789         return result;
 790 }
 791
 792 static int spi_internal_read(uint32_t adr, uint32_t *data)
 793 {
 794         int result;
 795
 796 #if defined USE_OLD_SPI_SW
 797         result = spi_cmd(CMD_INTERNAL_READ, adr, 0, 4, 0);
 798         if (result != N_OK) {
 799                 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
 800                 return 0;
 801         }
 802
 803         result = spi_cmd_rsp(CMD_INTERNAL_READ, 0);
 804         if (result != N_OK) {
 805                 PRINT_ER("[wilc spi]: Failed internal read cmd response...\n");
 806                 return 0;
 807         }
 808
 809         /**
 810          *      Data
 811          **/
 812         result = spi_data_read((uint8_t *)data, 4);
 813         if (result != N_OK) {
 814                 PRINT_ER("[wilc spi]: Failed internal read data...\n");
 815                 return 0;
 816         }
 817 #else
 818         result = spi_cmd_complete(CMD_INTERNAL_READ, adr, (uint8_t *)data, 4, 0);
 819         if (result != N_OK) {
 820                 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
 821                 return 0;
 822         }
 823 #endif
 824
 825
 826 #ifdef BIG_ENDIAN
 827         *data = BYTE_SWAP(*data);
 828 #endif
 829
 830         return 1;
 831 }
 832
 833 /********************************************
 834  *
 835  *      Spi interfaces
 836  *
 837  ********************************************/
 838
 839 static int spi_write_reg(uint32_t addr, uint32_t data)
 840 {
 841         int result = N_OK;
 842         uint8_t cmd = CMD_SINGLE_WRITE;
 843         uint8_t clockless = 0;
 844
 845
 846 #if defined USE_OLD_SPI_SW
 847         {
 848                 result = spi_cmd(cmd, addr, data, 4, 0);
 849                 if (result != N_OK) {
 850                         PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
 851                         return 0;
 852                 }
 853
 854                 result = spi_cmd_rsp(cmd, 0);
 855                 if (result != N_OK) {
 856                         PRINT_ER("[wilc spi]: Failed cmd response, write reg (%08x)...\n", addr);
 857                         return 0;
 858                 }
 859
 860                 return 1;
 861         }
 862 #else
 863 #ifdef BIG_ENDIAN
 864         data = BYTE_SWAP(data);
 865 #endif
 866         if (addr < 0x30) {
 867                 /* Clockless register*/
 868                 cmd = CMD_INTERNAL_WRITE;
 869                 clockless = 1;
 870         }
 871
 872         result = spi_cmd_complete(cmd, addr, (uint8_t *)&data, 4, clockless);
 873         if (result != N_OK) {
 874                 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
 875         }
 876
 877         return result;
 878 #endif
 879
 880 }
 881
 882 static int spi_write(uint32_t addr, uint8_t *buf, uint32_t size)
 883 {
 884         int result;
 885         uint8_t cmd = CMD_DMA_EXT_WRITE;
 886
 887         /**
 888          *      has to be greated than 4
 889          **/
 890         if (size <= 4)
 891                 return 0;
 892
 893 #if defined USE_OLD_SPI_SW
 894         /**
 895          *      Command
 896          **/
 897         result = spi_cmd(cmd, addr, 0, size, 0);
 898         if (result != N_OK) {
 899                 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
 900                 return 0;
 901         }
 902
 903         result = spi_cmd_rsp(cmd, 0);
 904         if (result != N_OK) {
 905                 PRINT_ER("[wilc spi ]: Failed cmd response, write block (%08x)...\n", addr);
 906                 return 0;
 907         }
 908 #else
 909         result = spi_cmd_complete(cmd, addr, NULL, size, 0);
 910         if (result != N_OK) {
 911                 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
 912                 return 0;
 913         }
 914 #endif
 915
 916         /**
 917          *      Data
 918          **/
 919         result = spi_data_write(buf, size);
 920         if (result != N_OK) {
 921                 PRINT_ER("[wilc spi]: Failed block data write...\n");
 922         }
 923
 924         return 1;
 925 }
 926
 927 static int spi_read_reg(uint32_t addr, uint32_t *data)
 928 {
 929         int result = N_OK;
 930         uint8_t cmd = CMD_SINGLE_READ;
 931         uint8_t clockless = 0;
 932
 933 #if defined USE_OLD_SPI_SW
 934         result = spi_cmd(cmd, addr, 0, 4, 0);
 935         if (result != N_OK) {
 936                 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
 937                 return 0;
 938         }
 939         result = spi_cmd_rsp(cmd, 0);
 940         if (result != N_OK) {
 941                 PRINT_ER("[wilc spi]: Failed cmd response, read reg (%08x)...\n", addr);
 942                 return 0;
 943         }
 944
 945         result = spi_data_read((uint8_t *)data, 4);
 946         if (result != N_OK) {
 947                 PRINT_ER("[wilc spi]: Failed data read...\n");
 948                 return 0;
 949         }
 950 #else
 951         if (addr < 0x30) {
 952                 /* PRINT_ER("***** read addr %d\n\n", addr); */
 953                 /* Clockless register*/
 954                 cmd = CMD_INTERNAL_READ;
 955                 clockless = 1;
 956         }
 957
 958         result = spi_cmd_complete(cmd, addr, (uint8_t *)data, 4, clockless);
 959         if (result != N_OK) {
 960                 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
 961                 return 0;
 962         }
 963 #endif
 964
 965
 966 #ifdef BIG_ENDIAN
 967         *data = BYTE_SWAP(*data);
 968 #endif
 969
 970         return 1;
 971 }
 972
 973 static int spi_read(uint32_t addr, uint8_t *buf, uint32_t size)
 974 {
 975         uint8_t cmd = CMD_DMA_EXT_READ;
 976         int result;
 977
 978         if (size <= 4)
 979                 return 0;
 980
 981 #if defined USE_OLD_SPI_SW
 982         /**
 983          *      Command
 984          **/
 985         result = spi_cmd(cmd, addr, 0, size, 0);
 986         if (result != N_OK) {
 987                 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
 988                 return 0;
 989         }
 990
 991         result = spi_cmd_rsp(cmd, 0);
 992         if (result != N_OK) {
 993                 PRINT_ER("[wilc spi]: Failed cmd response, read block (%08x)...\n", addr);
 994                 return 0;
 995         }
 996
 997         /**
 998          *      Data
 999          **/
1000         result = spi_data_read(buf, size);
1001         if (result != N_OK) {
1002                 PRINT_ER("[wilc spi]: Failed block data read...\n");
1003                 return 0;
1004         }
1005 #else
1006         result = spi_cmd_complete(cmd, addr, buf, size, 0);
1007         if (result != N_OK) {
1008                 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
1009                 return 0;
1010         }
1011 #endif
1012
1013
1014         return 1;
1015 }
1016
1017 /********************************************
1018  *
1019  *      Bus interfaces
1020  *
1021  ********************************************/
1022
1023 static int spi_clear_int(void)
1024 {
1025         uint32_t reg;
1026         if (!spi_read_reg(WILC_HOST_RX_CTRL_0, &reg)) {
1027                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_HOST_RX_CTRL_0);
1028                 return 0;
1029         }
1030         reg &= ~0x1;
1031         spi_write_reg(WILC_HOST_RX_CTRL_0, reg);
1032         int_clrd++;
1033         return 1;
1034 }
1035
1036 static int spi_deinit(void *pv)
1037 {
1038         /**
1039          *      TODO:
1040          **/
1041         return 1;
1042 }
1043
1044 static int spi_sync(void)
1045 {
1046         uint32_t reg;
1047         int ret;
1048
1049         /**
1050          *      interrupt pin mux select
1051          **/
1052         ret = spi_read_reg(WILC_PIN_MUX_0, &reg);
1053         if (!ret) {
1054                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1055                 return 0;
1056         }
1057         reg |= (1 << 8);
1058         ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1059         if (!ret) {
1060                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1061                 return 0;
1062         }
1063
1064         /**
1065          *      interrupt enable
1066          **/
1067         ret = spi_read_reg(WILC_INTR_ENABLE, &reg);
1068         if (!ret) {
1069                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1070                 return 0;
1071         }
1072         reg |= (1 << 16);
1073         ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1074         if (!ret) {
1075                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1076                 return 0;
1077         }
1078
1079         return 1;
1080 }
1081
1082 static int spi_init(wilc_wlan_inp_t *inp, wilc_debug_func func)
1083 {
1084         uint32_t reg;
1085         uint32_t chipid;
1086
1087         static int isinit;
1088
1089         if (isinit) {
1090
1091                 if (!spi_read_reg(0x1000, &chipid)) {
1092                         PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1093                         return 0;
1094                 }
1095                 return 1;
1096         }
1097
1098         memset(&g_spi, 0, sizeof(wilc_spi_t));
1099
1100         g_spi.dPrint = func;
1101         g_spi.os_context = inp->os_context.os_private;
1102         if (inp->io_func.io_init) {
1103                 if (!inp->io_func.io_init(g_spi.os_context)) {
1104                         PRINT_ER("[wilc spi]: Failed io init bus...\n");
1105                         return 0;
1106                 }
1107         } else {
1108                 return 0;
1109         }
1110         g_spi.spi_tx = inp->io_func.u.spi.spi_tx;
1111         g_spi.spi_rx = inp->io_func.u.spi.spi_rx;
1112         g_spi.spi_trx = inp->io_func.u.spi.spi_trx;
1113         g_spi.spi_max_speed = inp->io_func.u.spi.spi_max_speed;
1114
1115         /**
1116          *      configure protocol
1117          **/
1118         g_spi.crc_off = 0;
1119
1120         /* TODO: We can remove the CRC trials if there is a definite way to reset */
1121         /* the SPI to it's initial value. */
1122         if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, &reg)) {
1123                 /* Read failed. Try with CRC off. This might happen when module
1124                  * is removed but chip isn't reset*/
1125                 g_spi.crc_off = 1;
1126                 PRINT_ER("[wilc spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n");
1127                 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, &reg)) {
1128                         /* Reaad failed with both CRC on and off, something went bad */
1129                         PRINT_ER("[wilc spi]: Failed internal read protocol...\n");
1130                         return 0;
1131                 }
1132         }
1133         if (g_spi.crc_off == 0) {
1134                 reg &= ~0xc;    /* disable crc checking */
1135                 reg &= ~0x70;
1136                 reg |= (0x5 << 4);
1137                 if (!spi_internal_write(WILC_SPI_PROTOCOL_OFFSET, reg)) {
1138                         PRINT_ER("[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
1139                         return 0;
1140                 }
1141                 g_spi.crc_off = 1;
1142         }
1143
1144
1145         /**
1146          *      make sure can read back chip id correctly
1147          **/
1148         if (!spi_read_reg(0x1000, &chipid)) {
1149                 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1150                 return 0;
1151         }
1152         /* PRINT_ER("[wilc spi]: chipid (%08x)\n", chipid); */
1153
1154         g_spi.has_thrpt_enh = 1;
1155
1156         isinit = 1;
1157
1158         return 1;
1159 }
1160
1161 static void spi_max_bus_speed(void)
1162 {
1163         g_spi.spi_max_speed();
1164 }
1165
1166 static void spi_default_bus_speed(void)
1167 {
1168 }
1169
1170 static int spi_read_size(uint32_t *size)
1171 {
1172         int ret;
1173         if (g_spi.has_thrpt_enh) {
1174                 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, size);
1175                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
1176         } else {
1177                 uint32_t tmp;
1178                 uint32_t byte_cnt;
1179
1180                 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1181                 if (!ret) {
1182                         PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1183                         goto _fail_;
1184                 }
1185                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1186                 *size = tmp;
1187         }
1188
1189
1190
1191 _fail_:
1192         return ret;
1193 }
1194
1195
1196
1197 static int spi_read_int(uint32_t *int_status)
1198 {
1199         int ret;
1200         if (g_spi.has_thrpt_enh) {
1201                 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, int_status);
1202         } else {
1203                 uint32_t tmp;
1204                 uint32_t byte_cnt;
1205
1206                 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1207                 if (!ret) {
1208                         PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1209                         goto _fail_;
1210                 }
1211                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1212
1213                 {
1214                         int happended, j;
1215
1216                         j = 0;
1217                         do {
1218                                 uint32_t irq_flags;
1219
1220                                 happended = 0;
1221
1222                                 spi_read_reg(0x1a90, &irq_flags);
1223                                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
1224
1225                                 if (g_spi.nint > 5) {
1226                                         spi_read_reg(0x1a94, &irq_flags);
1227                                         tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
1228                                 }
1229
1230                                 {
1231                                         uint32_t unkmown_mask;
1232
1233                                         unkmown_mask = ~((1ul << g_spi.nint) - 1);
1234
1235                                         if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
1236                                                 PRINT_ER("[wilc spi]: Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
1237                                                 happended = 1;
1238                                         }
1239                                 }
1240                                 j++;
1241                         } while (happended);
1242                 }
1243
1244                 *int_status = tmp;
1245
1246         }
1247
1248 _fail_:
1249         return ret;
1250 }
1251
1252 static int spi_clear_int_ext(uint32_t val)
1253 {
1254         int ret;
1255
1256         if (g_spi.has_thrpt_enh) {
1257                 ret = spi_internal_write(0xe844 - WILC_SPI_REG_BASE, val);
1258         } else {
1259                 uint32_t flags;
1260                 flags = val & ((1 << MAX_NUM_INT) - 1);
1261                 if (flags) {
1262                         int i;
1263
1264                         ret = 1;
1265                         for (i = 0; i < g_spi.nint; i++) {
1266                                 /* No matter what you write 1 or 0, it will clear interrupt. */
1267                                 if (flags & 1)
1268                                         ret = spi_write_reg(0x10c8 + i * 4, 1);
1269                                 if (!ret)
1270                                         break;
1271                                 flags >>= 1;
1272                         }
1273                         if (!ret) {
1274                                 PRINT_ER("[wilc spi]: Failed spi_write_reg, set reg %x ...\n", 0x10c8 + i * 4);
1275                                 goto _fail_;
1276                         }
1277                         for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1278                                 if (flags & 1)
1279                                         PRINT_ER("[wilc spi]: Unexpected interrupt cleared %d...\n", i);
1280                                 flags >>= 1;
1281                         }
1282                 }
1283
1284                 {
1285                         uint32_t tbl_ctl;
1286
1287                         tbl_ctl = 0;
1288                         /* select VMM table 0 */
1289                         if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1290                                 tbl_ctl |= (1 << 0);
1291                         /* select VMM table 1 */
1292                         if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1293                                 tbl_ctl |= (1 << 1);
1294
1295                         ret = spi_write_reg(WILC_VMM_TBL_CTL, tbl_ctl);
1296                         if (!ret) {
1297                                 PRINT_ER("[wilc spi]: fail write reg vmm_tbl_ctl...\n");
1298                                 goto _fail_;
1299                         }
1300
1301                         if ((val & EN_VMM) == EN_VMM) {
1302                                 /**
1303                                  *      enable vmm transfer.
1304                                  **/
1305                                 ret = spi_write_reg(WILC_VMM_CORE_CTL, 1);
1306                                 if (!ret) {
1307                                         PRINT_ER("[wilc spi]: fail write reg vmm_core_ctl...\n");
1308                                         goto _fail_;
1309                                 }
1310                         }
1311                 }
1312         }
1313 _fail_:
1314         return ret;
1315 }
1316
1317 static int spi_sync_ext(int nint /*  how mant interrupts to enable. */)
1318 {
1319         uint32_t reg;
1320         int ret, i;
1321
1322         if (nint > MAX_NUM_INT) {
1323                 PRINT_ER("[wilc spi]: Too many interupts (%d)...\n", nint);
1324                 return 0;
1325         }
1326
1327         g_spi.nint = nint;
1328
1329         /**
1330          *      interrupt pin mux select
1331          **/
1332         ret = spi_read_reg(WILC_PIN_MUX_0, &reg);
1333         if (!ret) {
1334                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1335                 return 0;
1336         }
1337         reg |= (1 << 8);
1338         ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1339         if (!ret) {
1340                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1341                 return 0;
1342         }
1343
1344         /**
1345          *      interrupt enable
1346          **/
1347         ret = spi_read_reg(WILC_INTR_ENABLE, &reg);
1348         if (!ret) {
1349                 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1350                 return 0;
1351         }
1352
1353         for (i = 0; (i < 5) && (nint > 0); i++, nint--) {
1354                 reg |= (1 << (27 + i));
1355         }
1356         ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1357         if (!ret) {
1358                 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1359                 return 0;
1360         }
1361         if (nint) {
1362                 ret = spi_read_reg(WILC_INTR2_ENABLE, &reg);
1363                 if (!ret) {
1364                         PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR2_ENABLE);
1365                         return 0;
1366                 }
1367
1368                 for (i = 0; (i < 3) && (nint > 0); i++, nint--) {
1369                         reg |= (1 << i);
1370                 }
1371
1372                 ret = spi_read_reg(WILC_INTR2_ENABLE, &reg);
1373                 if (!ret) {
1374                         PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR2_ENABLE);
1375                         return 0;
1376                 }
1377         }
1378
1379         return 1;
1380 }
1381 /********************************************
1382  *
1383  *      Global spi HIF function table
1384  *
1385  ********************************************/
1386 wilc_hif_func_t hif_spi = {
1387         spi_init,
1388         spi_deinit,
1389         spi_read_reg,
1390         spi_write_reg,
1391         spi_read,
1392         spi_write,
1393         spi_sync,
1394         spi_clear_int,
1395         spi_read_int,
1396         spi_clear_int_ext,
1397         spi_read_size,
1398         spi_write,
1399         spi_read,
1400         spi_sync_ext,
1401         spi_max_bus_speed,
1402         spi_default_bus_speed,
1403 };