drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #include <drv_types.h>
  17 #include <rtw_debug.h>
  18 #include "odm_precomp.h"
  19
  20
  21
  22 /*---------------------------Define Local Constant---------------------------*/
  23 /*  2010/04/25 MH Define the max tx power tracking tx agc power. */
  24 #define         ODM_TXPWRTRACK_MAX_IDX8723B     6
  25
  26 /*  MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
  27 #define         PATH_S0                                                 1 /*  RF_PATH_B */
  28 #define         IDX_0xC94                                               0
  29 #define         IDX_0xC80                                               1
  30 #define         IDX_0xC4C                                               2
  31 #define         IDX_0xC14                                               0
  32 #define         IDX_0xCA0                                               1
  33 #define         KEY                                                     0
  34 #define         VAL                                                     1
  35
  36 /*  MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */
  37 #define         PATH_S1                                                 0 /*  RF_PATH_A */
  38 #define         IDX_0xC9C                                               0
  39 #define         IDX_0xC88                                               1
  40 #define         IDX_0xC4C                                               2
  41 #define         IDX_0xC1C                                               0
  42 #define         IDX_0xC78                                               1
  43
  44
  45 /*---------------------------Define Local Constant---------------------------*/
  46
  47 /* In the case that we fail to read TxPowerTrack.txt, we use the table for
  48  * 88E as the default table.
  49  */
  50 static u8 DeltaSwingTableIdx_2GA_N_8188E[] = {
  51         0, 0, 0, 2, 2, 3, 3, 4,  4,  4,  4,  5,  5,  6,  6,
  52         7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
  53 };
  54 static u8 DeltaSwingTableIdx_2GA_P_8188E[] = {
  55         0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4,
  56         4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9
  57 };
  58
  59 /* 3 ============================================================ */
  60 /* 3 Tx Power Tracking */
  61 /* 3 ============================================================ */
  62
  63
  64 static void setIqkMatrix_8723B(
  65         PDM_ODM_T pDM_Odm,
  66         u8 OFDM_index,
  67         u8 RFPath,
  68         s32 IqkResult_X,
  69         s32 IqkResult_Y
  70 )
  71 {
  72         s32 ele_A = 0, ele_D, ele_C = 0, value32;
  73
  74         if (OFDM_index >= OFDM_TABLE_SIZE)
  75                 OFDM_index = OFDM_TABLE_SIZE-1;
  76
  77         ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;
  78
  79         /* new element A = element D x X */
  80         if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) {
  81                 if ((IqkResult_X & 0x00000200) != 0)    /* consider minus */
  82                         IqkResult_X = IqkResult_X | 0xFFFFFC00;
  83                 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;
  84
  85                 /* new element C = element D x Y */
  86                 if ((IqkResult_Y & 0x00000200) != 0)
  87                         IqkResult_Y = IqkResult_Y | 0xFFFFFC00;
  88                 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;
  89
  90                 /* if (RFPath == ODM_RF_PATH_A) */
  91                 switch (RFPath) {
  92                 case ODM_RF_PATH_A:
  93                         /* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
  94                         value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
  95                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
  96
  97                         value32 = (ele_C&0x000003C0)>>6;
  98                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
  99
 100                         value32 = ((IqkResult_X * ele_D)>>7)&0x01;
 101                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32);
 102                         break;
 103                 case ODM_RF_PATH_B:
 104                         /* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
 105                         value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
 106                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
 107
 108                         value32 = (ele_C&0x000003C0)>>6;
 109                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
 110
 111                         value32 = ((IqkResult_X * ele_D)>>7)&0x01;
 112                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32);
 113
 114                         break;
 115                 default:
 116                         break;
 117                 }
 118         } else {
 119                 switch (RFPath) {
 120                 case ODM_RF_PATH_A:
 121                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
 122                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
 123                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00);
 124                         break;
 125
 126                 case ODM_RF_PATH_B:
 127                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
 128                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
 129                         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00);
 130                         break;
 131
 132                 default:
 133                         break;
 134                 }
 135         }
 136
 137         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
 138         (u32)IqkResult_X, (u32)IqkResult_Y, (u32)ele_A, (u32)ele_C, (u32)ele_D, (u32)IqkResult_X, (u32)IqkResult_Y));
 139 }
 140
 141
 142 static void setCCKFilterCoefficient(PDM_ODM_T pDM_Odm, u8 CCKSwingIndex)
 143 {
 144         if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 145                 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]);
 146                 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]);
 147                 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]);
 148                 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]);
 149                 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]);
 150                 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]);
 151                 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]);
 152                 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]);
 153         } else {
 154                 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]);
 155                 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]);
 156                 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]);
 157                 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]);
 158                 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]);
 159                 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]);
 160                 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]);
 161                 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]);
 162         }
 163 }
 164
 165 void DoIQK_8723B(
 166         PDM_ODM_T pDM_Odm,
 167         u8 DeltaThermalIndex,
 168         u8 ThermalValue,
 169         u8 Threshold
 170 )
 171 {
 172 }
 173
 174 /*-----------------------------------------------------------------------------
 175  * Function:    odm_TxPwrTrackSetPwr88E()
 176  *
 177  * Overview:    88E change all channel tx power accordign to flag.
 178  *                      OFDM & CCK are all different.
 179  *
 180  * Input:               NONE
 181  *
 182  * Output:              NONE
 183  *
 184  * Return:              NONE
 185  *
 186  * Revised History:
 187  *When          Who     Remark
 188  *04/23/2012    MHC     Create Version 0.
 189  *
 190  *---------------------------------------------------------------------------*/
 191 void ODM_TxPwrTrackSetPwr_8723B(
 192         PDM_ODM_T pDM_Odm,
 193         PWRTRACK_METHOD Method,
 194         u8 RFPath,
 195         u8 ChannelMappedIndex
 196 )
 197 {
 198         struct adapter *Adapter = pDM_Odm->Adapter;
 199         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 200         u8 PwrTrackingLimit_OFDM = 34; /* 0dB */
 201         u8 PwrTrackingLimit_CCK = 28; /* 2dB */
 202         u8 TxRate = 0xFF;
 203         u8 Final_OFDM_Swing_Index = 0;
 204         u8 Final_CCK_Swing_Index = 0;
 205
 206         {
 207                 u16 rate = *(pDM_Odm->pForcedDataRate);
 208
 209                 if (!rate) { /* auto rate */
 210                         if (pDM_Odm->TxRate != 0xFF)
 211                                 TxRate = HwRateToMRate(pDM_Odm->TxRate);
 212                 } else /* force rate */
 213                         TxRate = (u8)rate;
 214
 215         }
 216
 217         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8723B\n"));
 218
 219         if (TxRate != 0xFF) {
 220                 /* 2 CCK */
 221                 if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M))
 222                         PwrTrackingLimit_CCK = 28;      /* 2dB */
 223                 /* 2 OFDM */
 224                 else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M))
 225                         PwrTrackingLimit_OFDM = 36; /* 3dB */
 226                 else if (TxRate == MGN_54M)
 227                         PwrTrackingLimit_OFDM = 34; /* 2dB */
 228
 229                 /* 2 HT */
 230                 else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /* QPSK/BPSK */
 231                         PwrTrackingLimit_OFDM = 38; /* 4dB */
 232                 else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /* 16QAM */
 233                         PwrTrackingLimit_OFDM = 36; /* 3dB */
 234                 else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /* 64QAM */
 235                         PwrTrackingLimit_OFDM = 34; /* 2dB */
 236
 237                 else
 238                         PwrTrackingLimit_OFDM =  pDM_Odm->DefaultOfdmIndex;   /* Default OFDM index = 30 */
 239         }
 240         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate = 0x%x, PwrTrackingLimit =%d\n", TxRate, PwrTrackingLimit_OFDM));
 241
 242         if (Method == TXAGC) {
 243                 struct adapter *Adapter = pDM_Odm->Adapter;
 244
 245                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH =%d\n", *(pDM_Odm->pChannel)));
 246
 247                 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
 248
 249                 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
 250                 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
 251
 252                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
 253                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
 254                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
 255         } else if (Method == BBSWING) {
 256                 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
 257                 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
 258
 259                 /*  Adjust BB swing by OFDM IQ matrix */
 260                 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
 261                         Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
 262                 else if (Final_OFDM_Swing_Index <= 0)
 263                         Final_OFDM_Swing_Index = 0;
 264
 265                 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)
 266                         Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;
 267                 else if (pDM_Odm->BbSwingIdxCck <= 0)
 268                         Final_CCK_Swing_Index = 0;
 269
 270                 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
 271                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
 272                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
 273
 274                 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
 275
 276         } else if (Method == MIX_MODE) {
 277                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 278                         ("pDM_Odm->DefaultOfdmIndex =%d,  pDM_Odm->DefaultCCKIndex =%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
 279                         pDM_Odm->DefaultOfdmIndex, pDM_Odm->DefaultCckIndex, pDM_Odm->Absolute_OFDMSwingIdx[RFPath], RFPath));
 280
 281                 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
 282                 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
 283
 284                 if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /* BBSwing higher then Limit */
 285                         pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;
 286
 287                         setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath,
 288                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
 289                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
 290
 291                         pDM_Odm->Modify_TxAGC_Flag_PathA = true;
 292                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
 293                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
 294
 295                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 296                                 ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n",
 297                                 PwrTrackingLimit_OFDM, pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));
 298                 } else if (Final_OFDM_Swing_Index <= 0) {
 299                         pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index;
 300
 301                         setIqkMatrix_8723B(pDM_Odm, 0, RFPath,
 302                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
 303                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
 304
 305                         pDM_Odm->Modify_TxAGC_Flag_PathA = true;
 306                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
 307                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
 308
 309                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 310                                 ("******Path_A Lower then BBSwing lower bound  0 , Remnant TxAGC Value = %d\n",
 311                                 pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));
 312                 } else {
 313                         setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
 314                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
 315                                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
 316
 317                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 318                                 ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index));
 319
 320                         if (pDM_Odm->Modify_TxAGC_Flag_PathA) { /* If TxAGC has changed, reset TxAGC again */
 321                                 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0;
 322                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
 323                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
 324                                 pDM_Odm->Modify_TxAGC_Flag_PathA = false;
 325
 326                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 327                                         ("******Path_A pDM_Odm->Modify_TxAGC_Flag = false\n"));
 328                         }
 329                 }
 330
 331                 if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) {
 332                         pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;
 333                         setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);
 334                         pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
 335                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
 336
 337                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 338                                 ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx  = %d\n", PwrTrackingLimit_CCK, pDM_Odm->Remnant_CCKSwingIdx));
 339                 } else if (Final_CCK_Swing_Index <= 0) { /*  Lowest CCK Index = 0 */
 340                         pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
 341                         setCCKFilterCoefficient(pDM_Odm, 0);
 342                         pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
 343                         PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
 344
 345                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 346                                 ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx  = %d\n", 0, pDM_Odm->Remnant_CCKSwingIdx));
 347                 } else {
 348                         setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
 349
 350                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 351                                 ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index));
 352
 353                         if (pDM_Odm->Modify_TxAGC_Flag_PathA_CCK) { /* If TxAGC has changed, reset TxAGC again */
 354                                 pDM_Odm->Remnant_CCKSwingIdx = 0;
 355                                 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
 356                                 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = false;
 357
 358                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
 359                                         ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = false\n"));
 360                         }
 361                 }
 362         } else
 363                 return; /*  This method is not supported. */
 364 }
 365
 366 static void GetDeltaSwingTable_8723B(
 367         PDM_ODM_T pDM_Odm,
 368         u8 **TemperatureUP_A,
 369         u8 **TemperatureDOWN_A,
 370         u8 **TemperatureUP_B,
 371         u8 **TemperatureDOWN_B
 372 )
 373 {
 374         struct adapter *Adapter = pDM_Odm->Adapter;
 375         PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
 376         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 377         u16 rate = *(pDM_Odm->pForcedDataRate);
 378         u8 channel = pHalData->CurrentChannel;
 379
 380         if (1 <= channel && channel <= 14) {
 381                 if (IS_CCK_RATE(rate)) {
 382                         *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
 383                         *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
 384                         *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
 385                         *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
 386                 } else {
 387                         *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
 388                         *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
 389                         *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
 390                         *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
 391                 }
 392         } /*else if (36 <= channel && channel <= 64) {
 393                 *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0];
 394                 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0];
 395                 *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0];
 396                 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0];
 397         } else if (100 <= channel && channel <= 140) {
 398                 *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1];
 399                 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1];
 400                 *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1];
 401                 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1];
 402         } else if (149 <= channel && channel <= 173) {
 403                 *TemperatureUP_A   = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2];
 404                 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2];
 405                 *TemperatureUP_B   = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2];
 406                 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2];
 407         }*/else {
 408                 *TemperatureUP_A   = (u8 *)DeltaSwingTableIdx_2GA_P_8188E;
 409                 *TemperatureDOWN_A = (u8 *)DeltaSwingTableIdx_2GA_N_8188E;
 410                 *TemperatureUP_B   = (u8 *)DeltaSwingTableIdx_2GA_P_8188E;
 411                 *TemperatureDOWN_B = (u8 *)DeltaSwingTableIdx_2GA_N_8188E;
 412         }
 413
 414         return;
 415 }
 416
 417
 418 void ConfigureTxpowerTrack_8723B(PTXPWRTRACK_CFG pConfig)
 419 {
 420         pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
 421         pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
 422         pConfig->Threshold_IQK = IQK_THRESHOLD;
 423         pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B;
 424         pConfig->RfPathCount = MAX_PATH_NUM_8723B;
 425         pConfig->ThermalRegAddr = RF_T_METER_8723B;
 426
 427         pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B;
 428         pConfig->DoIQK = DoIQK_8723B;
 429         pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B;
 430         pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B;
 431 }
 432
 433 /* 1 7. IQK */
 434 #define MAX_TOLERANCE           5
 435 #define IQK_DELAY_TIME          1               /* ms */
 436
 437 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
 438 static u8 phy_PathA_IQK_8723B(
 439         struct adapter *padapter, bool configPathB, u8 RF_Path
 440 )
 441 {
 442         u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/;
 443         u8 result = 0x00;
 444
 445         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
 446         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;
 447
 448         /*  Save RF Path */
 449         Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
 450
 451         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));
 452
 453         /* leave IQK mode */
 454         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 455
 456         /*      enable path A PA in TXIQK mode */
 457         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
 458         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
 459         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f);
 460         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87);
 461         /*      disable path B PA in TXIQK mode */
 462 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */
 463 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */
 464
 465         /* 1 Tx IQK */
 466         /* IQK setting */
 467         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
 468         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
 469         /* path-A IQK setting */
 470 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); */
 471         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
 472         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
 473         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 474         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 475 /*      PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */
 476         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
 477         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
 478         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
 479         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
 480
 481         /* LO calibration setting */
 482 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
 483         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
 484
 485         /* enter IQK mode */
 486         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
 487
 488         /* Ant switch */
 489         if (configPathB || (RF_Path == 0))
 490                 /*  wifi switch to S1 */
 491                 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
 492         else
 493                 /*  wifi switch to S0 */
 494                 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
 495
 496         /* GNT_BT = 0 */
 497         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
 498
 499         /* One shot, path A LOK & IQK */
 500 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */
 501         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 502         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 503
 504         /*  delay x ms */
 505 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); */
 506         /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
 507         mdelay(IQK_DELAY_TIME_8723B);
 508
 509         /* restore Ant Path */
 510         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
 511         /* GNT_BT = 1 */
 512         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
 513
 514         /* leave IQK mode */
 515         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 516
 517
 518         /*  Check failed */
 519         regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
 520         regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
 521         regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
 522         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
 523         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
 524         /* monitor image power before & after IQK */
 525         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n",
 526         PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord)));
 527
 528
 529         /* Allen 20131125 */
 530         tmp = (regE9C & 0x03FF0000)>>16;
 531         if ((tmp & 0x200) > 0)
 532                 tmp = 0x400 - tmp;
 533
 534         if (
 535                 !(regEAC & BIT28) &&
 536                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
 537                 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
 538                 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
 539                 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
 540                 (tmp < 0xf)
 541         )
 542                 result |= 0x01;
 543         else                                    /* if Tx not OK, ignore Rx */
 544                 return result;
 545
 546         return result;
 547 }
 548
 549 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
 550 static u8 phy_PathA_RxIQK8723B(
 551         struct adapter *padapter, bool configPathB, u8 RF_Path
 552 )
 553 {
 554         u32 regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB;
 555         u8 result = 0x00;
 556         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 557         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
 558
 559 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); */
 560
 561         /*  Save RF Path */
 562         Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
 563
 564         /* leave IQK mode */
 565         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 566
 567         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n"));
 568         /* 1 Get TXIMR setting */
 569         /* modify RXIQK mode table */
 570 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); */
 571         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
 572         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
 573         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
 574         /* LNA2 off, PA on for Dcut */
 575         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
 576 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
 577         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
 578
 579         /* IQK setting */
 580         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
 581         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
 582
 583         /* path-A IQK setting */
 584         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
 585         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
 586         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 587         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 588
 589 /*      PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
 590         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
 591         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
 592         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
 593         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
 594
 595         /* LO calibration setting */
 596 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
 597         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
 598
 599         /* enter IQK mode */
 600         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
 601
 602         /* Ant switch */
 603         if (configPathB || (RF_Path == 0))
 604                 /*  wifi switch to S1 */
 605                 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
 606         else
 607                 /*  wifi switch to S0 */
 608                 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
 609
 610         /* GNT_BT = 0 */
 611         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
 612
 613         /* One shot, path A LOK & IQK */
 614 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */
 615         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 616         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 617
 618         /*  delay x ms */
 619 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); */
 620         /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
 621         mdelay(IQK_DELAY_TIME_8723B);
 622
 623         /* restore Ant Path */
 624         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
 625         /* GNT_BT = 1 */
 626         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
 627
 628         /* leave IQK mode */
 629         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 630
 631         /*  Check failed */
 632         regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
 633         regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
 634         regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
 635         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
 636         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
 637         /* monitor image power before & after IQK */
 638         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n",
 639         PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord)));
 640
 641         /* Allen 20131125 */
 642         tmp = (regE9C & 0x03FF0000)>>16;
 643         if ((tmp & 0x200) > 0)
 644                 tmp = 0x400 - tmp;
 645
 646         if (
 647                 !(regEAC & BIT28) &&
 648                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
 649                 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
 650                 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
 651                 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
 652                 (tmp < 0xf)
 653         )
 654                 result |= 0x01;
 655         else                            /* if Tx not OK, ignore Rx */
 656                 return result;
 657
 658         u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
 659         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp);
 660         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord), u4tmp));
 661
 662
 663         /* 1 RX IQK */
 664         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n"));
 665
 666         /* modify RXIQK mode table */
 667 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); */
 668         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 669         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
 670         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
 671         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
 672         /* LAN2 on, PA off for Dcut */
 673         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
 674 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
 675
 676         /* PA, PAD setting */
 677         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);
 678         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f);
 679
 680
 681         /* IQK setting */
 682         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
 683
 684         /* path-A IQK setting */
 685         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
 686         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
 687         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 688         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 689
 690         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
 691 /*      PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
 692         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
 693         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
 694         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
 695
 696         /* LO calibration setting */
 697 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
 698         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
 699
 700         /* enter IQK mode */
 701         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
 702
 703         /* Ant switch */
 704         if (configPathB || (RF_Path == 0))
 705                 /*  wifi switch to S1 */
 706                 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
 707         else
 708                 /*  wifi switch to S0 */
 709                 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
 710
 711         /* GNT_BT = 0 */
 712         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
 713
 714         /* One shot, path A LOK & IQK */
 715 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */
 716         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 717         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 718
 719         /*  delay x ms */
 720 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */
 721         /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
 722         mdelay(IQK_DELAY_TIME_8723B);
 723
 724         /* restore Ant Path */
 725         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
 726         /* GNT_BT = 1 */
 727         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
 728
 729     /* leave IQK mode */
 730         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 731
 732         /*  Check failed */
 733         regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
 734         regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
 735         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));
 736         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));
 737         /* monitor image power before & after IQK */
 738         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK) = 0x%x, 0xea8(afer IQK) = 0x%x\n",
 739         PHY_QueryBBReg(pDM_Odm->Adapter, 0xea0, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xea8, bMaskDWord)));
 740
 741         /*      PA/PAD controlled by 0x0 */
 742         /* leave IQK mode */
 743         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 744         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780);
 745
 746         /* Allen 20131125 */
 747         tmp = (regEAC & 0x03FF0000)>>16;
 748         if ((tmp & 0x200) > 0)
 749                 tmp = 0x400 - tmp;
 750
 751         if (
 752                 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
 753                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
 754                 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
 755                 (((regEA4 & 0x03FF0000)>>16) < 0x110) &&
 756                 (((regEA4 & 0x03FF0000)>>16) > 0xf0) &&
 757                 (tmp < 0xf)
 758         )
 759                 result |= 0x02;
 760         else                                                    /* if Tx not OK, ignore Rx */
 761                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A Rx IQK fail!!\n"));
 762         return result;
 763 }
 764
 765 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
 766 static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
 767 {
 768         u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/;
 769         u8 result = 0x00;
 770         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
 771         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
 772
 773         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B IQK!\n"));
 774
 775         /*  Save RF Path */
 776         Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
 777
 778     /* leave IQK mode */
 779         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 780
 781         /*      in TXIQK mode */
 782 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */
 783 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */
 784 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */
 785 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */
 786         /*      enable path B PA in TXIQK mode */
 787         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
 788         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1);
 789
 790
 791
 792         /* 1 Tx IQK */
 793         /* IQK setting */
 794         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
 795         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
 796         /* path-A IQK setting */
 797 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); */
 798         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
 799         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
 800         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 801         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 802
 803 /*      PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */
 804         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
 805         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
 806         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
 807         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
 808
 809         /* LO calibration setting */
 810 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
 811         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
 812
 813         /* enter IQK mode */
 814         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
 815
 816         /* switch to path B */
 817         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
 818 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
 819
 820         /* GNT_BT = 0 */
 821         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
 822
 823         /* One shot, path B LOK & IQK */
 824 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */
 825         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 826         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 827
 828         /*  delay x ms */
 829 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); */
 830         /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
 831         mdelay(IQK_DELAY_TIME_8723B);
 832
 833         /* restore Ant Path */
 834         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
 835         /* GNT_BT = 1 */
 836         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
 837
 838     /* leave IQK mode */
 839         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 840
 841 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord))); */
 842
 843
 844         /*  Check failed */
 845         regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
 846         regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
 847         regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
 848         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));
 849         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
 850         /* monitor image power before & after IQK */
 851         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n",
 852         PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord)));
 853
 854         /* Allen 20131125 */
 855         tmp = (regE9C & 0x03FF0000)>>16;
 856         if ((tmp & 0x200) > 0)
 857                 tmp = 0x400 - tmp;
 858
 859         if (
 860                 !(regEAC & BIT28) &&
 861                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
 862                 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
 863                 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
 864                 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
 865                 (tmp < 0xf)
 866         )
 867                 result |= 0x01;
 868
 869         return result;
 870 }
 871
 872 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
 873 static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
 874 {
 875         u32 regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB;
 876         u8 result = 0x00;
 877         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 878         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
 879
 880 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); */
 881
 882         /*  Save RF Path */
 883         Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
 884     /* leave IQK mode */
 885         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 886
 887         /* switch to path B */
 888         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
 889
 890         /* 1 Get TXIMR setting */
 891         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n"));
 892         /* modify RXIQK mode table */
 893 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); */
 894         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
 895         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
 896         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
 897         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
 898         /* open PA S1 & SMIXER */
 899         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
 900         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd);
 901
 902
 903         /* IQK setting */
 904         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
 905         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
 906
 907
 908         /* path-B IQK setting */
 909         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
 910         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
 911         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 912         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
 913
 914 /*      PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
 915         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
 916         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
 917         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
 918         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
 919
 920         /* LO calibration setting */
 921 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
 922         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
 923
 924     /* enter IQK mode */
 925         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
 926
 927         /* switch to path B */
 928         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
 929 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
 930
 931         /* GNT_BT = 0 */
 932         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
 933
 934         /* One shot, path B TXIQK @ RXIQK */
 935 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */
 936         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
 937         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
 938
 939
 940         /*  delay x ms */
 941 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */
 942         /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
 943         mdelay(IQK_DELAY_TIME_8723B);
 944
 945         /* restore Ant Path */
 946         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
 947         /* GNT_BT = 1 */
 948         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
 949
 950     /* leave IQK mode */
 951         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 952
 953         /*  Check failed */
 954         regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
 955         regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
 956         regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
 957         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));
 958         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
 959         /* monitor image power before & after IQK */
 960         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n",
 961                 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord)));
 962
 963         /* Allen 20131125 */
 964         tmp = (regE9C & 0x03FF0000)>>16;
 965 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("tmp1 = 0x%x\n", tmp)); */
 966         if ((tmp & 0x200) > 0)
 967                 tmp = 0x400 - tmp;
 968 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("tmp2 = 0x%x\n", tmp)); */
 969
 970         if (
 971                 !(regEAC & BIT28) &&
 972                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
 973                 (((regE9C & 0x03FF0000)>>16) != 0x42)  &&
 974                 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
 975                 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
 976                 (tmp < 0xf)
 977         )
 978                         result |= 0x01;
 979         else    /* if Tx not OK, ignore Rx */
 980                 return result;
 981
 982         u4tmp = 0x80007C00 | (regE94&0x3FF0000)  | ((regE9C&0x3FF0000) >> 16);
 983         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp);
 984         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord), u4tmp));
 985
 986         /* 1 RX IQK */
 987         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n"));
 988
 989         /* modify RXIQK mode table */
 990         /* 20121009, Kordan> RF Mode = 3 */
 991         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
 992         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
 993         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
 994         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
 995         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
 996 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
 997
 998         /* open PA S1 & close SMIXER */
 999         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
1000         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd);
1001
1002         /* PA, PAD setting */
1003 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */
1004 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */
1005
1006         /* IQK setting */
1007         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
1008
1009         /* path-B IQK setting */
1010         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
1011         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
1012         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
1013         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
1014
1015         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
1016 /*      PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
1017         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
1018         PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
1019         PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
1020
1021         /* LO calibration setting */
1022 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */
1023         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
1024
1025     /* enter IQK mode */
1026         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
1027
1028         /* switch to path B */
1029         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
1030 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
1031
1032         /* GNT_BT = 0 */
1033         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
1034
1035         /* One shot, path B LOK & IQK */
1036 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */
1037         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
1038         PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1039
1040         /*  delay x ms */
1041 /*      ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */
1042         /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
1043         mdelay(IQK_DELAY_TIME_8723B);
1044
1045         /* restore Ant Path */
1046         PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
1047         /* GNT_BT = 1 */
1048         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
1049
1050     /* leave IQK mode */
1051         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1052
1053         /*  Check failed */
1054         regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
1055         regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
1056
1057         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));
1058         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));
1059         /* monitor image power before & after IQK */
1060         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK) = 0x%x, 0xea8(afer IQK) = 0x%x\n",
1061                 PHY_QueryBBReg(pDM_Odm->Adapter, 0xea0, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xea8, bMaskDWord)));
1062
1063         /*      PA/PAD controlled by 0x0 */
1064         /* leave IQK mode */
1065 /*      PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */
1066 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */
1067
1068
1069
1070         /* Allen 20131125 */
1071         tmp = (regEAC & 0x03FF0000)>>16;
1072         if ((tmp & 0x200) > 0)
1073                 tmp = 0x400 - tmp;
1074
1075         if (
1076                 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
1077                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
1078                 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
1079                 (((regEA4 & 0x03FF0000)>>16) < 0x110) &&
1080                 (((regEA4 & 0x03FF0000)>>16) > 0xf0) &&
1081                 (tmp < 0xf)
1082         )
1083                 result |= 0x02;
1084         else
1085                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK fail!!\n"));
1086
1087         return result;
1088 }
1089
1090 static void _PHY_PathAFillIQKMatrix8723B(
1091         struct adapter *padapter,
1092         bool bIQKOK,
1093         s32 result[][8],
1094         u8 final_candidate,
1095         bool bTxOnly
1096 )
1097 {
1098         u32 Oldval_0, X, TX0_A, reg;
1099         s32 Y, TX0_C;
1100         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
1101         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1102
1103         PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1104
1105         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed"));
1106
1107         if (final_candidate == 0xFF)
1108                 return;
1109
1110         else if (bIQKOK) {
1111                 Oldval_0 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
1112
1113                 X = result[final_candidate][0];
1114                 if ((X & 0x00000200) != 0)
1115                         X = X | 0xFFFFFC00;
1116                 TX0_A = (X * Oldval_0) >> 8;
1117                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
1118                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
1119
1120                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval_0>>7) & 0x1));
1121
1122                 Y = result[final_candidate][1];
1123                 if ((Y & 0x00000200) != 0)
1124                         Y = Y | 0xFFFFFC00;
1125
1126                 /* 2 Tx IQC */
1127                 TX0_C = (Y * Oldval_0) >> 8;
1128                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
1129                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
1130                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
1131                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord);
1132
1133                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
1134                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
1135                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord);
1136
1137                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval_0>>7) & 0x1));
1138                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
1139                 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
1140
1141                 if (bTxOnly) {
1142                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n"));
1143
1144                         /*  <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
1145                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1146                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1147                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1148 /*                      pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
1149                         pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;
1150                         return;
1151                 }
1152
1153                 reg = result[final_candidate][2];
1154
1155                 /* 2 Rx IQC */
1156                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
1157                 reg = result[final_candidate][3] & 0x3F;
1158                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
1159                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1160                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord);
1161
1162                 reg = (result[final_candidate][3] >> 6) & 0xF;
1163                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
1164                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1165                 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1166
1167         }
1168 }
1169
1170 static void _PHY_PathBFillIQKMatrix8723B(
1171         struct adapter *padapter,
1172         bool bIQKOK,
1173         s32 result[][8],
1174         u8 final_candidate,
1175         bool bTxOnly /* do Tx only */
1176 )
1177 {
1178         u32 Oldval_1, X, TX1_A, reg;
1179         s32     Y, TX1_C;
1180         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
1181         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1182
1183         PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1184
1185         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed"));
1186
1187         if (final_candidate == 0xFF)
1188                 return;
1189
1190         else if (bIQKOK) {
1191                 Oldval_1 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
1192
1193                 X = result[final_candidate][4];
1194                 if ((X & 0x00000200) != 0)
1195                         X = X | 0xFFFFFC00;
1196                 TX1_A = (X * Oldval_1) >> 8;
1197                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
1198
1199                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
1200
1201                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval_1>>7) & 0x1));
1202
1203                 Y = result[final_candidate][5];
1204                 if ((Y & 0x00000200) != 0)
1205                         Y = Y | 0xFFFFFC00;
1206
1207                 TX1_C = (Y * Oldval_1) >> 8;
1208                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
1209
1210                 /* 2 Tx IQC */
1211                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
1212 /*              pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; */
1213 /*              pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */
1214                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
1215                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord);
1216
1217                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
1218                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
1219                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord);
1220
1221                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval_1>>7) & 0x1));
1222                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
1223                 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
1224
1225                 if (bTxOnly) {
1226                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n"));
1227
1228                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1229 /*                      pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
1230                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;
1231                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1232                         pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1233                         return;
1234                 }
1235
1236                 /* 2 Rx IQC */
1237                 reg = result[final_candidate][6];
1238                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
1239                 reg = result[final_candidate][7] & 0x3F;
1240                 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
1241                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1242                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord);
1243
1244                 reg = (result[final_candidate][7] >> 6) & 0xF;
1245 /*              PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); */
1246                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1247                 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff);
1248         }
1249 }
1250
1251 /*  */
1252 /*  2011/07/26 MH Add an API for testing IQK fail case. */
1253 /*  */
1254 /*  MP Already declare in odm.c */
1255
1256 void ODM_SetIQCbyRFpath(PDM_ODM_T pDM_Odm, u32 RFpath)
1257 {
1258
1259         PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1260
1261         if (
1262                 (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) &&
1263                 (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) &&
1264                 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) &&
1265                 (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)
1266         ) {
1267                 if (RFpath) { /* S1: RFpath = 0, S0:RFpath = 1 */
1268                         /* S0 TX IQC */
1269                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]);
1270                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]);
1271                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]);
1272                         /* S0 RX IQC */
1273                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]);
1274                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]);
1275                 } else {
1276                         /* S1 TX IQC */
1277                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]);
1278                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]);
1279                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]);
1280                         /* S1 RX IQC */
1281                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]);
1282                         PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]);
1283                 }
1284         }
1285 }
1286
1287 static bool ODM_CheckPowerStatus(struct adapter *Adapter)
1288 {
1289         return true;
1290 }
1291
1292 static void _PHY_SaveADDARegisters8723B(
1293         struct adapter *padapter,
1294         u32 *ADDAReg,
1295         u32 *ADDABackup,
1296         u32 RegisterNum
1297 )
1298 {
1299         u32 i;
1300         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1301         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1302
1303         if (ODM_CheckPowerStatus(padapter) == false)
1304                 return;
1305
1306         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
1307         for (i = 0 ; i < RegisterNum ; i++) {
1308                 ADDABackup[i] = PHY_QueryBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord);
1309         }
1310 }
1311
1312
1313 static void _PHY_SaveMACRegisters8723B(
1314         struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1315 )
1316 {
1317         u32 i;
1318         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
1319         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;
1320
1321         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
1322         for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1323                 MACBackup[i] = rtw_read8(pDM_Odm->Adapter, MACReg[i]);
1324         }
1325         MACBackup[i] = rtw_read32(pDM_Odm->Adapter, MACReg[i]);
1326
1327 }
1328
1329
1330 static void _PHY_ReloadADDARegisters8723B(
1331         struct adapter *padapter,
1332         u32 *ADDAReg,
1333         u32 *ADDABackup,
1334         u32 RegiesterNum
1335 )
1336 {
1337         u32 i;
1338         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
1339         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1340
1341         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));
1342         for (i = 0 ; i < RegiesterNum; i++) {
1343                 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, ADDABackup[i]);
1344         }
1345 }
1346
1347 static void _PHY_ReloadMACRegisters8723B(
1348         struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1349 )
1350 {
1351         u32 i;
1352
1353         for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1354                 rtw_write8(padapter, MACReg[i], (u8)MACBackup[i]);
1355         }
1356         rtw_write32(padapter, MACReg[i], MACBackup[i]);
1357 }
1358
1359
1360 static void _PHY_PathADDAOn8723B(
1361         struct adapter *padapter,
1362         u32 *ADDAReg,
1363         bool isPathAOn,
1364         bool is2T
1365 )
1366 {
1367         u32 pathOn;
1368         u32 i;
1369         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1370         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1371
1372         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
1373
1374         pathOn = isPathAOn ? 0x01c00014 : 0x01c00014;
1375         if (false == is2T) {
1376                 pathOn = 0x01c00014;
1377                 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, 0x01c00014);
1378         } else {
1379                 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, pathOn);
1380         }
1381
1382         for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) {
1383                 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, pathOn);
1384         }
1385
1386 }
1387
1388 static void _PHY_MACSettingCalibration8723B(
1389         struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1390 )
1391 {
1392         u32 i = 0;
1393         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
1394         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1395
1396         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));
1397
1398         rtw_write8(pDM_Odm->Adapter, MACReg[i], 0x3F);
1399
1400         for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1401                 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
1402         }
1403         rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
1404
1405 }
1406
1407 static bool phy_SimularityCompare_8723B(
1408         struct adapter *padapter,
1409         s32 result[][8],
1410         u8  c1,
1411         u8  c2
1412 )
1413 {
1414         u32 i, j, diff, SimularityBitMap, bound = 0;
1415         u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
1416         bool bResult = true;
1417         bool is2T = true;
1418         s32 tmp1 = 0, tmp2 = 0;
1419
1420         if (is2T)
1421                 bound = 8;
1422         else
1423                 bound = 4;
1424
1425         SimularityBitMap = 0;
1426
1427         for (i = 0; i < bound; i++) {
1428
1429                 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
1430                         if ((result[c1][i] & 0x00000200) != 0)
1431                                 tmp1 = result[c1][i] | 0xFFFFFC00;
1432                         else
1433                                 tmp1 = result[c1][i];
1434
1435                         if ((result[c2][i] & 0x00000200) != 0)
1436                                 tmp2 = result[c2][i] | 0xFFFFFC00;
1437                         else
1438                                 tmp2 = result[c2][i];
1439                 } else {
1440                         tmp1 = result[c1][i];
1441                         tmp2 = result[c2][i];
1442                 }
1443
1444                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1445
1446                 if (diff > MAX_TOLERANCE) {
1447                         if ((i == 2 || i == 6) && !SimularityBitMap) {
1448                                 if (result[c1][i]+result[c1][i+1] == 0)
1449                                         final_candidate[(i/4)] = c2;
1450                                 else if (result[c2][i]+result[c2][i+1] == 0)
1451                                         final_candidate[(i/4)] = c1;
1452                                 else
1453                                         SimularityBitMap = SimularityBitMap|(1<<i);
1454                         } else
1455                                 SimularityBitMap = SimularityBitMap|(1<<i);
1456                 }
1457         }
1458
1459         if (SimularityBitMap == 0) {
1460                 for (i = 0; i < (bound/4); i++) {
1461                         if (final_candidate[i] != 0xFF) {
1462                                 for (j = i*4; j < (i+1)*4-2; j++)
1463                                         result[3][j] = result[final_candidate[i]][j];
1464                                 bResult = false;
1465                         }
1466                 }
1467                 return bResult;
1468         } else {
1469
1470                 if (!(SimularityBitMap & 0x03)) { /* path A TX OK */
1471                         for (i = 0; i < 2; i++)
1472                                 result[3][i] = result[c1][i];
1473                 }
1474
1475                 if (!(SimularityBitMap & 0x0c)) { /* path A RX OK */
1476                         for (i = 2; i < 4; i++)
1477                                 result[3][i] = result[c1][i];
1478                 }
1479
1480                 if (!(SimularityBitMap & 0x30)) { /* path B TX OK */
1481                         for (i = 4; i < 6; i++)
1482                                 result[3][i] = result[c1][i];
1483                 }
1484
1485                 if (!(SimularityBitMap & 0xc0)) { /* path B RX OK */
1486                         for (i = 6; i < 8; i++)
1487                                 result[3][i] = result[c1][i];
1488                 }
1489                 return false;
1490         }
1491 }
1492
1493
1494
1495 static void phy_IQCalibrate_8723B(
1496         struct adapter *padapter,
1497         s32 result[][8],
1498         u8 t,
1499         bool is2T,
1500         u8 RF_Path
1501 )
1502 {
1503         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
1504         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1505
1506         u32 i;
1507         u8 PathAOK, PathBOK;
1508         u8 tmp0xc50 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC50, bMaskByte0);
1509         u8 tmp0xc58 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC58, bMaskByte0);
1510         u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
1511                 rFPGA0_XCD_SwitchControl,
1512                 rBlue_Tooth,
1513                 rRx_Wait_CCA,
1514                 rTx_CCK_RFON,
1515                 rTx_CCK_BBON,
1516                 rTx_OFDM_RFON,
1517                 rTx_OFDM_BBON,
1518                 rTx_To_Rx,
1519                 rTx_To_Tx,
1520                 rRx_CCK,
1521                 rRx_OFDM,
1522                 rRx_Wait_RIFS,
1523                 rRx_TO_Rx,
1524                 rStandby,
1525                 rSleep,
1526                 rPMPD_ANAEN
1527         };
1528         u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1529                 REG_TXPAUSE,
1530                 REG_BCN_CTRL,
1531                 REG_BCN_CTRL_1,
1532                 REG_GPIO_MUXCFG
1533         };
1534
1535         /* since 92C & 92D have the different define in IQK_BB_REG */
1536         u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1537                 rOFDM0_TRxPathEnable,
1538                 rOFDM0_TRMuxPar,
1539                 rFPGA0_XCD_RFInterfaceSW,
1540                 rConfig_AntA,
1541                 rConfig_AntB,
1542                 rFPGA0_XAB_RFInterfaceSW,
1543                 rFPGA0_XA_RFInterfaceOE,
1544                 rFPGA0_XB_RFInterfaceOE,
1545                 rCCK0_AFESetting
1546         };
1547         const u32 retryCount = 2;
1548
1549         /*  Note: IQ calibration must be performed after loading */
1550         /*              PHY_REG.txt , and radio_a, radio_b.txt */
1551
1552         /* u32 bbvalue; */
1553
1554         if (t == 0) {
1555 /*               bbvalue = PHY_QueryBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, bMaskDWord); */
1556 /*                      RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E() ==>0x%08x\n", bbvalue)); */
1557
1558                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
1559
1560                 /*  Save ADDA parameters, turn Path A ADDA on */
1561                 _PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1562                 _PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1563                 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1564         }
1565         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
1566
1567         _PHY_PathADDAOn8723B(padapter, ADDA_REG, true, is2T);
1568
1569 /* no serial mode */
1570
1571         /* save RF path for 8723B */
1572 /*      Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
1573 /*      Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */
1574
1575         /* MAC settings */
1576         _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1577
1578         /* BB setting */
1579         /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, BIT24, 0x00); */
1580         PHY_SetBBReg(pDM_Odm->Adapter, rCCK0_AFESetting, 0x0f000000, 0xf);
1581         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
1582         PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
1583         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
1584
1585
1586 /*      PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */
1587 /*      PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */
1588 /*      PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */
1589 /*      PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */
1590
1591
1592 /* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */
1593
1594         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1595         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1596         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
1597         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
1598         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
1599         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
1600         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd);
1601
1602 /* path A TX IQK */
1603         for (i = 0 ; i < retryCount ; i++) {
1604                 PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path);
1605 /*              if (PathAOK == 0x03) { */
1606                 if (PathAOK == 0x01) {
1607                         /*  Path A Tx IQK Success */
1608                         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1609                         pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask);
1610
1611                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
1612                                 result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1613                                 result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1614                         break;
1615                 }
1616         }
1617
1618 /* path A RXIQK */
1619         for (i = 0 ; i < retryCount ; i++) {
1620                 PathAOK = phy_PathA_RxIQK8723B(padapter, is2T, RF_Path);
1621                 if (PathAOK == 0x03) {
1622                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A Rx IQK Success!!\n"));
1623 /*                              result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1624 /*                              result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1625                                 result[t][2] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1626                                 result[t][3] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1627                         break;
1628                 } else {
1629                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));
1630                 }
1631         }
1632
1633         if (0x00 == PathAOK) {
1634                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));
1635         }
1636
1637 /* path B IQK */
1638         if (is2T) {
1639
1640                 /* path B TX IQK */
1641                 for (i = 0 ; i < retryCount ; i++) {
1642                         PathBOK = phy_PathB_IQK_8723B(padapter);
1643                         if (PathBOK == 0x01) {
1644                                 /*  Path B Tx IQK Success */
1645                                 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1646                                 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask);
1647
1648                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n"));
1649                                 result[t][4] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1650                                 result[t][5] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1651                                 break;
1652                         }
1653                 }
1654
1655 /* path B RX IQK */
1656                 for (i = 0 ; i < retryCount ; i++) {
1657                         PathBOK = phy_PathB_RxIQK8723B(padapter, is2T);
1658                         if (PathBOK == 0x03) {
1659                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK Success!!\n"));
1660 /*                              result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1661 /*                              result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1662                                 result[t][6] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1663                                 result[t][7] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1664                                 break;
1665                         } else {
1666                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n"));
1667                         }
1668                 }
1669
1670 /* Allen end */
1671                 if (0x00 == PathBOK) {
1672                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));
1673                 }
1674         }
1675
1676         /* Back to BB mode, load original value */
1677         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));
1678         PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0);
1679
1680         if (t != 0) {
1681                 /*  Reload ADDA power saving parameters */
1682                 _PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1683
1684                 /*  Reload MAC parameters */
1685                 _PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1686
1687                 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1688
1689                 /* Reload RF path */
1690 /*              PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
1691 /*              PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
1692
1693                 /* Allen initial gain 0xc50 */
1694                 /*  Restore RX initial gain */
1695                 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50);
1696                 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50);
1697                 if (is2T) {
1698                         PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, 0x50);
1699                         PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, tmp0xc58);
1700                 }
1701
1702                 /* load 0xe30 IQC default value */
1703                 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1704                 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1705
1706         }
1707         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n"));
1708
1709 }
1710
1711
1712 static void phy_LCCalibrate_8723B(PDM_ODM_T pDM_Odm, bool is2T)
1713 {
1714         u8 tmpReg;
1715         u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;
1716         struct adapter *padapter = pDM_Odm->Adapter;
1717
1718         /* Check continuous TX and Packet TX */
1719         tmpReg = rtw_read8(pDM_Odm->Adapter, 0xd03);
1720
1721         if ((tmpReg&0x70) != 0)                 /* Deal with contisuous TX case */
1722                 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F);       /* disable all continuous TX */
1723         else                                                    /*  Deal with Packet TX case */
1724                 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF);                /*  block all queues */
1725
1726         if ((tmpReg&0x70) != 0) {
1727                 /* 1. Read original RF mode */
1728                 /* Path-A */
1729                 RF_Amode = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_AC, bMask12Bits);
1730
1731                 /* Path-B */
1732                 if (is2T)
1733                         RF_Bmode = PHY_QueryRFReg(padapter, ODM_RF_PATH_B, RF_AC, bMask12Bits);
1734
1735                 /* 2. Set RF mode = standby mode */
1736                 /* Path-A */
1737                 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
1738
1739                 /* Path-B */
1740                 if (is2T)
1741                         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
1742         }
1743
1744         /* 3. Read RF reg18 */
1745         LC_Cal = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);
1746
1747         /* 4. Set LC calibration begin  bit15 */
1748         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /*  LDO ON */
1749         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
1750
1751         mdelay(100);
1752
1753         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /*  LDO OFF */
1754
1755         /*  Channel 10 LC calibration issue for 8723bs with 26M xtal */
1756         if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) {
1757                 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);
1758         }
1759
1760         /* Restore original situation */
1761         if ((tmpReg&0x70) != 0) { /* Deal with contisuous TX case */
1762                 /* Path-A */
1763                 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg);
1764                 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
1765
1766                 /* Path-B */
1767                 if (is2T)
1768                         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
1769         } else /*  Deal with Packet TX case */
1770                 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00);
1771 }
1772
1773 /* Analog Pre-distortion calibration */
1774 #define         APK_BB_REG_NUM  8
1775 #define         APK_CURVE_REG_NUM 4
1776 #define         PATH_NUM                2
1777
1778 #define         DP_BB_REG_NUM           7
1779 #define         DP_RF_REG_NUM           1
1780 #define         DP_RETRY_LIMIT          10
1781 #define         DP_PATH_NUM     2
1782 #define         DP_DPK_NUM                      3
1783 #define         DP_DPK_VALUE_NUM        2
1784
1785
1786
1787 /* IQK version:V2.5    20140123 */
1788 /* IQK is controlled by Is2ant, RF path */
1789 void PHY_IQCalibrate_8723B(
1790         struct adapter *padapter,
1791         bool bReCovery,
1792         bool bRestore,
1793         bool Is2ant,    /* false:1ant, true:2-ant */
1794         u8 RF_Path      /* 0:S1, 1:S0 */
1795 )
1796 {
1797         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
1798
1799         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1800
1801         s32 result[4][8];       /* last is final result */
1802         u8 i, final_candidate, Indexforchannel;
1803         bool bPathAOK, bPathBOK;
1804         s32 RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
1805         bool is12simular, is13simular, is23simular;
1806         bool bSingleTone = false, bCarrierSuppression = false;
1807         u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1808                 rOFDM0_XARxIQImbalance,
1809                 rOFDM0_XBRxIQImbalance,
1810                 rOFDM0_ECCAThreshold,
1811                 rOFDM0_AGCRSSITable,
1812                 rOFDM0_XATxIQImbalance,
1813                 rOFDM0_XBTxIQImbalance,
1814                 rOFDM0_XCTxAFE,
1815                 rOFDM0_XDTxAFE,
1816                 rOFDM0_RxIQExtAnta
1817         };
1818 /*      u32             Path_SEL_BB = 0; */
1819         u32             GNT_BT_default;
1820         u32             StartTime;
1821         s32                     ProgressingTime;
1822
1823         if (ODM_CheckPowerStatus(padapter) == false)
1824                 return;
1825
1826         if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
1827                 return;
1828
1829         /*  20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
1830         if (bSingleTone || bCarrierSuppression)
1831                 return;
1832
1833 #if DISABLE_BB_RF
1834         return;
1835 #endif
1836         if (pDM_Odm->RFCalibrateInfo.bIQKInProgress)
1837                 return;
1838
1839
1840         pDM_Odm->RFCalibrateInfo.bIQKInProgress = true;
1841
1842         if (bRestore) {
1843                 u32 offset, data;
1844                 u8 path, bResult = SUCCESS;
1845                 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1846
1847                 path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? ODM_RF_PATH_A : ODM_RF_PATH_B;
1848
1849                 /*  Restore TX IQK */
1850                 for (i = 0; i < 3; ++i) {
1851                         offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];
1852                         data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];
1853                         if ((offset == 0) || (data == 0)) {
1854                                 DBG_871X(
1855                                         "%s =>path:%s Restore TX IQK result failed\n",
1856                                         __func__,
1857                                         (path == ODM_RF_PATH_A)?"A":"B"
1858                                 );
1859                                 bResult = FAIL;
1860                                 break;
1861                         }
1862                         /* RT_TRACE(_module_mp_, _drv_notice_, ("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data)); */
1863                         PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
1864                 }
1865
1866                 /*  Restore RX IQK */
1867                 for (i = 0; i < 2; ++i) {
1868                         offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];
1869                         data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];
1870                         if ((offset == 0) || (data == 0)) {
1871                                 DBG_871X(
1872                                         "%s =>path:%s  Restore RX IQK result failed\n",
1873                                         __func__,
1874                                         (path == ODM_RF_PATH_A)?"A":"B"
1875                                 );
1876                                 bResult = FAIL;
1877                                 break;
1878                         }
1879                         /* RT_TRACE(_module_mp_, _drv_notice_, ("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data)); */
1880                         PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
1881                 }
1882
1883                 if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] == 0) {
1884                         DBG_871X("%s => Restore Path-A TxLOK result failed\n", __func__);
1885                         bResult = FAIL;
1886                 } else {
1887                         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]);
1888                         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]);
1889                 }
1890
1891                 if (bResult == SUCCESS)
1892                         return;
1893         }
1894
1895         if (bReCovery) {
1896                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n"));
1897                 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1898                 return;
1899         }
1900         StartTime = jiffies;
1901         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK:Start!!!\n"));
1902
1903         /* save default GNT_BT */
1904         GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord);
1905         /*  Save RF Path */
1906 /*      Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
1907 /*      Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */
1908
1909     /* set GNT_BT = 0, pause BT traffic */
1910 /*      PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
1911 /*      PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */
1912
1913
1914         for (i = 0; i < 8; i++) {
1915                 result[0][i] = 0;
1916                 result[1][i] = 0;
1917                 result[2][i] = 0;
1918                 result[3][i] = 0;
1919         }
1920
1921         final_candidate = 0xff;
1922         bPathAOK = false;
1923         bPathBOK = false;
1924         is12simular = false;
1925         is23simular = false;
1926         is13simular = false;
1927
1928
1929         for (i = 0; i < 3; i++) {
1930                 phy_IQCalibrate_8723B(padapter, result, i, Is2ant, RF_Path);
1931
1932                 if (i == 1) {
1933                         is12simular = phy_SimularityCompare_8723B(padapter, result, 0, 1);
1934                         if (is12simular) {
1935                                 final_candidate = 0;
1936                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate));
1937                                 break;
1938                         }
1939                 }
1940
1941                 if (i == 2) {
1942                         is13simular = phy_SimularityCompare_8723B(padapter, result, 0, 2);
1943                         if (is13simular) {
1944                                 final_candidate = 0;
1945                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate));
1946
1947                                 break;
1948                         }
1949
1950                         is23simular = phy_SimularityCompare_8723B(padapter, result, 1, 2);
1951                         if (is23simular) {
1952                                 final_candidate = 1;
1953                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate));
1954                         } else {
1955                                 for (i = 0; i < 8; i++)
1956                                         RegTmp += result[3][i];
1957
1958                                 if (RegTmp != 0)
1959                                         final_candidate = 3;
1960                                 else
1961                                         final_candidate = 0xFF;
1962                         }
1963                 }
1964         }
1965 /*      RT_TRACE(COMP_INIT, DBG_LOUD, ("Release Mutex in IQCalibrate\n")); */
1966
1967         for (i = 0; i < 4; i++) {
1968                 RegE94 = result[i][0];
1969                 RegE9C = result[i][1];
1970                 RegEA4 = result[i][2];
1971                 RegEAC = result[i][3];
1972                 RegEB4 = result[i][4];
1973                 RegEBC = result[i][5];
1974                 RegEC4 = result[i][6];
1975                 RegECC = result[i][7];
1976                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94 =%x RegE9C =%x RegEA4 =%x RegEAC =%x RegEB4 =%x RegEBC =%x RegEC4 =%x RegECC =%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
1977         }
1978
1979         if (final_candidate != 0xff) {
1980                 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
1981                 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
1982                 RegEA4 = result[final_candidate][2];
1983                 RegEAC = result[final_candidate][3];
1984                 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];
1985                 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];
1986                 RegEC4 = result[final_candidate][6];
1987                 RegECC = result[final_candidate][7];
1988                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: final_candidate is %x\n", final_candidate));
1989                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: RegE94 =%x RegE9C =%x RegEA4 =%x RegEAC =%x RegEB4 =%x RegEBC =%x RegEC4 =%x RegECC =%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
1990                 bPathAOK = bPathBOK = true;
1991         } else {
1992                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: FAIL use default value\n"));
1993
1994                 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100;      /* X default value */
1995                 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0;                /* Y default value */
1996         }
1997
1998         {
1999                 if (RegE94 != 0)
2000                         _PHY_PathAFillIQKMatrix8723B(padapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
2001         }
2002         {
2003                 if (RegEB4 != 0)
2004                         _PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
2005         }
2006
2007         Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
2008
2009 /* To Fix BSOD when final_candidate is 0xff */
2010 /* by sherry 20120321 */
2011         if (final_candidate < 4) {
2012                 for (i = 0; i < IQK_Matrix_REG_NUM; i++)
2013                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];
2014                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = true;
2015         }
2016         /* RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); */
2017         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
2018
2019         _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
2020
2021         /* restore GNT_BT */
2022         PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default);
2023         /*  Restore RF Path */
2024 /*      PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
2025 /*      PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
2026
2027         /* Resotr RX mode table parameter */
2028         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
2029         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
2030         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
2031         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177);
2032         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
2033         PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd);
2034
2035         /* set GNT_BT = HW control */
2036 /*      PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
2037 /*      PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */
2038
2039         if (Is2ant) {
2040                 if (RF_Path == 0x0)     /* S1 */
2041                         ODM_SetIQCbyRFpath(pDM_Odm, 0);
2042                 else    /* S0 */
2043                         ODM_SetIQCbyRFpath(pDM_Odm, 1);
2044         }
2045
2046         pDM_Odm->RFCalibrateInfo.bIQKInProgress = false;
2047
2048         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK finished\n"));
2049         ProgressingTime = jiffies_to_msecs(jiffies - StartTime);
2050         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK ProgressingTime = %d\n", ProgressingTime));
2051
2052
2053 }
2054
2055
2056 void PHY_LCCalibrate_8723B(PDM_ODM_T pDM_Odm)
2057 {
2058         bool            bSingleTone = false, bCarrierSuppression = false;
2059         u32             timeout = 2000, timecount = 0;
2060         u32             StartTime;
2061         s32                     ProgressingTime;
2062
2063 #if DISABLE_BB_RF
2064         return;
2065 #endif
2066
2067         if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
2068                 return;
2069
2070         /*  20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
2071         if (bSingleTone || bCarrierSuppression)
2072                 return;
2073
2074         StartTime = jiffies;
2075         while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) {
2076                 mdelay(50);
2077                 timecount += 50;
2078         }
2079
2080         pDM_Odm->RFCalibrateInfo.bLCKInProgress = true;
2081
2082
2083         phy_LCCalibrate_8723B(pDM_Odm, false);
2084
2085
2086         pDM_Odm->RFCalibrateInfo.bLCKInProgress = false;
2087
2088         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));
2089         ProgressingTime = jiffies_to_msecs(jiffies - StartTime);
2090         ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("LCK ProgressingTime = %d\n", ProgressingTime));
2091 }