drivers/staging/meilhaus/me4600_ai.c

   1 /**
   2  * @file me4600_ai.c
   3  *
   4  * @brief ME-4000 analog input subdevice instance.
   5  * @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
   6  * @author Guenter Gebhardt
   7  * @author Krzysztof Gantzke    (k.gantzke@meilhaus.de)
   8  */
   9
  10 /*
  11  * Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
  12  *
  13  * This file is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #ifndef __KERNEL__
  29 # define __KERNEL__
  30 #endif
  31
  32 /*
  33  * Includes
  34  */
  35 #include <linux/module.h>
  36
  37 #include <linux/slab.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/io.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/types.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/delay.h>
  44
  45 #include "medefines.h"
  46 #include "meinternal.h"
  47 #include "meerror.h"
  48 #include "medebug.h"
  49 #include "meids.h"
  50
  51 #include "me4600_reg.h"
  52 #include "me4600_ai_reg.h"
  53 #include "me4600_ai.h"
  54
  55 /*
  56  * Declarations (local)
  57  */
  58
  59 static void me4600_ai_destructor(struct me_subdevice *subdevice);
  60 static int me4600_ai_io_reset_subdevice(me_subdevice_t *subdevice,
  61                                         struct file *filep, int flags);
  62
  63 static int me4600_ai_io_single_config(me_subdevice_t *subdevice,
  64                                       struct file *filep,
  65                                       int channel,
  66                                       int single_config,
  67                                       int ref,
  68                                       int trig_chan,
  69                                       int trig_type, int trig_edge, int flags);
  70
  71 static int me4600_ai_io_single_read(me_subdevice_t *subdevice,
  72                                     struct file *filep,
  73                                     int channel,
  74                                     int *value, int time_out, int flags);
  75
  76 static int me4600_ai_io_stream_config(me_subdevice_t *subdevice,
  77                                       struct file *filep,
  78                                       meIOStreamConfig_t *config_list,
  79                                       int count,
  80                                       meIOStreamTrigger_t *trigger,
  81                                       int fifo_irq_threshold, int flags);
  82 static int me4600_ai_io_stream_read(me_subdevice_t *subdevice,
  83                                     struct file *filep,
  84                                     int read_mode,
  85                                     int *values, int *count, int flags);
  86 static int me4600_ai_io_stream_new_values(me_subdevice_t *subdevice,
  87                                           struct file *filep,
  88                                           int time_out, int *count, int flags);
  89 static inline int me4600_ai_io_stream_read_get_value(me4600_ai_subdevice_t *
  90                                                      instance, int *values,
  91                                                      const int count,
  92                                                      const int flags);
  93
  94 static int me4600_ai_io_stream_start(me_subdevice_t *subdevice,
  95                                      struct file *filep,
  96                                      int start_mode, int time_out, int flags);
  97 static int me4600_ai_io_stream_stop(me_subdevice_t *subdevice,
  98                                     struct file *filep,
  99                                     int stop_mode, int flags);
 100 static int me4600_ai_io_stream_status(me_subdevice_t *subdevice,
 101                                       struct file *filep,
 102                                       int wait,
 103                                       int *status, int *values, int flags);
 104
 105 static int me4600_ai_query_range_by_min_max(me_subdevice_t *subdevice,
 106                                             int unit,
 107                                             int *min,
 108                                             int *max, int *maxdata, int *range);
 109 static int me4600_ai_query_number_ranges(me_subdevice_t *subdevice,
 110                                          int unit, int *count);
 111 static int me4600_ai_query_range_info(me_subdevice_t *subdevice,
 112                                       int range,
 113                                       int *unit,
 114                                       int *min, int *max, int *maxdata);
 115 static int me4600_ai_query_timer(me_subdevice_t *subdevice,
 116                                  int timer,
 117                                  int *base_frequency,
 118                                  long long *min_ticks, long long *max_ticks);
 119 static int me4600_ai_query_number_channels(me_subdevice_t *subdevice,
 120                                            int *number);
 121 static int me4600_ai_query_subdevice_type(me_subdevice_t *subdevice,
 122                                           int *type, int *subtype);
 123 static int me4600_ai_query_subdevice_caps(me_subdevice_t *subdevice,
 124                                           int *caps);
 125 static int me4600_ai_query_subdevice_caps_args(struct me_subdevice *subdevice,
 126                                                int cap, int *args, int count);
 127
 128 static irqreturn_t me4600_ai_isr(int irq, void *dev_id);
 129
 130 static int ai_mux_toggler(me4600_ai_subdevice_t *subdevice);
 131
 132 /** Immidiate stop.
 133 * Reset all IRQ's sources. (block laches)
 134 * Preserve FIFO
 135 */
 136 static int ai_stop_immediately(me4600_ai_subdevice_t *instance);
 137
 138 /** Immidiate stop.
 139 * Reset all IRQ's sources. (block laches)
 140 * Reset data FIFO
 141 */
 142 inline void ai_stop_isr(me4600_ai_subdevice_t *instance);
 143
 144 /** Interrupt logics.
 145 * Read datas
 146 * Reset latches
 147 */
 148 void ai_limited_isr(me4600_ai_subdevice_t *instance, const uint32_t irq_status,
 149                     const uint32_t ctrl_status);
 150 void ai_infinite_isr(me4600_ai_subdevice_t *instance,
 151                      const uint32_t irq_status, const uint32_t ctrl_status);
 152
 153 /** Last chunck of datas. We must reschedule sample counter.
 154 * Leaving SC_RELOAD doesn't do any harm, but in some bad case can make extra interrupts.
 155 * When threshold is wrongly set some IRQ are lost.(!!!)
 156 */
 157 inline void ai_reschedule_SC(me4600_ai_subdevice_t *instance);
 158
 159 /** Read datas from FIFO and copy them to buffer */
 160 static inline int ai_read_data(me4600_ai_subdevice_t *instance,
 161                                const int count);
 162
 163 /** Copy rest of data from fifo to circular buffer.*/
 164 static inline int ai_read_data_pooling(me4600_ai_subdevice_t *instance);
 165
 166 /** Set ISM to next state for infinite data aqusation mode*/
 167 inline void ai_infinite_ISM(me4600_ai_subdevice_t *instance);
 168
 169 /** Set ISM to next state for define amount of data aqusation mode*/
 170 inline void ai_limited_ISM(me4600_ai_subdevice_t *instance,
 171                            uint32_t irq_status);
 172
 173 /** Set ISM to next stage for limited mode */
 174 inline void ai_data_acquisition_logic(me4600_ai_subdevice_t *instance);
 175
 176 static void me4600_ai_work_control_task(struct work_struct *work);
 177
 178 /* Definitions
 179  */
 180
 181 me4600_ai_subdevice_t *me4600_ai_constructor(uint32_t reg_base,
 182                                              unsigned int channels,
 183                                              unsigned int ranges,
 184                                              int isolated,
 185                                              int sh,
 186                                              int irq,
 187                                              spinlock_t *ctrl_reg_lock,
 188                                              struct workqueue_struct *me4600_wq)
 189 {
 190         me4600_ai_subdevice_t *subdevice;
 191         int err;
 192         unsigned int i;
 193
 194         PDEBUG("executed. idx=0\n");
 195
 196         // Allocate memory for subdevice instance.
 197         subdevice = kmalloc(sizeof(me4600_ai_subdevice_t), GFP_KERNEL);
 198
 199         if (!subdevice) {
 200                 PERROR("Cannot get memory for subdevice instance.\n");
 201                 return NULL;
 202         }
 203
 204         memset(subdevice, 0, sizeof(me4600_ai_subdevice_t));
 205
 206         // Initialize subdevice base class.
 207         err = me_subdevice_init(&subdevice->base);
 208
 209         if (err) {
 210                 PERROR("Cannot initialize subdevice base class instance.\n");
 211                 kfree(subdevice);
 212                 return NULL;
 213         }
 214         // Initialize spin locks.
 215         spin_lock_init(&subdevice->subdevice_lock);
 216
 217         subdevice->ctrl_reg_lock = ctrl_reg_lock;
 218
 219         // Initialize circular buffer.
 220         subdevice->circ_buf.mask = ME4600_AI_CIRC_BUF_COUNT - 1;
 221
 222         subdevice->circ_buf.buf =
 223             (void *)__get_free_pages(GFP_KERNEL, ME4600_AI_CIRC_BUF_SIZE_ORDER);
 224         PDEBUG("circ_buf = %p size=%ld\n", subdevice->circ_buf.buf,
 225                ME4600_AI_CIRC_BUF_SIZE);
 226
 227         if (!subdevice->circ_buf.buf) {
 228                 PERROR("Cannot get circular buffer.\n");
 229                 me_subdevice_deinit((me_subdevice_t *) subdevice);
 230                 kfree(subdevice);
 231                 return NULL;
 232         }
 233
 234         memset(subdevice->circ_buf.buf, 0, ME4600_AI_CIRC_BUF_SIZE);
 235         subdevice->circ_buf.head = 0;
 236         subdevice->circ_buf.tail = 0;
 237         subdevice->status = ai_status_none;
 238
 239         // Initialize wait queue.
 240         init_waitqueue_head(&subdevice->wait_queue);
 241
 242         // Save the number of channels.
 243         subdevice->channels = channels;
 244
 245         /* Initialize the single config entries to reset values */
 246         for (i = 0; i < channels; i++) {
 247                 subdevice->single_config[i].status = ME_SINGLE_CHANNEL_NOT_CONFIGURED;  //not configured
 248         }
 249
 250         // Save if isolated device.
 251         subdevice->isolated = isolated;
 252
 253         // Save if sample and hold is available.
 254         subdevice->sh = sh;
 255
 256         // Set stream config to not configured state.
 257         subdevice->fifo_irq_threshold = 0;
 258         subdevice->data_required = 0;
 259         subdevice->chan_list_len = 0;
 260
 261         // Initialize registers addresses.
 262         subdevice->ctrl_reg = reg_base + ME4600_AI_CTRL_REG;
 263         subdevice->status_reg = reg_base + ME4600_AI_STATUS_REG;
 264         subdevice->channel_list_reg = reg_base + ME4600_AI_CHANNEL_LIST_REG;
 265         subdevice->data_reg = reg_base + ME4600_AI_DATA_REG;
 266         subdevice->chan_timer_reg = reg_base + ME4600_AI_CHAN_TIMER_REG;
 267         subdevice->chan_pre_timer_reg = reg_base + ME4600_AI_CHAN_PRE_TIMER_REG;
 268         subdevice->scan_timer_low_reg = reg_base + ME4600_AI_SCAN_TIMER_LOW_REG;
 269         subdevice->scan_timer_high_reg =
 270             reg_base + ME4600_AI_SCAN_TIMER_HIGH_REG;
 271         subdevice->scan_pre_timer_low_reg =
 272             reg_base + ME4600_AI_SCAN_PRE_TIMER_LOW_REG;
 273         subdevice->scan_pre_timer_high_reg =
 274             reg_base + ME4600_AI_SCAN_PRE_TIMER_HIGH_REG;
 275         subdevice->start_reg = reg_base + ME4600_AI_START_REG;
 276         subdevice->irq_status_reg = reg_base + ME4600_IRQ_STATUS_REG;
 277         subdevice->sample_counter_reg = reg_base + ME4600_AI_SAMPLE_COUNTER_REG;
 278 #ifdef MEDEBUG_DEBUG_REG
 279         subdevice->reg_base = reg_base;
 280 #endif
 281
 282         // Initialize ranges.
 283         subdevice->ranges_len = ranges;
 284         subdevice->ranges[0].min = -10E6;
 285         subdevice->ranges[0].max = 9999694;
 286
 287         subdevice->ranges[1].min = 0;
 288         subdevice->ranges[1].max = 9999847;
 289
 290         subdevice->ranges[2].min = -25E5;
 291         subdevice->ranges[2].max = 2499923;
 292
 293         subdevice->ranges[3].min = 0;
 294         subdevice->ranges[3].max = 2499961;
 295
 296         // We have to switch the mux in order to get it work correctly.
 297         ai_mux_toggler(subdevice);
 298
 299         // Register interrupt service routine.
 300         subdevice->irq = irq;
 301         if (request_irq(subdevice->irq, me4600_ai_isr,
 302                         IRQF_DISABLED | IRQF_SHARED,
 303                         ME4600_NAME, subdevice)) {
 304                 PERROR("Cannot register interrupt service routine.\n");
 305                 me_subdevice_deinit((me_subdevice_t *) subdevice);
 306                 free_pages((unsigned long)subdevice->circ_buf.buf,
 307                            ME4600_AI_CIRC_BUF_SIZE_ORDER);
 308                 subdevice->circ_buf.buf = NULL;
 309                 kfree(subdevice);
 310                 return NULL;
 311         }
 312         PINFO("Registered irq=%d.\n", subdevice->irq);
 313
 314         // Override base class methods.
 315         subdevice->base.me_subdevice_destructor = me4600_ai_destructor;
 316         subdevice->base.me_subdevice_io_reset_subdevice =
 317             me4600_ai_io_reset_subdevice;
 318         subdevice->base.me_subdevice_io_single_config =
 319             me4600_ai_io_single_config;
 320         subdevice->base.me_subdevice_io_single_read = me4600_ai_io_single_read;
 321         subdevice->base.me_subdevice_io_stream_config =
 322             me4600_ai_io_stream_config;
 323         subdevice->base.me_subdevice_io_stream_new_values =
 324             me4600_ai_io_stream_new_values;
 325         subdevice->base.me_subdevice_io_stream_read = me4600_ai_io_stream_read;
 326         subdevice->base.me_subdevice_io_stream_start =
 327             me4600_ai_io_stream_start;
 328         subdevice->base.me_subdevice_io_stream_status =
 329             me4600_ai_io_stream_status;
 330         subdevice->base.me_subdevice_io_stream_stop = me4600_ai_io_stream_stop;
 331         subdevice->base.me_subdevice_query_number_channels =
 332             me4600_ai_query_number_channels;
 333         subdevice->base.me_subdevice_query_subdevice_type =
 334             me4600_ai_query_subdevice_type;
 335         subdevice->base.me_subdevice_query_subdevice_caps =
 336             me4600_ai_query_subdevice_caps;
 337         subdevice->base.me_subdevice_query_subdevice_caps_args =
 338             me4600_ai_query_subdevice_caps_args;
 339         subdevice->base.me_subdevice_query_range_by_min_max =
 340             me4600_ai_query_range_by_min_max;
 341         subdevice->base.me_subdevice_query_number_ranges =
 342             me4600_ai_query_number_ranges;
 343         subdevice->base.me_subdevice_query_range_info =
 344             me4600_ai_query_range_info;
 345         subdevice->base.me_subdevice_query_timer = me4600_ai_query_timer;
 346
 347         // Prepare work queue.
 348         subdevice->me4600_workqueue = me4600_wq;
 349
 350 /* workqueue API changed in kernel 2.6.20 */
 351         INIT_DELAYED_WORK(&subdevice->ai_control_task,
 352                           me4600_ai_work_control_task);
 353
 354         return subdevice;
 355 }
 356
 357 static void me4600_ai_destructor(struct me_subdevice *subdevice)
 358 {
 359         me4600_ai_subdevice_t *instance;
 360
 361         instance = (me4600_ai_subdevice_t *) subdevice;
 362
 363         PDEBUG("executed. idx=0\n");
 364
 365         instance->ai_control_task_flag = 0;
 366         // Reset subdevice to asure clean exit.
 367         me4600_ai_io_reset_subdevice(subdevice, NULL,
 368                                      ME_IO_RESET_SUBDEVICE_NO_FLAGS);
 369
 370         // Remove any tasks from work queue. This is paranoic because it was done allready in reset().
 371         if (!cancel_delayed_work(&instance->ai_control_task)) { //Wait 2 ticks to be sure that control task is removed from queue.
 372                 set_current_state(TASK_INTERRUPTIBLE);
 373                 schedule_timeout(2);
 374         }
 375
 376         free_irq(instance->irq, instance);
 377         free_pages((unsigned long)instance->circ_buf.buf,
 378                    ME4600_AI_CIRC_BUF_SIZE_ORDER);
 379         me_subdevice_deinit(&instance->base);
 380         kfree(instance);
 381 }
 382
 383 static int me4600_ai_io_reset_subdevice(me_subdevice_t *subdevice,
 384                                         struct file *filep, int flags)
 385 {
 386         me4600_ai_subdevice_t *instance;
 387         int err = ME_ERRNO_SUCCESS;
 388         volatile uint32_t ctrl;
 389         unsigned long status;
 390         const int timeout = HZ / 10;    //100ms
 391         int i;
 392
 393         PDEBUG("executed. idx=0\n");
 394
 395         if (flags) {
 396                 PERROR("Invalid flag specified.\n");
 397                 return ME_ERRNO_INVALID_FLAGS;
 398         }
 399
 400         instance = (me4600_ai_subdevice_t *) subdevice;
 401
 402         ME_SUBDEVICE_ENTER;
 403
 404         instance->ai_control_task_flag = 0;
 405         instance->status = ai_status_none;
 406
 407         for (i = 0; i <= timeout; i++) {
 408                 spin_lock_irqsave(instance->ctrl_reg_lock, status);
 409                 ctrl = inl(instance->ctrl_reg);
 410                 //Stop DMA
 411                 ctrl &= ~ME4600_AI_CTRL_RPCI_FIFO;
 412                 // Stop all actions. No conditions!
 413                 ctrl &= ~ME4600_AI_CTRL_BIT_STOP;
 414                 ctrl |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
 415
 416                 outl(ctrl, instance->ctrl_reg);
 417                 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
 418                            instance->reg_base,
 419                            instance->ctrl_reg - instance->reg_base, ctrl);
 420                 spin_unlock_irqrestore(instance->ctrl_reg_lock, status);
 421
 422                 if (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM))
 423                         break;
 424
 425                 set_current_state(TASK_INTERRUPTIBLE);
 426                 schedule_timeout(1);
 427         }
 428
 429         if (i > timeout) {
 430                 PERROR("FSM is still busy.\n");
 431                 ME_SUBDEVICE_EXIT;
 432                 return ME_ERRNO_INTERNAL;
 433         }
 434
 435         spin_lock_irqsave(instance->ctrl_reg_lock, status);
 436         ctrl = inl(instance->ctrl_reg);
 437         // Clear all features. Dissable interrupts.
 438         ctrl &= ~(ME4600_AI_CTRL_BIT_STOP
 439                   | ME4600_AI_CTRL_BIT_LE_IRQ
 440                   | ME4600_AI_CTRL_BIT_HF_IRQ | ME4600_AI_CTRL_BIT_SC_IRQ);
 441         ctrl |= (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP
 442                  | ME4600_AI_CTRL_BIT_LE_IRQ_RESET
 443                  | ME4600_AI_CTRL_BIT_HF_IRQ_RESET
 444                  | ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
 445
 446         outl(ctrl, instance->ctrl_reg);
 447         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 448                    instance->ctrl_reg - instance->reg_base, ctrl);
 449         spin_unlock_irqrestore(instance->ctrl_reg_lock, status);
 450
 451         outl(ME4600_AI_MIN_CHAN_TICKS - 1, instance->chan_timer_reg);
 452         PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%llx\n",
 453                    instance->reg_base,
 454                    instance->chan_timer_reg - instance->reg_base,
 455                    ME4600_AI_MIN_CHAN_TICKS);
 456         outl(ME4600_AI_MIN_ACQ_TICKS - 1, instance->chan_pre_timer_reg);
 457         PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%llx\n",
 458                    instance->reg_base,
 459                    instance->chan_pre_timer_reg - instance->reg_base,
 460                    ME4600_AI_MIN_ACQ_TICKS);
 461         outl(0, instance->scan_timer_low_reg);
 462         PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
 463                    instance->reg_base,
 464                    instance->scan_timer_low_reg - instance->reg_base, 0);
 465         outl(0, instance->scan_timer_high_reg);
 466         PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
 467                    instance->reg_base,
 468                    instance->scan_timer_high_reg - instance->reg_base, 0);
 469         outl(0, instance->scan_pre_timer_low_reg);
 470         PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
 471                    instance->reg_base,
 472                    instance->scan_pre_timer_low_reg - instance->reg_base, 0);
 473         outl(0, instance->scan_pre_timer_high_reg);
 474         PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
 475                    instance->reg_base,
 476                    instance->scan_pre_timer_high_reg - instance->reg_base, 0);
 477         outl(0xEFFFFFFF, instance->sample_counter_reg);
 478         PDEBUG_REG("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
 479                    instance->reg_base,
 480                    instance->sample_counter_reg - instance->reg_base,
 481                    0xEFFFFFFF);
 482
 483         instance->circ_buf.head = 0;
 484         instance->circ_buf.tail = 0;
 485
 486         instance->fifo_irq_threshold = 0;
 487         instance->data_required = 0;
 488         instance->chan_list_len = 0;
 489
 490         // Initialize the single config entries to reset values.
 491         for (i = 0; i < instance->channels; i++) {
 492                 instance->single_config[i].status =
 493                     ME_SINGLE_CHANNEL_NOT_CONFIGURED;
 494         }
 495         instance->status = ai_status_none;
 496
 497         //Signal reset if user is on wait.
 498         wake_up_interruptible_all(&instance->wait_queue);
 499
 500         ME_SUBDEVICE_EXIT;
 501
 502         return err;
 503 }
 504
 505 static int me4600_ai_io_single_config(me_subdevice_t *subdevice,
 506                                       struct file *filep,
 507                                       int channel,
 508                                       int single_config,
 509                                       int ref,
 510                                       int trig_chan,
 511                                       int trig_type, int trig_edge, int flags)
 512 {
 513         me4600_ai_subdevice_t *instance;
 514         int err = ME_ERRNO_SUCCESS;
 515         unsigned long cpu_flags;
 516         int i;
 517
 518         instance = (me4600_ai_subdevice_t *) subdevice;
 519
 520         PDEBUG("executed. idx=0\n");
 521
 522         if (flags & ~ME_IO_SINGLE_CONFIG_CONTINUE) {
 523                 PERROR("Invalid flag specified.\n");
 524                 return ME_ERRNO_INVALID_FLAGS;
 525         }
 526
 527         switch (trig_type) {
 528         case ME_TRIG_TYPE_SW:
 529                 if (trig_edge != ME_TRIG_EDGE_NONE) {
 530                         PERROR
 531                             ("Invalid trigger edge. Software trigger has not edge.\n");
 532                         return ME_ERRNO_INVALID_TRIG_EDGE;
 533                 }
 534                 break;
 535
 536         case ME_TRIG_TYPE_EXT_ANALOG:
 537                 if (instance->channels <= 16)   //Only versions with 32 channels have analog trigger (4670 and 4680)
 538                 {
 539                         PERROR("Invalid trigger type specified.\n");
 540                         return ME_ERRNO_INVALID_TRIG_TYPE;
 541                 }
 542
 543         case ME_TRIG_TYPE_EXT_DIGITAL:
 544                 if ((trig_edge != ME_TRIG_EDGE_ANY)
 545                     && (trig_edge != ME_TRIG_EDGE_RISING)
 546                     && (trig_edge != ME_TRIG_EDGE_FALLING)) {
 547                         PERROR("Invalid trigger edge specified.\n");
 548                         return ME_ERRNO_INVALID_TRIG_EDGE;
 549                 }
 550                 break;
 551
 552         default:
 553                 PERROR("Invalid trigger type specified.\n");
 554                 return ME_ERRNO_INVALID_TRIG_TYPE;
 555         }
 556
 557         if (trig_chan != ME_TRIG_CHAN_DEFAULT) {
 558                 PERROR("Invalid trigger channel specified.\n");
 559                 return ME_ERRNO_INVALID_TRIG_CHAN;
 560         }
 561
 562         if ((single_config < 0) || (single_config >= instance->ranges_len)) {
 563                 PERROR("Invalid single config specified.\n");
 564                 return ME_ERRNO_INVALID_SINGLE_CONFIG;
 565         }
 566
 567         if ((ref != ME_REF_AI_GROUND) && (ref != ME_REF_AI_DIFFERENTIAL)) {
 568                 PERROR("Invalid analog reference specified.\n");
 569                 return ME_ERRNO_INVALID_REF;
 570         }
 571
 572         if ((single_config % 2) && (ref != ME_REF_AI_GROUND)) {
 573                 PERROR("Invalid analog reference specified.\n");
 574                 return ME_ERRNO_INVALID_REF;
 575         }
 576
 577         if ((ref == ME_REF_AI_DIFFERENTIAL)
 578             && ((instance->channels == 16) || (channel >= 16))) {
 579                 PERROR("Invalid analog reference specified.\n");
 580                 return ME_ERRNO_INVALID_REF;
 581         }
 582
 583         if (channel < 0) {
 584                 PERROR("Invalid channel number specified.\n");
 585                 return ME_ERRNO_INVALID_CHANNEL;
 586         }
 587
 588         if (channel >= instance->channels) {
 589                 PERROR("Invalid channel number specified.\n");
 590                 return ME_ERRNO_INVALID_CHANNEL;
 591         }
 592
 593         ME_SUBDEVICE_ENTER;
 594
 595         spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
 596         //Prepare data entry.
 597         // Common for all modes.
 598         instance->single_config[channel].entry =
 599             channel | ME4600_AI_LIST_LAST_ENTRY;
 600
 601         if (ref == ME_REF_AI_DIFFERENTIAL) {    // ME_REF_AI_DIFFERENTIAL
 602                 instance->single_config[channel].entry |=
 603                     ME4600_AI_LIST_INPUT_DIFFERENTIAL;
 604         }
 605 /*
 606                 // ME4600_AI_LIST_INPUT_SINGLE_ENDED = 0x0000
 607                 // 'entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED' <== Do nothing. Removed.
 608                 else
 609                 {// ME_REF_AI_GROUND
 610                         instance->single_config[channel].entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED;
 611                 }
 612 */
 613         switch (single_config) {
 614         case 0:         //-10V..10V
 615 /*
 616                                         // ME4600_AI_LIST_RANGE_BIPOLAR_10 = 0x0000
 617                                         // 'entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10' <== Do nothing. Removed.
 618                                         instance->single_config[channel].entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10;
 619 */ break;
 620
 621         case 1:         //0V..10V
 622                 instance->single_config[channel].entry |=
 623                     ME4600_AI_LIST_RANGE_UNIPOLAR_10;
 624                 break;
 625
 626         case 2:         //-2.5V..2.5V
 627                 instance->single_config[channel].entry |=
 628                     ME4600_AI_LIST_RANGE_BIPOLAR_2_5;
 629                 break;
 630
 631         case 3:         //0V..2.5V
 632                 instance->single_config[channel].entry |=
 633                     ME4600_AI_LIST_RANGE_UNIPOLAR_2_5;
 634                 break;
 635         }
 636
 637         // Prepare control register.
 638         // Common for all modes.
 639         instance->single_config[channel].ctrl =
 640             ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
 641
 642         switch (trig_type) {
 643         case ME_TRIG_TYPE_SW:
 644                 // Nothing to set.
 645                 break;
 646
 647         case ME_TRIG_TYPE_EXT_ANALOG:
 648                 instance->single_config[channel].ctrl |=
 649                     ME4600_AI_CTRL_BIT_EX_TRIG_ANALOG;
 650
 651         case ME_TRIG_TYPE_EXT_DIGITAL:
 652                 instance->single_config[channel].ctrl |=
 653                     ME4600_AI_CTRL_BIT_EX_TRIG;
 654                 break;
 655         }
 656
 657         switch (trig_edge) {
 658         case ME_TRIG_EDGE_RISING:
 659                 // Nothing to set.
 660                 break;
 661
 662         case ME_TRIG_EDGE_ANY:
 663                 instance->single_config[channel].ctrl |=
 664                     ME4600_AI_CTRL_BIT_EX_TRIG_BOTH;
 665
 666         case ME_TRIG_EDGE_FALLING:
 667                 instance->single_config[channel].ctrl |=
 668                     ME4600_AI_CTRL_BIT_EX_TRIG_FALLING;
 669                 break;
 670         }
 671
 672         // Enable this channel
 673         instance->single_config[channel].status = ME_SINGLE_CHANNEL_CONFIGURED;
 674
 675         // Copy this settings to other outputs.
 676         if (flags == ME_IO_SINGLE_CONFIG_CONTINUE) {
 677                 for (i = channel + 1; i < instance->channels; i++) {
 678                         instance->single_config[i].ctrl =
 679                             instance->single_config[channel].ctrl;
 680                         instance->single_config[i].entry =
 681                             instance->single_config[channel].entry;
 682                         instance->single_config[i].status =
 683                             ME_SINGLE_CHANNEL_CONFIGURED;
 684                 }
 685         }
 686
 687         instance->status = ai_status_single_configured;
 688         spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
 689
 690         ME_SUBDEVICE_EXIT;
 691
 692         return err;
 693 }
 694
 695 static int me4600_ai_io_single_read(me_subdevice_t *subdevice,
 696                                     struct file *filep,
 697                                     int channel,
 698                                     int *value, int time_out, int flags)
 699 {
 700         me4600_ai_subdevice_t *instance;
 701         volatile uint32_t tmp;
 702         volatile uint32_t val;
 703         unsigned long cpu_flags;
 704         int err = ME_ERRNO_SUCCESS;
 705
 706         unsigned long j;
 707         unsigned long delay = 0;
 708
 709         PDEBUG("executed. idx=0\n");
 710
 711         instance = (me4600_ai_subdevice_t *) subdevice;
 712
 713         if (flags) {
 714                 PERROR("Invalid flag specified.\n");
 715                 return ME_ERRNO_INVALID_FLAGS;
 716         }
 717
 718         if (instance->status != ai_status_single_configured) {
 719                 PERROR("Subdevice not configured to work in single mode!\n");
 720                 return ME_ERRNO_PREVIOUS_CONFIG;
 721         }
 722
 723         if ((channel > instance->channels) || (channel < 0)) {
 724                 PERROR("Invalid channel specified.\n");
 725                 return ME_ERRNO_INVALID_CHANNEL;
 726         }
 727
 728         if (time_out < 0) {
 729                 PERROR("Invalid timeout specified.\n");
 730                 return ME_ERRNO_INVALID_TIMEOUT;
 731         }
 732
 733         if (instance->single_config[channel].status !=
 734             ME_SINGLE_CHANNEL_CONFIGURED) {
 735                 PERROR("Channel is not configured to work in single mode!\n");
 736                 return ME_ERRNO_PREVIOUS_CONFIG;
 737         }
 738
 739         if (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) {
 740                 PERROR("Subdevice is busy.\n");
 741                 return ME_ERRNO_SUBDEVICE_BUSY;
 742         }
 743
 744         ME_SUBDEVICE_ENTER;
 745
 746         // Cancel control task
 747         PDEBUG("Cancel control task.\n");
 748         instance->ai_control_task_flag = 0;
 749         cancel_delayed_work(&instance->ai_control_task);
 750
 751         if (time_out) {
 752                 delay = (time_out * HZ) / 1000;
 753
 754                 if (delay == 0)
 755                         delay = 1;
 756         }
 757
 758         spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
 759
 760         // Mark that StreamConfig is removed.
 761         instance->chan_list_len = 0;
 762
 763         spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
 764         /// @note Imprtant: Preserve EXT IRQ settings.
 765         tmp = inl(instance->ctrl_reg);
 766         // Clear FIFOs and dissable interrupts
 767         tmp &=
 768             ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
 769
 770         tmp &=
 771             ~(ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_HF_IRQ |
 772               ME4600_AI_CTRL_BIT_LE_IRQ);
 773         tmp |=
 774             ME4600_AI_CTRL_BIT_SC_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
 775             ME4600_AI_CTRL_BIT_LE_IRQ_RESET;
 776
 777         tmp |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
 778         outl(tmp, instance->ctrl_reg);
 779         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 780                    instance->ctrl_reg - instance->reg_base, tmp);
 781
 782         outl(0, instance->scan_pre_timer_low_reg);
 783         PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
 784                    instance->reg_base,
 785                    instance->scan_pre_timer_low_reg - instance->reg_base, 0);
 786         outl(0, instance->scan_pre_timer_high_reg);
 787         PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
 788                    instance->reg_base,
 789                    instance->scan_pre_timer_high_reg - instance->reg_base, 0);
 790         outl(0, instance->scan_timer_low_reg);
 791         PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
 792                    instance->reg_base,
 793                    instance->scan_timer_low_reg - instance->reg_base, 0);
 794         outl(0, instance->scan_timer_high_reg);
 795         PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
 796                    instance->reg_base,
 797                    instance->scan_timer_high_reg - instance->reg_base, 0);
 798         outl(65, instance->chan_timer_reg);
 799         PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
 800                    instance->reg_base,
 801                    instance->chan_timer_reg - instance->reg_base, 65);
 802         outl(65, instance->chan_pre_timer_reg);
 803         PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
 804                    instance->reg_base,
 805                    instance->chan_pre_timer_reg - instance->reg_base, 65);
 806
 807         //Reactive FIFOs. Enable work.
 808         tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
 809         outl(tmp, instance->ctrl_reg);
 810         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 811                    instance->ctrl_reg - instance->reg_base, tmp);
 812
 813         outl(instance->single_config[channel].entry,
 814              instance->channel_list_reg);
 815         PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
 816                    instance->reg_base,
 817                    instance->channel_list_reg - instance->reg_base,
 818                    instance->single_config[channel].entry);
 819
 820         // Preserve EXT IRQ settings.
 821         tmp &= (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET);
 822         outl(instance->single_config[channel].ctrl | tmp, instance->ctrl_reg);
 823         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 824                    instance->ctrl_reg - instance->reg_base,
 825                    instance->single_config[channel].ctrl | tmp);
 826
 827         spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
 828
 829         if (!(instance->single_config[channel].ctrl & ME4600_AI_CTRL_BIT_EX_TRIG)) {    // Software start
 830                 inl(instance->start_reg);
 831                 PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
 832                            instance->start_reg - instance->reg_base);
 833
 834                 delay = 2;
 835         }
 836
 837         j = jiffies;
 838
 839         while (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_EF_DATA)) {
 840                 if (delay && ((jiffies - j) >= delay)) {
 841                         if (!(instance->single_config[channel].ctrl & ME4600_AI_CTRL_BIT_EX_TRIG)) {    // Software start.
 842                                 PERROR("Value not available after wait.\n");
 843                                 err = ME_ERRNO_INTERNAL;
 844                         } else {        // External start.
 845                                 PERROR("Timeout reached.\n");
 846                                 err = ME_ERRNO_TIMEOUT;
 847                         }
 848                         break;
 849                 }
 850                 // Wait
 851                 set_current_state(TASK_INTERRUPTIBLE);
 852                 schedule_timeout(1);
 853
 854                 if (signal_pending(current)) {
 855                         PERROR
 856                             ("Wait on external trigger interrupted by signal.\n");
 857                         err = ME_ERRNO_SIGNAL;
 858                         break;
 859                 }
 860
 861                 if (instance->status != ai_status_single_configured) {
 862                         PERROR("Wait interrupted by reset.\n");
 863                         err = ME_ERRNO_CANCELLED;
 864                         break;
 865                 }
 866         }
 867
 868         // Read value.
 869         if (!err) {
 870                 val = inl(instance->data_reg) ^ 0x8000;
 871                 PDEBUG_REG("data_reg inl(0x%lX+0x%lX)=0x%x\n",
 872                            instance->reg_base,
 873                            instance->data_reg - instance->reg_base, val);
 874                 *value = val & ME4600_AI_MAX_DATA;
 875         } else {
 876                 *value = 0xFFFFFFFF;
 877         }
 878
 879         // Restore settings.
 880         spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
 881         tmp = inl(instance->ctrl_reg);
 882         // Clear FIFOs and dissable interrupts.
 883         tmp &=
 884             ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
 885         tmp |= ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_HF_IRQ;
 886         tmp |=
 887             ME4600_AI_CTRL_BIT_SC_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
 888             ME4600_AI_CTRL_BIT_LE_IRQ_RESET | ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
 889         outl(tmp, instance->ctrl_reg);
 890         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 891                    instance->ctrl_reg - instance->reg_base, tmp);
 892         spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
 893
 894         spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
 895
 896         ME_SUBDEVICE_EXIT;
 897
 898         return err;
 899 }
 900
 901 static int me4600_ai_io_stream_config(me_subdevice_t *subdevice,
 902                                       struct file *filep,
 903                                       meIOStreamConfig_t *config_list,
 904                                       int count,
 905                                       meIOStreamTrigger_t *trigger,
 906                                       int fifo_irq_threshold, int flags)
 907 {
 908         me4600_ai_subdevice_t *instance;
 909         int err = ME_ERRNO_SUCCESS;
 910         int i;                  // internal multipurpose variable
 911         unsigned long long data_required;
 912
 913         volatile uint32_t entry;
 914         volatile uint32_t ctrl = ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
 915         volatile uint32_t tmp;  // use when current copy of register's value needed
 916         unsigned long cpu_flags;
 917
 918         uint64_t acq_ticks;
 919         uint64_t scan_ticks;
 920         uint64_t conv_ticks;
 921         unsigned int acq_start_ticks_low = trigger->iAcqStartTicksLow;
 922         unsigned int acq_start_ticks_high = trigger->iAcqStartTicksHigh;
 923         unsigned int scan_start_ticks_low = trigger->iScanStartTicksLow;
 924         unsigned int scan_start_ticks_high = trigger->iScanStartTicksHigh;
 925         unsigned int conv_start_ticks_low = trigger->iConvStartTicksLow;
 926         unsigned int conv_start_ticks_high = trigger->iConvStartTicksHigh;
 927
 928         PDEBUG("executed. idx=0\n");
 929
 930         instance = (me4600_ai_subdevice_t *) subdevice;
 931
 932         if (flags) {
 933                 PERROR("Invalid flag specified.\n");
 934                 return ME_ERRNO_INVALID_FLAGS;
 935         }
 936
 937         ME_SUBDEVICE_ENTER
 938             // Convert ticks to 64 bit long values
 939             acq_ticks =
 940             (uint64_t) acq_start_ticks_low +
 941             ((uint64_t) acq_start_ticks_high << 32);
 942         scan_ticks =
 943             (uint64_t) scan_start_ticks_low +
 944             ((uint64_t) scan_start_ticks_high << 32);
 945         conv_ticks =
 946             (uint64_t) conv_start_ticks_low +
 947             ((uint64_t) conv_start_ticks_high << 32);
 948
 949         // Check settings - begin
 950         switch (trigger->iAcqStartTrigType) {
 951         case ME_TRIG_TYPE_SW:
 952         case ME_TRIG_TYPE_EXT_DIGITAL:
 953         case ME_TRIG_TYPE_EXT_ANALOG:
 954                 break;
 955
 956         default:
 957                 PERROR("Invalid acquisition start trigger type specified.\n");
 958                 err = ME_ERRNO_INVALID_ACQ_START_TRIG_TYPE;
 959                 goto ERROR;
 960                 break;
 961         }
 962
 963         if ((trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW)
 964             && (trigger->iAcqStartTrigEdge != ME_TRIG_EDGE_NONE)) {
 965                 PERROR("Invalid acquisition start trigger edge specified.\n");
 966                 err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
 967                 goto ERROR;
 968         }
 969
 970         if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_SW) {
 971                 switch (trigger->iAcqStartTrigEdge) {
 972                 case ME_TRIG_EDGE_RISING:
 973                 case ME_TRIG_EDGE_FALLING:
 974                 case ME_TRIG_EDGE_ANY:
 975                         break;
 976
 977                 default:
 978                         PERROR
 979                             ("Invalid acquisition start trigger edge specified.\n");
 980                         err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
 981                         goto ERROR;
 982                         break;
 983                 }
 984         }
 985
 986         if (trigger->iAcqStartTrigChan != ME_TRIG_CHAN_DEFAULT) {
 987                 PERROR
 988                     ("Invalid acquisition start trigger channel specified.\n");
 989                 err = ME_ERRNO_INVALID_ACQ_START_TRIG_CHAN;
 990                 goto ERROR;
 991         }
 992
 993         if ((acq_ticks < ME4600_AI_MIN_ACQ_TICKS)
 994             || (acq_ticks > ME4600_AI_MAX_ACQ_TICKS)) {
 995                 PERROR
 996                     ("Invalid acquisition start trigger argument specified.\n");
 997                 err = ME_ERRNO_INVALID_ACQ_START_ARG;
 998                 goto ERROR;
 999         }
1000
1001         switch (trigger->iScanStartTrigType) {
1002
1003         case ME_TRIG_TYPE_TIMER:
1004                 if ((scan_ticks < ME4600_AI_MIN_SCAN_TICKS)
1005                     || (scan_ticks > ME4600_AI_MAX_SCAN_TICKS)
1006                     || (scan_ticks < count * conv_ticks)
1007                     ) {
1008                         PERROR("Invalid scan start argument specified.\n");
1009                         err = ME_ERRNO_INVALID_SCAN_START_ARG;
1010                         goto ERROR;
1011                 }
1012                 break;
1013
1014         case ME_TRIG_TYPE_EXT_DIGITAL:
1015                 if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_EXT_DIGITAL) {
1016                         PERROR
1017                             ("Invalid scan start trigger type specified (Acq is HW digital)\n");
1018                         err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1019                         goto ERROR;
1020                 }
1021                 break;
1022
1023         case ME_TRIG_TYPE_EXT_ANALOG:
1024                 if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_EXT_ANALOG) {
1025                         PERROR
1026                             ("Invalid scan start trigger type specified (Acq is HW analog)\n");
1027                         err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1028                         goto ERROR;
1029                 }
1030                 break;
1031
1032         case ME_TRIG_TYPE_FOLLOW:
1033                 break;
1034
1035         default:
1036                 PERROR("Invalid scan start trigger type specified.\n");
1037                 err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1038                 goto ERROR;
1039                 break;
1040         }
1041
1042         switch (trigger->iConvStartTrigType) {
1043
1044         case ME_TRIG_TYPE_TIMER:
1045                 if ((conv_ticks < ME4600_AI_MIN_CHAN_TICKS)
1046                     || (conv_ticks > ME4600_AI_MAX_CHAN_TICKS)) {
1047                         PERROR
1048                             ("Invalid conv start trigger argument specified.\n");
1049                         err = ME_ERRNO_INVALID_CONV_START_ARG;
1050                         goto ERROR;
1051                 }
1052                 break;
1053
1054         case ME_TRIG_TYPE_EXT_DIGITAL:
1055                 if ((trigger->iScanStartTrigType != ME_TRIG_TYPE_FOLLOW)
1056                     || (trigger->iAcqStartTrigType !=
1057                         ME_TRIG_TYPE_EXT_DIGITAL)) {
1058                         PERROR("Invalid conv start trigger type specified.\n");
1059                         err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1060                         goto ERROR;
1061                 }
1062                 break;
1063
1064         case ME_TRIG_TYPE_EXT_ANALOG:
1065                 if ((trigger->iScanStartTrigType != ME_TRIG_TYPE_FOLLOW)
1066                     || (trigger->iAcqStartTrigType !=
1067                         ME_TRIG_TYPE_EXT_ANALOG)) {
1068                         PERROR("Invalid conv start trigger type specified.\n");
1069                         err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1070                         goto ERROR;
1071                 }
1072                 break;
1073
1074         default:
1075                 PERROR("Invalid conv start trigger type specified.\n");
1076                 err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1077                 goto ERROR;
1078
1079                 break;
1080         }
1081 /**
1082 * Aceptable settings:
1083 * iScanStopTrigType             :       iAcqStopTrigType
1084 *
1085 * ME_TRIG_TYPE_NONE             :       ME_TRIG_TYPE_NONE       -> infinite count with manual stop
1086 * ME_TRIG_TYPE_NONE             :       ME_TRIG_TYPE_COUNT      -> stop after getting iScanStopCount list of values (iScanStopCount * count)
1087 * ME_TRIG_TYPE_COUNT    :       ME_TRIG_TYPE_FOLLOW     -> stop after getting iAcqStopCount values (it can stops in midle of the list)
1088 */
1089         switch (trigger->iScanStopTrigType) {
1090
1091         case ME_TRIG_TYPE_NONE:
1092                 break;
1093
1094         case ME_TRIG_TYPE_COUNT:
1095                 if (trigger->iScanStopCount <= 0) {
1096                         PERROR("Invalid scan stop argument specified.\n");
1097                         err = ME_ERRNO_INVALID_SCAN_STOP_ARG;
1098                         goto ERROR;
1099                 }
1100                 break;
1101
1102         default:
1103                 PERROR("Invalid scan stop trigger type specified.\n");
1104                 err = ME_ERRNO_INVALID_SCAN_STOP_TRIG_TYPE;
1105                 goto ERROR;
1106                 break;
1107         }
1108
1109         switch (trigger->iAcqStopTrigType) {
1110
1111         case ME_TRIG_TYPE_NONE:
1112                 if (trigger->iScanStopTrigType != ME_TRIG_TYPE_NONE) {
1113                         PERROR("Invalid acq stop trigger type specified.\n");
1114                         err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1115                         goto ERROR;
1116                 }
1117                 break;
1118
1119         case ME_TRIG_TYPE_FOLLOW:
1120                 if (trigger->iScanStopTrigType != ME_TRIG_TYPE_COUNT) {
1121                         PERROR("Invalid acq stop trigger type specified.\n");
1122                         err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1123                         goto ERROR;
1124                 }
1125                 break;
1126
1127         case ME_TRIG_TYPE_COUNT:
1128                 if (trigger->iScanStopTrigType != ME_TRIG_TYPE_NONE) {
1129                         PERROR("Invalid acq stop trigger type specified.\n");
1130                         err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1131                         goto ERROR;
1132                 }
1133
1134                 if (trigger->iAcqStopCount <= 0) {
1135                         PERROR
1136                             ("Invalid acquisition or scan stop argument specified.\n");
1137                         err = ME_ERRNO_INVALID_ACQ_STOP_ARG;
1138                         goto ERROR;
1139                 }
1140                 break;
1141
1142         default:
1143                 PERROR("Invalid acq stop trigger type specified.\n");
1144                 err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1145                 goto ERROR;
1146                 break;
1147         }
1148
1149         if ((count <= 0) || (count > ME4600_AI_LIST_COUNT)) {
1150                 PERROR("Invalid channel list count specified.\n");
1151                 err = ME_ERRNO_INVALID_CONFIG_LIST_COUNT;
1152                 goto ERROR;
1153         }
1154 ///This is general limitation
1155 //      if (fifo_irq_threshold < 0 || fifo_irq_threshold >= ME4600_AI_CIRC_BUF_COUNT)
1156 ///This is limitation from Windows. I use it for compatibility.
1157         if (fifo_irq_threshold < 0
1158             || fifo_irq_threshold >= ME4600_AI_FIFO_COUNT) {
1159                 PERROR("Invalid fifo irq threshold specified.\n");
1160                 err = ME_ERRNO_INVALID_FIFO_IRQ_THRESHOLD;
1161                 goto ERROR;
1162         }
1163
1164         if ((config_list[0].iRef == ME_REF_AI_DIFFERENTIAL)
1165             && (instance->channels == 16)) {
1166                 PERROR
1167                     ("Differential reference is not available on this subdevice.\n");
1168                 err = ME_ERRNO_INVALID_REF;
1169                 goto ERROR;
1170         }
1171
1172         if (flags & ME_IO_STREAM_CONFIG_SAMPLE_AND_HOLD) {
1173                 if (!instance->sh) {
1174                         PERROR
1175                             ("Sample and hold is not available for this board.\n");
1176                         err = ME_ERRNO_INVALID_FLAGS;
1177                         goto ERROR;
1178                 }
1179                 if (config_list[0].iRef == ME_REF_AI_DIFFERENTIAL) {
1180                         PERROR
1181                             ("Sample and hold is not available in differential mode.\n");
1182                         err = ME_ERRNO_INVALID_FLAGS;
1183                         goto ERROR;
1184                 }
1185         }
1186
1187         for (i = 0; i < count; i++) {
1188                 if ((config_list[i].iStreamConfig < 0)
1189                     || (config_list[i].iStreamConfig >= instance->ranges_len)) {
1190                         PERROR("Invalid stream config specified.\n");
1191                         err = ME_ERRNO_INVALID_STREAM_CONFIG;
1192                         goto ERROR;
1193                 }
1194
1195                 if ((config_list[i].iRef != ME_REF_AI_GROUND)
1196                     && (config_list[i].iRef != ME_REF_AI_DIFFERENTIAL)) {
1197                         PERROR("Invalid references in the list. Ref=0x%x\n",
1198                                config_list[i].iRef);
1199                         err = ME_ERRNO_INVALID_REF;
1200                         goto ERROR;
1201                 }
1202
1203                 if (config_list[i].iStreamConfig % 2) { // StreamConfig: 1 or 3
1204                         if (config_list[i].iRef == ME_REF_AI_DIFFERENTIAL) {
1205                                 PERROR
1206                                     ("Only bipolar modes support differential measurement.\n");
1207                                 err = ME_ERRNO_INVALID_REF;
1208                                 goto ERROR;
1209                         }
1210                 }
1211
1212                 if (config_list[i].iRef != config_list[0].iRef) {
1213                         PERROR
1214                             ("Not all references in the configuration list are equal. Ref[0]=0x%x Ref[%d]=0x%x\n",
1215                              config_list[0].iRef, i, config_list[i].iRef);
1216                         err = ME_ERRNO_INVALID_REF;
1217                         goto ERROR;
1218                 }
1219
1220                 if ((config_list[i].iRef == ME_REF_AI_DIFFERENTIAL)
1221                     && (config_list[i].iChannel >= 16)) {
1222                         PERROR("Channel not available in differential mode.\n");
1223                         err = ME_ERRNO_INVALID_CHANNEL;
1224                         goto ERROR;
1225                 }
1226
1227                 if ((config_list[i].iChannel < 0)
1228                     || (config_list[i].iChannel >= instance->channels)) {
1229                         PERROR("Invalid channel number specified.\n");
1230                         err = ME_ERRNO_INVALID_CHANNEL;
1231                         goto ERROR;
1232                 }
1233         }
1234
1235         // Check settings - end
1236
1237         //Cancel control task
1238         PDEBUG("Cancel control task.\n");
1239         instance->ai_control_task_flag = 0;
1240         cancel_delayed_work(&instance->ai_control_task);
1241
1242         // Work around from Keith Hartley - begin
1243         if (trigger->iScanStartTrigType == ME_TRIG_TYPE_TIMER) {
1244                 if (count == 1) {
1245                         // The hardware does not work properly with a non-zero scan time
1246                         // if there is only ONE channel in the channel list. In this case
1247                         // we must set the scan time to zero and use the channel time.
1248
1249                         conv_ticks = scan_ticks;
1250                         trigger->iScanStartTrigType = ME_TRIG_TYPE_FOLLOW;
1251                 } else if (scan_ticks == count * conv_ticks) {
1252                         // Another hardware problem. If the number of scan ticks is
1253                         // exactly equal to the number of channel ticks multiplied by
1254                         // the number of channels then the sampling rate is reduced
1255                         // by half.
1256                         trigger->iScanStartTrigType = ME_TRIG_TYPE_FOLLOW;
1257                 }
1258         }
1259         // Work around from Keith Hartley - end
1260
1261         spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
1262
1263         if (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) {
1264                 PERROR("Subdevice is busy.\n");
1265                 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
1266                 ME_SUBDEVICE_EXIT;
1267                 return ME_ERRNO_SUBDEVICE_BUSY;
1268         }
1269
1270         instance->status = ai_status_none;
1271         spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1272         // Stop all actions. Block all interrupts. Clear (disable) FIFOs.
1273         ctrl =
1274             ME4600_AI_CTRL_BIT_LE_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
1275             ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
1276
1277         tmp = inl(instance->ctrl_reg);
1278         // Preserve EXT IRQ and OFFSET settings. Clean other bits.
1279         tmp &=
1280             (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET |
1281              ME4600_AI_CTRL_BIT_FULLSCALE | ME4600_AI_CTRL_BIT_OFFSET);
1282
1283         // Send it to register.
1284         outl(tmp | ctrl, instance->ctrl_reg);
1285         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1286                    instance->ctrl_reg - instance->reg_base, tmp | ctrl);
1287
1288         // Enable channel fifo -> data fifo in stream_start().
1289         ctrl |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO;
1290         outl(tmp | ctrl, instance->ctrl_reg);
1291         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1292                    instance->ctrl_reg - instance->reg_base, tmp | ctrl);
1293         spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1294
1295         // Write the channel list
1296         for (i = 0; i < count; i++) {
1297                 entry = config_list[i].iChannel;
1298
1299                 switch (config_list[i].iStreamConfig) {
1300                 case 0: //BIPOLAR 10V
1301 /*
1302                                 // ME4600_AI_LIST_RANGE_BIPOLAR_10 = 0x0000
1303                                 // 'entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10' <== Do nothing. Removed.
1304                                 entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10;
1305 */
1306                         break;
1307                 case 1: //UNIPOLAR 10V
1308                         entry |= ME4600_AI_LIST_RANGE_UNIPOLAR_10;
1309                         break;
1310                 case 2: //BIPOLAR 2.5V
1311                         entry |= ME4600_AI_LIST_RANGE_BIPOLAR_2_5;
1312                         break;
1313                 case 3: //UNIPOLAR 2.5V
1314                         entry |= ME4600_AI_LIST_RANGE_UNIPOLAR_2_5;
1315                         break;
1316                 default:
1317                         PERROR_CRITICAL("UNCHECK ERROR in config_list!\n");
1318                         PERROR_CRITICAL
1319                             ("WRONG range\nPosition:%d Range:0x%04X\n", i,
1320                              config_list[i].iStreamConfig);
1321                         goto VERIFY_ERROR;
1322                         break;
1323                 }
1324
1325                 switch (config_list[i].iRef) {
1326                 case ME_REF_AI_GROUND:  //SINGLE ENDED
1327 /*
1328                                 // ME4600_AI_LIST_INPUT_SINGLE_ENDED = 0x0000
1329                                 // 'entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED' ==> Do nothing. Removed.
1330                                 entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED;
1331 */ break;
1332                 case ME_REF_AI_DIFFERENTIAL:    //DIFFERENTIAL
1333                         entry |= ME4600_AI_LIST_INPUT_DIFFERENTIAL;
1334                         break;
1335                 default:
1336                         PERROR_CRITICAL("UNCHECK ERROR in config_list!\n");
1337                         PERROR_CRITICAL
1338                             ("WRONG reference\nPosition:%d Reference:0x%04X\n",
1339                              i, config_list[i].iRef);
1340                         goto VERIFY_ERROR;
1341                         break;
1342                 }
1343
1344                 //Add last entry flag
1345                 if (i == (count - 1)) {
1346                         entry |= ME4600_AI_LIST_LAST_ENTRY;
1347                 }
1348
1349                 outl(entry, instance->channel_list_reg);
1350                 PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
1351                            instance->reg_base,
1352                            instance->channel_list_reg - instance->reg_base,
1353                            entry);
1354         }
1355
1356         // Set triggering registers
1357         --acq_ticks;
1358         outl(acq_ticks, instance->chan_pre_timer_reg);
1359         PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%llX\n",
1360                    instance->reg_base,
1361                    instance->chan_pre_timer_reg - instance->reg_base,
1362                    acq_ticks);
1363         outl(acq_ticks, instance->scan_pre_timer_low_reg);
1364         PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%llX\n",
1365                    instance->reg_base,
1366                    instance->scan_pre_timer_low_reg - instance->reg_base,
1367                    acq_ticks & 0xFFFFFFFF);
1368         outl((acq_ticks >> 32), instance->scan_pre_timer_high_reg);
1369         PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%llX\n",
1370                    instance->reg_base,
1371                    instance->scan_pre_timer_high_reg - instance->reg_base,
1372                    (acq_ticks >> 32) & 0xFFFFFFFF);
1373
1374         // Set triggers
1375         switch (trigger->iAcqStartTrigType) {
1376                 // Internal
1377         case ME_TRIG_TYPE_SW:
1378                 // Nothing to set.
1379                 break;
1380
1381                 // External
1382         case ME_TRIG_TYPE_EXT_ANALOG:
1383                 ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG_ANALOG;
1384         case ME_TRIG_TYPE_EXT_DIGITAL:
1385                 ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG;
1386
1387                 // External trigger needs edge's definition
1388                 switch (trigger->iAcqStartTrigEdge) {
1389                 case ME_TRIG_EDGE_RISING:
1390                         // Nothing to set.
1391                         break;
1392
1393                 case ME_TRIG_EDGE_FALLING:
1394                         ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG_FALLING;
1395                         break;
1396
1397                 case ME_TRIG_EDGE_ANY:
1398                         ctrl |=
1399                             ME4600_AI_CTRL_BIT_EX_TRIG_FALLING |
1400                             ME4600_AI_CTRL_BIT_EX_TRIG_BOTH;
1401                         break;
1402
1403                 default:
1404                         PERROR_CRITICAL
1405                             ("UNCHECK TRIGGER EDGE in triggers structure!\n");
1406                         PERROR_CRITICAL
1407                             ("WRONG acquisition start trigger:0x%04X.\n",
1408                              trigger->iAcqStartTrigEdge);
1409                         err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
1410                         goto VERIFY_ERROR;
1411                         break;
1412                 }
1413                 break;
1414
1415         default:
1416                 PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1417                 PERROR_CRITICAL("WRONG acquisition start trigger:0x%04X.\n",
1418                                 trigger->iAcqStartTrigType);
1419                 err = ME_ERRNO_INVALID_ACQ_START_TRIG_TYPE;
1420                 goto VERIFY_ERROR;
1421                 break;
1422         }
1423
1424         switch (trigger->iScanStartTrigType) {
1425         case ME_TRIG_TYPE_TIMER:
1426                 --scan_ticks;
1427                 outl(scan_ticks, instance->scan_timer_low_reg);
1428                 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%llX\n",
1429                            instance->reg_base,
1430                            instance->scan_timer_low_reg - instance->reg_base,
1431                            scan_ticks & 0xFFFFFFFF);
1432                 outl((scan_ticks >> 32), instance->scan_timer_high_reg);
1433                 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%llX\n",
1434                            instance->reg_base,
1435                            instance->scan_timer_high_reg - instance->reg_base,
1436                            (scan_ticks >> 32) & 0xFFFFFFFF);
1437
1438                 if (trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW) {
1439                         ctrl |= ME4600_AI_CTRL_BIT_MODE_0;
1440                 } else {
1441                         ctrl |= ME4600_AI_CTRL_BIT_MODE_1;
1442                 }
1443                 break;
1444
1445         case ME_TRIG_TYPE_EXT_DIGITAL:
1446         case ME_TRIG_TYPE_EXT_ANALOG:
1447                 outl(0, instance->scan_timer_low_reg);
1448                 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
1449                            instance->reg_base,
1450                            instance->scan_timer_low_reg - instance->reg_base,
1451                            0);
1452                 outl(0, instance->scan_timer_high_reg);
1453                 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
1454                            instance->reg_base,
1455                            instance->scan_timer_high_reg - instance->reg_base,
1456                            0);
1457                 ctrl |= ME4600_AI_CTRL_BIT_MODE_2;
1458                 break;
1459
1460         case ME_TRIG_TYPE_FOLLOW:
1461                 outl(0, instance->scan_timer_low_reg);
1462                 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
1463                            instance->reg_base,
1464                            instance->scan_timer_low_reg - instance->reg_base,
1465                            0);
1466                 outl(0, instance->scan_timer_high_reg);
1467                 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
1468                            instance->reg_base,
1469                            instance->scan_timer_high_reg - instance->reg_base,
1470                            0);
1471
1472                 if (trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW) {
1473                         ctrl |= ME4600_AI_CTRL_BIT_MODE_0;
1474                 } else {
1475                         ctrl |= ME4600_AI_CTRL_BIT_MODE_1;
1476                 }
1477                 break;
1478
1479         default:
1480                 PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1481                 PERROR_CRITICAL("WRONG scan start trigger:0x%04X.\n",
1482                                 trigger->iScanStartTrigType);
1483                 err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1484                 goto VERIFY_ERROR;
1485                 break;
1486         }
1487
1488         switch (trigger->iConvStartTrigType) {
1489
1490         case ME_TRIG_TYPE_TIMER:
1491                 --conv_ticks;
1492                 outl(conv_ticks, instance->chan_timer_reg);
1493                 PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%llX\n",
1494                            instance->reg_base,
1495                            instance->chan_timer_reg - instance->reg_base,
1496                            conv_ticks);
1497                 break;
1498
1499         case ME_TRIG_TYPE_EXT_DIGITAL:
1500         case ME_TRIG_TYPE_EXT_ANALOG:
1501                 outl(0, instance->chan_timer_reg);
1502                 PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
1503                            instance->reg_base,
1504                            instance->chan_timer_reg - instance->reg_base, 0);
1505                 ctrl |= ME4600_AI_CTRL_BIT_MODE_0 | ME4600_AI_CTRL_BIT_MODE_1;
1506                 break;
1507
1508         default:
1509                 PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1510                 PERROR_CRITICAL("WRONG conv start trigger:0x%04X.\n",
1511                                 trigger->iConvStartTrigType);
1512                 err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1513                 goto VERIFY_ERROR;
1514
1515                 break;
1516         }
1517
1518         //Sample & Hold feature
1519         if (flags & ME_IO_STREAM_CONFIG_SAMPLE_AND_HOLD) {
1520                 if (instance->sh) {
1521                         ctrl |= ME4600_AI_CTRL_BIT_SAMPLE_HOLD;
1522                 } else {
1523                         PERROR_CRITICAL("UNCHECK S&H feature!\n");
1524                         err = ME_ERRNO_INVALID_FLAGS;
1525                         goto VERIFY_ERROR;
1526                 }
1527         }
1528         //Enable IRQs sources but leave latches blocked.
1529         ctrl |= (ME4600_AI_CTRL_BIT_HF_IRQ | ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_LE_IRQ);    //The last IRQ source (ME4600_AI_CTRL_BIT_LE_IRQ) is unused!
1530
1531         //Everything is good. Finalize
1532         spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1533         tmp = inl(instance->ctrl_reg);
1534
1535         //Preserve EXT IRQ and OFFSET settings. Clean other bits.
1536         tmp &=
1537             (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET |
1538              ME4600_AI_CTRL_BIT_FULLSCALE | ME4600_AI_CTRL_BIT_OFFSET);
1539
1540         // write the control word
1541         outl(ctrl | tmp, instance->ctrl_reg);
1542         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1543                    instance->ctrl_reg - instance->reg_base, ctrl | tmp);
1544         spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1545
1546         //Set the global parameters end exit.
1547         instance->chan_list_len = count;
1548         instance->fifo_irq_threshold = fifo_irq_threshold;
1549
1550         if (trigger->iAcqStopTrigType == ME_TRIG_TYPE_COUNT) {
1551                 data_required =
1552                     (unsigned long long)trigger->iAcqStopCount *
1553                     (unsigned long long)count;
1554                 if (data_required > UINT_MAX)
1555                         data_required = UINT_MAX;
1556                 instance->data_required = (unsigned int)data_required;
1557         } else if (trigger->iScanStopTrigType == ME_TRIG_TYPE_COUNT)
1558                 instance->data_required =
1559                     (unsigned long long)trigger->iScanStopCount;
1560         else
1561                 instance->data_required = 0;
1562
1563         // Mark subdevice as configured to work in stream mode.
1564         instance->status = ai_status_stream_configured;
1565
1566         // Deinit single config. Set all entries to NOT_CONFIGURED.
1567         for (i = 0; i < instance->channels; i++) {
1568                 instance->single_config[i].status =
1569                     ME_SINGLE_CHANNEL_NOT_CONFIGURED;
1570         }
1571
1572 VERIFY_ERROR:           // Error in code. Wrong setting check. This should never ever happend!
1573         spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
1574 ERROR:                  // Error in settings.
1575         ME_SUBDEVICE_EXIT;
1576
1577         return err;
1578 }
1579
1580 static int me4600_ai_io_stream_new_values(me_subdevice_t *subdevice,
1581                                           struct file *filep,
1582                                           int time_out, int *count, int flags)
1583 {
1584         me4600_ai_subdevice_t *instance;
1585         int err = ME_ERRNO_SUCCESS;
1586         unsigned long t;
1587         unsigned long j;
1588         int volatile head;
1589
1590         PDEBUG("executed. idx=0\n");
1591
1592         if (flags) {
1593                 PERROR("Invalid flag specified.\n");
1594                 return ME_ERRNO_INVALID_FLAGS;
1595         }
1596
1597         if (time_out < 0) {
1598                 PERROR("Invalid time_out specified.\n");
1599                 return ME_ERRNO_INVALID_TIMEOUT;
1600         }
1601
1602         if (time_out) {
1603                 t = (time_out * HZ) / 1000;
1604
1605                 if (t == 0)
1606                         t = 1;
1607         } else {                // Max time.
1608                 t = LONG_MAX;
1609         }
1610
1611         instance = (me4600_ai_subdevice_t *) subdevice;
1612
1613         ME_SUBDEVICE_ENTER;
1614
1615         j = jiffies;
1616
1617         while (1) {
1618                 // Only runing device can generate break.
1619                 head = instance->circ_buf.head;
1620                 wait_event_interruptible_timeout(instance->wait_queue,
1621                                                  ((head !=
1622                                                    instance->circ_buf.head)
1623                                                   ||
1624                                                   ((instance->status <=
1625                                                     ai_status_stream_run_wait)
1626                                                    && (instance->status >=
1627                                                        ai_status_stream_end_wait))),
1628                                                  t);
1629
1630                 if (head != instance->circ_buf.head) {  // New data in buffer.
1631                         break;
1632                 } else if (instance->status == ai_status_stream_end) {  // End of work.
1633                         break;
1634                 } else if (instance->status == ai_status_stream_fifo_error) {
1635                         err = ME_ERRNO_FIFO_BUFFER_OVERFLOW;
1636                         break;
1637                 } else if (instance->status == ai_status_stream_buffer_error) {
1638                         err = ME_ERRNO_RING_BUFFER_OVERFLOW;
1639                         break;
1640                 } else if (instance->status == ai_status_stream_error) {
1641                         err = ME_ERRNO_INTERNAL;
1642                         break;
1643                 } else if ((jiffies - j) >= t) {
1644                         PERROR("Wait on values timed out.\n");
1645                         err = ME_ERRNO_TIMEOUT;
1646                         break;
1647                 } else if (signal_pending(current)) {
1648                         PERROR("Wait on values interrupted from signal.\n");
1649                         err = ME_ERRNO_SIGNAL;
1650                         break;
1651                 }
1652                 // Correct timeout.
1653                 t -= jiffies - j;
1654         }
1655
1656         *count = me_circ_buf_values(&instance->circ_buf);
1657
1658         ME_SUBDEVICE_EXIT;
1659
1660         return err;
1661 }
1662
1663 static inline int me4600_ai_io_stream_read_get_value(me4600_ai_subdevice_t *
1664                                                      instance, int *values,
1665                                                      const int count,
1666                                                      const int flags)
1667 {
1668         int n;
1669         int i;
1670         uint32_t value;
1671
1672         ///Checking how many datas can be copied.
1673         n = me_circ_buf_values(&instance->circ_buf);
1674         if (n <= 0)
1675                 return 0;
1676
1677         if (n > count)
1678                 n = count;
1679
1680         if (flags & ME_IO_STREAM_READ_FRAMES) {
1681                 if (n < instance->chan_list_len)        //Not enough data!
1682                         return 0;
1683                 n -= n % instance->chan_list_len;
1684         }
1685
1686         for (i = 0; i < n; i++) {
1687                 value = *(instance->circ_buf.buf + instance->circ_buf.tail);
1688                 if (put_user(value, values + i)) {
1689                         PERROR("Cannot copy new values to user.\n");
1690                         return -ME_ERRNO_INTERNAL;
1691                 }
1692                 instance->circ_buf.tail++;
1693                 instance->circ_buf.tail &= instance->circ_buf.mask;
1694         }
1695         return n;
1696 }
1697
1698 static int me4600_ai_io_stream_read(me_subdevice_t *subdevice,
1699                                     struct file *filep,
1700                                     int read_mode,
1701                                     int *values, int *count, int flags)
1702 {
1703         me4600_ai_subdevice_t *instance;
1704         int err = ME_ERRNO_SUCCESS;
1705         int ret;
1706
1707         int c = *count;
1708         int min = c;
1709
1710         PDEBUG("executed. idx=0\n");
1711
1712         if (flags & ~ME_IO_STREAM_READ_FRAMES) {
1713                 PERROR("Invalid flag specified.\n");
1714                 return ME_ERRNO_INVALID_FLAGS;
1715         }
1716
1717         if (!values || !count) {
1718                 PERROR("Request has invalid pointer.\n");
1719                 return ME_ERRNO_INVALID_POINTER;
1720         }
1721
1722         if (c < 0) {
1723                 PERROR("Request has invalid value's counter.\n");
1724                 return ME_ERRNO_INVALID_VALUE_COUNT;
1725         }
1726
1727         if ((read_mode != ME_READ_MODE_BLOCKING)
1728             && (read_mode != ME_READ_MODE_NONBLOCKING)) {
1729                 PERROR("Invalid read mode specified.\n");
1730                 return ME_ERRNO_INVALID_READ_MODE;
1731         }
1732
1733         if (c == 0) {           //You get what you want! Nothing more or less.
1734                 return ME_ERRNO_SUCCESS;
1735         }
1736
1737         instance = (me4600_ai_subdevice_t *) subdevice;
1738         ME_SUBDEVICE_ENTER;
1739
1740         //Check if subdevice is configured.
1741         if (instance->chan_list_len <= 0) {
1742                 PERROR("Subdevice wasn't configured.\n");
1743                 ME_SUBDEVICE_EXIT;
1744                 return ME_ERRNO_PREVIOUS_CONFIG;
1745         }
1746
1747         if (flags & ME_IO_STREAM_READ_FRAMES) {
1748                 if (c < instance->chan_list_len) {      //Not enough data requested.
1749                         PERROR
1750                             ("When using FRAME_READ mode minimal size is defined by channel list.\n");
1751                         ME_SUBDEVICE_EXIT;
1752                         return ME_ERRNO_INVALID_VALUE_COUNT;
1753                 }
1754         }
1755
1756         if (c > (ME4600_AI_CIRC_BUF_COUNT - instance->chan_list_len)) { // To return acceptable amount of data when user pass too big value.
1757                 min = ME4600_AI_CIRC_BUF_COUNT - instance->chan_list_len;
1758         }
1759
1760         if (flags & ME_IO_STREAM_READ_FRAMES) {
1761                 //Wait for whole list.
1762                 if (read_mode == ME_READ_MODE_BLOCKING) {
1763                         min = c - (c % instance->chan_list_len);
1764                 }
1765
1766                 if (read_mode == ME_READ_MODE_NONBLOCKING) {
1767                         min = instance->chan_list_len;
1768                 }
1769         }
1770
1771         if ((inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM)) {   //Working
1772                 //If blocking mode -> wait for data.
1773                 if ((me_circ_buf_values(&instance->circ_buf) < min)
1774                     && (read_mode == ME_READ_MODE_BLOCKING)) {
1775                         wait_event_interruptible(instance->wait_queue,
1776                                                  ((me_circ_buf_values
1777                                                    (&instance->circ_buf) >= min)
1778                                                   || !(inl(instance->status_reg)
1779                                                        &
1780                                                        ME4600_AI_STATUS_BIT_FSM)));
1781
1782                         if (signal_pending(current)) {
1783                                 PERROR
1784                                     ("Wait on values interrupted from signal.\n");
1785                                 err = ME_ERRNO_SIGNAL;
1786                         }
1787                 }
1788         }
1789
1790         ret = me4600_ai_io_stream_read_get_value(instance, values, c, flags);
1791         if (ret < 0) {
1792                 err = -ret;
1793                 *count = 0;
1794         } else if (ret == 0) {
1795                 *count = 0;
1796                 if (instance->status == ai_status_stream_fifo_error) {
1797                         err = ME_ERRNO_FIFO_BUFFER_OVERFLOW;
1798                         instance->status = ai_status_stream_end;
1799                 } else if (instance->status == ai_status_stream_buffer_error) {
1800                         err = ME_ERRNO_RING_BUFFER_OVERFLOW;
1801                         instance->status = ai_status_stream_end;
1802                 } else if (instance->status == ai_status_stream_end) {
1803                         err = ME_ERRNO_SUBDEVICE_NOT_RUNNING;
1804                 } else if (instance->status == ai_status_stream_error) {
1805                         err = ME_ERRNO_INTERNAL;
1806                 } else if (instance->status == ai_status_none) {
1807                         PDEBUG("Stream canceled.\n");
1808                         err = ME_ERRNO_INTERNAL;
1809                 }
1810         } else {
1811                 *count = ret;
1812         }
1813
1814         ME_SUBDEVICE_EXIT;
1815
1816         return err;
1817 }
1818
1819 /** @brief Stop aqusation. Preserve FIFOs.
1820 *
1821 * @param instance The subdevice instance (pointer).
1822 */
1823
1824 static int ai_stop_immediately(me4600_ai_subdevice_t *instance)
1825 {
1826         unsigned long cpu_flags = 0;
1827         volatile uint32_t ctrl;
1828         const int timeout = HZ / 10;    //100ms
1829         int i;
1830
1831         for (i = 0; i <= timeout; i++) {
1832                 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1833                 ctrl = inl(instance->ctrl_reg);
1834                 ctrl &= ~ME4600_AI_CTRL_BIT_STOP;
1835                 ctrl |=
1836                     (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP |
1837                      ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
1838                      ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
1839                 outl(ctrl, instance->ctrl_reg);
1840                 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
1841                            instance->reg_base,
1842                            instance->ctrl_reg - instance->reg_base, ctrl);
1843                 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1844
1845                 if (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM)) {  // Exit.
1846                         break;
1847                 }
1848
1849                 PINFO("Wait for stop: %d\n", i + 1);
1850                 //Still working!
1851                 set_current_state(TASK_INTERRUPTIBLE);
1852                 schedule_timeout(1);
1853         }
1854
1855         if (i > timeout) {
1856                 PERROR_CRITICAL("FSM IS BUSY!\n");
1857                 return ME_ERRNO_INTERNAL;
1858         }
1859
1860         return ME_ERRNO_SUCCESS;
1861 }
1862
1863 static int me4600_ai_io_stream_start(me_subdevice_t *subdevice,
1864                                      struct file *filep,
1865                                      int start_mode, int time_out, int flags)
1866 {
1867         me4600_ai_subdevice_t *instance;
1868         int err = ME_ERRNO_SUCCESS;
1869         unsigned long cpu_flags = 0;
1870         unsigned long ref;
1871         unsigned long delay = 0;
1872
1873         volatile uint32_t tmp;
1874
1875         PDEBUG("executed. idx=0\n");
1876
1877         instance = (me4600_ai_subdevice_t *) subdevice;
1878
1879         if (flags) {
1880                 PERROR("Invalid flag specified.\n");
1881                 return ME_ERRNO_INVALID_FLAGS;
1882         }
1883
1884         if ((start_mode != ME_START_MODE_BLOCKING)
1885             && (start_mode != ME_START_MODE_NONBLOCKING)) {
1886                 PERROR("Invalid start mode specified.\n");
1887                 return ME_ERRNO_INVALID_START_MODE;
1888         }
1889
1890         if (time_out < 0) {
1891                 PERROR("Invalid timeout specified.\n");
1892                 return ME_ERRNO_INVALID_TIMEOUT;
1893         }
1894
1895         if (time_out) {
1896                 delay = (time_out * HZ) / 1000;
1897
1898                 if (delay == 0)
1899                         delay = 1;
1900         }
1901
1902         ME_SUBDEVICE_ENTER
1903             spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1904
1905         tmp = inl(instance->ctrl_reg);
1906
1907         if ((tmp & ME4600_AI_STATUS_BIT_FSM)) {
1908                 PERROR("Conversion is already running.\n");
1909                 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1910                 err = ME_ERRNO_SUBDEVICE_BUSY;
1911                 goto ERROR;
1912         }
1913
1914         if (instance->chan_list_len == 0) {     //Not configured!
1915                 PERROR("Subdevice is not configured to work in stream mode!\n");
1916                 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1917                 err = ME_ERRNO_PREVIOUS_CONFIG;
1918                 goto ERROR;
1919         }
1920
1921         if (!(tmp & (ME4600_AI_CTRL_BIT_MODE_0 | ME4600_AI_CTRL_BIT_MODE_1 | ME4600_AI_CTRL_BIT_MODE_2))) {     //Mode 0 = single work => no stream config
1922                 PERROR("Subdevice is configured to work in single mode.\n");
1923                 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1924                 err = ME_ERRNO_PREVIOUS_CONFIG;
1925                 goto ERROR;
1926         }
1927         //Reset stop bits.
1928         tmp |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_STOP;
1929         outl(tmp, instance->ctrl_reg);
1930         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1931                    instance->ctrl_reg - instance->reg_base, tmp);
1932
1933         //Start datas' FIFO.
1934         tmp |= ME4600_AI_CTRL_BIT_DATA_FIFO;
1935         //Free stop bits.
1936         tmp &= ~(ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_STOP);
1937         outl(tmp, instance->ctrl_reg);
1938         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1939                    instance->ctrl_reg - instance->reg_base, tmp);
1940         spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1941
1942         //Cancel control task
1943         PDEBUG("Cancel control task.\n");
1944         instance->ai_control_task_flag = 0;
1945         cancel_delayed_work(&instance->ai_control_task);
1946
1947         //Set the starting values.
1948         instance->ISM.global_read = 0;
1949         instance->ISM.read = 0;
1950         //Clear circular buffer
1951         instance->circ_buf.head = 0;
1952         instance->circ_buf.tail = 0;
1953
1954         //Set everything.
1955         ai_data_acquisition_logic(instance);
1956
1957         //Set status to 'wait for start'
1958         instance->status = ai_status_stream_run_wait;
1959
1960         // Set control task's timeout
1961         instance->timeout.delay = delay;
1962         instance->timeout.start_time = jiffies;
1963
1964         //Lets go! Start work
1965         inl(instance->start_reg);
1966         PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
1967                    instance->start_reg - instance->reg_base);
1968
1969         // Schedule control task
1970         instance->ai_control_task_flag = 1;
1971         queue_delayed_work(instance->me4600_workqueue,
1972                            &instance->ai_control_task, 1);
1973
1974         PDEVELOP("Delay:%ld\n", delay);
1975
1976         if (start_mode == ME_START_MODE_BLOCKING) {     //Wait for start.
1977                 ref = jiffies;
1978                 //Only runing process will interrupt this call. Events are signaled when status change. Extra timeout add for safe reason.
1979                 wait_event_interruptible_timeout(instance->wait_queue,
1980                                                  (instance->status !=
1981                                                   ai_status_stream_run_wait),
1982                                                  (delay) ? delay +
1983                                                  1 : LONG_MAX);
1984
1985                 if ((instance->status != ai_status_stream_run)
1986                     && (instance->status != ai_status_stream_end)) {
1987                         PDEBUG("Starting stream canceled. %d\n",
1988                                instance->status);
1989                         err = ME_ERRNO_CANCELLED;
1990                 }
1991
1992                 if (signal_pending(current)) {
1993                         PERROR("Wait on start of state machine interrupted.\n");
1994                         instance->status = ai_status_none;
1995                         ai_stop_isr(instance);
1996                         err = ME_ERRNO_SIGNAL;
1997                 } else if ((delay) && ((jiffies - ref) > delay)) {
1998                         if (instance->status != ai_status_stream_run) {
1999                                 if (instance->status == ai_status_stream_end) {
2000                                         PDEBUG("Timeout reached.\n");
2001                                 } else if ((jiffies - ref) > delay + 1) {
2002                                         PERROR
2003                                             ("Timeout reached. Not handled by control task!\n");
2004                                         ai_stop_isr(instance);
2005                                         instance->status =
2006                                             ai_status_stream_error;
2007                                 } else {
2008                                         PERROR
2009                                             ("Timeout reached. Signal come but status is strange: %d\n",
2010                                              instance->status);
2011                                         ai_stop_isr(instance);
2012                                         instance->status =
2013                                             ai_status_stream_error;
2014                                 }
2015
2016                                 instance->ai_control_task_flag = 0;
2017                                 cancel_delayed_work(&instance->ai_control_task);
2018                                 err = ME_ERRNO_TIMEOUT;
2019                         }
2020                 }
2021         }
2022 #ifdef MEDEBUG_INFO
2023         tmp = inl(instance->ctrl_reg);
2024         PDEBUG_REG("ctrl_reg inl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2025                    instance->ctrl_reg - instance->reg_base, tmp);
2026
2027         PINFO("STATUS_BIT_FSM=%s.\n",
2028               (tmp & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2029         PINFO("CTRL_BIT_HF_IRQ=%s.\n",
2030               (tmp & ME4600_AI_CTRL_BIT_HF_IRQ) ? "enable" : "disable");
2031         PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2032               (tmp & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" : "work");
2033         PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2034               (tmp & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2035         PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2036               (tmp & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2037         PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2038               (tmp & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" : "work");
2039 #endif
2040
2041 ERROR:
2042         ME_SUBDEVICE_EXIT;
2043
2044         return err;
2045 }
2046
2047 static int me4600_ai_io_stream_status(me_subdevice_t *subdevice,
2048                                       struct file *filep,
2049                                       int wait,
2050                                       int *status, int *values, int flags)
2051 {
2052         me4600_ai_subdevice_t *instance;
2053         int err = ME_ERRNO_SUCCESS;
2054
2055         PDEBUG("executed. idx=0\n");
2056
2057         instance = (me4600_ai_subdevice_t *) subdevice;
2058
2059         if (flags) {
2060                 PERROR("Invalid flag specified.\n");
2061                 return ME_ERRNO_INVALID_FLAGS;
2062         }
2063
2064         ME_SUBDEVICE_ENTER;
2065
2066         switch (instance->status) {
2067         case ai_status_single_configured:
2068         case ai_status_stream_configured:
2069         case ai_status_stream_end:
2070         case ai_status_stream_fifo_error:
2071         case ai_status_stream_buffer_error:
2072         case ai_status_stream_error:
2073                 *status = ME_STATUS_IDLE;
2074                 break;
2075
2076         case ai_status_stream_run_wait:
2077         case ai_status_stream_run:
2078         case ai_status_stream_end_wait:
2079                 *status = ME_STATUS_BUSY;
2080                 break;
2081
2082         case ai_status_none:
2083         default:
2084                 *status =
2085                     (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) ?
2086                     ME_STATUS_BUSY : ME_STATUS_IDLE;
2087                 break;
2088         }
2089
2090         if ((wait == ME_WAIT_IDLE) && (*status == ME_STATUS_BUSY)) {
2091                 // Only runing process will interrupt this call. Events are signaled when status change. Extra timeout add for safe reason.
2092                 wait_event_interruptible_timeout(instance->wait_queue,
2093                                                  ((instance->status !=
2094                                                    ai_status_stream_run_wait)
2095                                                   && (instance->status !=
2096                                                       ai_status_stream_run)
2097                                                   && (instance->status !=
2098                                                       ai_status_stream_end_wait)),
2099                                                  LONG_MAX);
2100
2101                 if (instance->status != ai_status_stream_end) {
2102                         PDEBUG("Wait for IDLE canceled. %d\n",
2103                                instance->status);
2104                         err = ME_ERRNO_CANCELLED;
2105                 }
2106
2107                 if (signal_pending(current)) {
2108                         PERROR("Wait for IDLE interrupted.\n");
2109                         instance->status = ai_status_none;
2110                         ai_stop_isr(instance);
2111                         err = ME_ERRNO_SIGNAL;
2112                 }
2113
2114                 *status = ME_STATUS_IDLE;
2115         }
2116
2117         *values = me_circ_buf_values(&instance->circ_buf);
2118         PDEBUG("me_circ_buf_values(&instance->circ_buf)=%d.\n", *values);
2119
2120         ME_SUBDEVICE_EXIT;
2121
2122         return err;
2123 }
2124
2125 static int me4600_ai_io_stream_stop(me_subdevice_t *subdevice,
2126                                     struct file *filep,
2127                                     int stop_mode, int flags)
2128 {
2129 /**
2130  @note Stop is implemented only in blocking mode.
2131  @note Function return when state machine is stoped.
2132 */
2133         me4600_ai_subdevice_t *instance;
2134         unsigned long cpu_flags;
2135         uint32_t ctrl;
2136         int ret;
2137
2138         PDEBUG("executed. idx=0\n");
2139
2140         if (flags) {
2141                 PERROR("Invalid flag specified.\n");
2142                 return ME_ERRNO_INVALID_FLAGS;
2143         }
2144
2145         if ((stop_mode != ME_STOP_MODE_IMMEDIATE)
2146             && (stop_mode != ME_STOP_MODE_LAST_VALUE)) {
2147                 PERROR("Invalid stop mode specified.\n");
2148                 return ME_ERRNO_INVALID_STOP_MODE;
2149         }
2150
2151         instance = (me4600_ai_subdevice_t *) subdevice;
2152
2153         ME_SUBDEVICE_ENTER;
2154
2155         // Mark as stopping. => Software stop.
2156         instance->status = ai_status_stream_end_wait;
2157
2158         if (stop_mode == ME_STOP_MODE_IMMEDIATE) {
2159                 ret = ai_stop_immediately(instance);
2160
2161                 if (ret) {
2162                         PERROR("FSM is still busy.\n");
2163                         ME_SUBDEVICE_EXIT;
2164                         return ME_ERRNO_SUBDEVICE_BUSY;
2165                 }
2166                 instance->ai_control_task_flag = 0;
2167
2168         } else if (stop_mode == ME_STOP_MODE_LAST_VALUE) {
2169                 // Set stop bit in registry.
2170                 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
2171                 ctrl = inl(instance->ctrl_reg);
2172                 ctrl |= ME4600_AI_CTRL_BIT_STOP;
2173                 outl(ctrl, instance->ctrl_reg);
2174                 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2175                            instance->reg_base,
2176                            instance->ctrl_reg - instance->reg_base, ctrl);
2177                 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
2178
2179                 // Only runing process will interrupt this call. Events are signaled when status change.
2180                 wait_event_interruptible_timeout(instance->wait_queue,
2181                                                  (instance->status !=
2182                                                   ai_status_stream_end_wait),
2183                                                  LONG_MAX);
2184
2185                 if (instance->status != ai_status_stream_end) {
2186                         PDEBUG("Stopping stream canceled.\n");
2187                         ret = ME_ERRNO_CANCELLED;
2188                 }
2189
2190                 if (signal_pending(current)) {
2191                         PERROR("Stopping stream interrupted.\n");
2192                         instance->status = ai_status_none;
2193                         ret = ME_ERRNO_SIGNAL;
2194                 }
2195                 // End of work.
2196                 ai_stop_immediately(instance);
2197
2198         }
2199
2200         ret = ai_read_data_pooling(instance);
2201         if (ret > 0) {          // Everything fine. More datas put to software buffer.
2202                 instance->status = ai_status_stream_end;
2203                 ret = ME_ERRNO_SUCCESS;
2204                 // Signal that we put last data to software buffer.
2205                 wake_up_interruptible_all(&instance->wait_queue);
2206         } else if (ret == 0) {  // Everything fine. No more datas in FIFO.
2207                 instance->status = ai_status_stream_end;
2208                 ret = ME_ERRNO_SUCCESS;
2209         } else if (ret == -ME_ERRNO_RING_BUFFER_OVERFLOW) {     // Stop is unsuccessful, buffer is overflow.
2210                 instance->status = ai_status_stream_buffer_error;
2211                 ret = ME_ERRNO_SUCCESS;
2212         } else {                // Stop is unsuccessful
2213                 instance->status = ai_status_stream_end;
2214                 ret = -ret;
2215         }
2216
2217         ME_SUBDEVICE_EXIT;
2218
2219         return ret;
2220 }
2221
2222 static int me4600_ai_query_range_by_min_max(me_subdevice_t *subdevice,
2223                                             int unit,
2224                                             int *min,
2225                                             int *max, int *maxdata, int *range)
2226 {
2227         me4600_ai_subdevice_t *instance;
2228         int i;
2229         int r = -1;
2230         int diff = 21E6;
2231
2232         PDEBUG("executed. idx=0\n");
2233
2234         instance = (me4600_ai_subdevice_t *) subdevice;
2235
2236         if ((*max - *min) < 0) {
2237                 PERROR("Invalid minimum and maximum values specified.\n");
2238                 return ME_ERRNO_INVALID_MIN_MAX;
2239         }
2240
2241         if ((unit == ME_UNIT_VOLT) || (unit == ME_UNIT_ANY)) {
2242                 for (i = 0; i < instance->ranges_len; i++) {
2243                         if ((instance->ranges[i].min <= *min)
2244                             && ((instance->ranges[i].max + 1000) >= *max)) {
2245                                 if ((instance->ranges[i].max -
2246                                      instance->ranges[i].min) - (*max - *min) <
2247                                     diff) {
2248                                         r = i;
2249                                         diff =
2250                                             (instance->ranges[i].max -
2251                                              instance->ranges[i].min) - (*max -
2252                                                                          *min);
2253                                 }
2254                         }
2255                 }
2256
2257                 if (r < 0) {
2258                         PERROR("No matching range found.\n");
2259                         return ME_ERRNO_NO_RANGE;
2260                 } else {
2261                         *min = instance->ranges[r].min;
2262                         *max = instance->ranges[r].max;
2263                         *maxdata = ME4600_AI_MAX_DATA;
2264                         *range = r;
2265                 }
2266         } else {
2267                 PERROR("Invalid physical unit specified.\n");
2268                 return ME_ERRNO_INVALID_UNIT;
2269         }
2270
2271         return ME_ERRNO_SUCCESS;
2272 }
2273
2274 static int me4600_ai_query_number_ranges(me_subdevice_t *subdevice,
2275                                          int unit, int *count)
2276 {
2277         me4600_ai_subdevice_t *instance;
2278
2279         PDEBUG("executed. idx=0\n");
2280
2281         instance = (me4600_ai_subdevice_t *) subdevice;
2282
2283         if ((unit == ME_UNIT_VOLT) || (unit == ME_UNIT_ANY)) {
2284                 *count = instance->ranges_len;
2285         } else {
2286                 *count = 0;
2287         }
2288
2289         return ME_ERRNO_SUCCESS;
2290 }
2291
2292 static int me4600_ai_query_range_info(me_subdevice_t *subdevice,
2293                                       int range,
2294                                       int *unit,
2295                                       int *min, int *max, int *maxdata)
2296 {
2297         me4600_ai_subdevice_t *instance;
2298
2299         PDEBUG("executed. idx=0\n");
2300
2301         instance = (me4600_ai_subdevice_t *) subdevice;
2302
2303         if ((range < instance->ranges_len) && (range >= 0)) {
2304                 *unit = ME_UNIT_VOLT;
2305                 *min = instance->ranges[range].min;
2306                 *max = instance->ranges[range].max;
2307                 *maxdata = ME4600_AI_MAX_DATA;
2308         } else {
2309                 PERROR("Invalid range number specified.\n");
2310                 return ME_ERRNO_INVALID_RANGE;
2311         }
2312
2313         return ME_ERRNO_SUCCESS;
2314 }
2315
2316 static int me4600_ai_query_timer(me_subdevice_t *subdevice,
2317                                  int timer,
2318                                  int *base_frequency,
2319                                  long long *min_ticks, long long *max_ticks)
2320 {
2321         me4600_ai_subdevice_t *instance;
2322
2323         PDEBUG("executed. idx=0\n");
2324
2325         instance = (me4600_ai_subdevice_t *) subdevice;
2326
2327         switch (timer) {
2328
2329         case ME_TIMER_ACQ_START:
2330                 *base_frequency = ME4600_AI_BASE_FREQUENCY;
2331                 *min_ticks = ME4600_AI_MIN_ACQ_TICKS;
2332                 *max_ticks = ME4600_AI_MAX_ACQ_TICKS;
2333                 break;
2334
2335         case ME_TIMER_SCAN_START:
2336                 *base_frequency = ME4600_AI_BASE_FREQUENCY;
2337                 *min_ticks = ME4600_AI_MIN_SCAN_TICKS;
2338                 *max_ticks = ME4600_AI_MAX_SCAN_TICKS;
2339                 break;
2340
2341         case ME_TIMER_CONV_START:
2342                 *base_frequency = ME4600_AI_BASE_FREQUENCY;
2343                 *min_ticks = ME4600_AI_MIN_CHAN_TICKS;
2344                 *max_ticks = ME4600_AI_MAX_CHAN_TICKS;
2345                 break;
2346
2347         default:
2348                 PERROR("Invalid timer specified.(0x%04x)\n", timer);
2349
2350                 return ME_ERRNO_INVALID_TIMER;
2351         }
2352
2353         return ME_ERRNO_SUCCESS;
2354 }
2355
2356 static int me4600_ai_query_number_channels(me_subdevice_t *subdevice,
2357                                            int *number)
2358 {
2359         me4600_ai_subdevice_t *instance;
2360
2361         PDEBUG("executed. idx=0\n");
2362
2363         instance = (me4600_ai_subdevice_t *) subdevice;
2364         *number = instance->channels;
2365
2366         return ME_ERRNO_SUCCESS;
2367 }
2368
2369 static int me4600_ai_query_subdevice_type(me_subdevice_t *subdevice,
2370                                           int *type, int *subtype)
2371 {
2372         PDEBUG("executed. idx=0\n");
2373
2374         *type = ME_TYPE_AI;
2375         *subtype = ME_SUBTYPE_STREAMING;
2376
2377         return ME_ERRNO_SUCCESS;
2378 }
2379
2380 static int me4600_ai_query_subdevice_caps(me_subdevice_t *subdevice, int *caps)
2381 {
2382         PDEBUG("executed. idx=0\n");
2383
2384         *caps =
2385             ME_CAPS_AI_TRIG_SYNCHRONOUS | ME_CAPS_AI_FIFO |
2386             ME_CAPS_AI_FIFO_THRESHOLD;
2387
2388         return ME_ERRNO_SUCCESS;
2389 }
2390
2391 static int me4600_ai_query_subdevice_caps_args(struct me_subdevice *subdevice,
2392                                                int cap, int *args, int count)
2393 {
2394         me4600_ai_subdevice_t *instance;
2395         int err = ME_ERRNO_SUCCESS;
2396
2397         instance = (me4600_ai_subdevice_t *) subdevice;
2398
2399         PDEBUG("executed. idx=0\n");
2400
2401         if (count != 1) {
2402                 PERROR("Invalid capability argument count.\n");
2403                 return ME_ERRNO_INVALID_CAP_ARG_COUNT;
2404         }
2405
2406         switch (cap) {
2407         case ME_CAP_AI_FIFO_SIZE:
2408                 args[0] = ME4600_AI_FIFO_COUNT;
2409                 break;
2410
2411         case ME_CAP_AI_BUFFER_SIZE:
2412                 args[0] =
2413                     (instance->circ_buf.buf) ? ME4600_AI_CIRC_BUF_COUNT : 0;
2414                 break;
2415
2416         default:
2417                 PERROR("Invalid capability.\n");
2418                 err = ME_ERRNO_INVALID_CAP;
2419                 args[0] = 0;
2420         }
2421
2422         return err;
2423 }
2424
2425 void ai_limited_isr(me4600_ai_subdevice_t *instance, const uint32_t irq_status,
2426                     const uint32_t ctrl_status)
2427 {
2428         int to_read;
2429
2430         if (!instance->fifo_irq_threshold) {    //No threshold provided. SC ends work. HF need reseting.
2431                 if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2432                         if (ai_read_data(instance, instance->ISM.next) != instance->ISM.next) { //ERROR!
2433                                 PERROR
2434                                     ("Limited amounts aqusition with TH=0: Circular buffer full!\n");
2435                                 instance->status =
2436                                     ai_status_stream_buffer_error;
2437                         } else {
2438                                 instance->status = ai_status_stream_end;
2439                         }
2440                         //End of work.
2441                         ai_stop_isr(instance);
2442                 } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2443                         instance->ISM.global_read += ME4600_AI_FIFO_HALF;
2444
2445                         if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) {       //ERROR!
2446                                 PERROR
2447                                     ("Limited amounts aqusition with TH = 0: Circular buffer full!\n");
2448                                 //End of work.
2449                                 ai_stop_isr(instance);
2450                                 instance->status =
2451                                     ai_status_stream_buffer_error;
2452                         } else {
2453                                 //Continue.
2454                                 ai_limited_ISM(instance, irq_status);
2455                         }
2456                 }
2457                 //Signal user.
2458                 wake_up_interruptible_all(&instance->wait_queue);
2459         } else                  //if(instance->fifo_irq_threshold)
2460         {
2461                 if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2462                         instance->ISM.read = 0;
2463                         if ((instance->fifo_irq_threshold < ME4600_AI_FIFO_HALF)
2464                             && (!(ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA)))
2465                         {
2466                                 to_read =
2467                                     ME4600_AI_FIFO_HALF -
2468                                     (ME4600_AI_FIFO_HALF %
2469                                      instance->fifo_irq_threshold);
2470                                 PDEBUG
2471                                     ("Limited amounts aqusition with TH != 0: Not fast enough data aqusition! correction=%d\n",
2472                                      to_read);
2473                         } else {
2474                                 to_read = instance->ISM.next;
2475                         }
2476                         instance->ISM.global_read += to_read;
2477
2478                         ai_reschedule_SC(instance);
2479
2480                         if (ai_read_data(instance, to_read) != to_read) {       //ERROR!
2481                                 PERROR
2482                                     ("Limited amounts aqusition with TH != 0: Circular buffer full!\n");
2483                                 //End of work.
2484                                 ai_stop_isr(instance);
2485                                 instance->status =
2486                                     ai_status_stream_buffer_error;
2487                         } else {
2488                                 //Continue.
2489                                 ai_limited_ISM(instance, irq_status);
2490                         }
2491
2492                         //Signal user.
2493                         wake_up_interruptible_all(&instance->wait_queue);
2494                 } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2495                         instance->ISM.read += ME4600_AI_FIFO_HALF;
2496                         instance->ISM.global_read += ME4600_AI_FIFO_HALF;
2497
2498                         if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) {       //ERROR!
2499                                 PERROR
2500                                     ("Limited amounts aqusition with TH != 0: Circular buffer full!\n");
2501                                 ai_stop_isr(instance);
2502
2503                                 instance->status =
2504                                     ai_status_stream_buffer_error;
2505                                 //Signal user.
2506                                 wake_up_interruptible_all(&instance->
2507                                                           wait_queue);
2508                         } else {
2509                                 //Countinue.
2510                                 ai_limited_ISM(instance, irq_status);
2511                         }
2512                 }
2513
2514                 if (instance->ISM.global_read >= instance->data_required) {     //End of work. Next paranoid pice of code: '>=' instead od '==' only to be sure.
2515                         ai_stop_isr(instance);
2516                         if (instance->status < ai_status_stream_end) {
2517                                 instance->status = ai_status_stream_end;
2518                         }
2519 #ifdef MEDEBUG_ERROR
2520                         if (instance->ISM.global_read > instance->data_required) {      //This is security check case. This should never ever happend!
2521                                 PERROR
2522                                     ("Limited amounts aqusition: Read more data than necessary! data_required=%d < read=%d\n",
2523                                      instance->data_required,
2524                                      instance->ISM.global_read);
2525                                 //Signal error (warning??).
2526                                 instance->status = ai_status_stream_error;
2527                         }
2528 #endif
2529                 }
2530         }
2531 }
2532
2533 void ai_infinite_isr(me4600_ai_subdevice_t *instance,
2534                      const uint32_t irq_status, const uint32_t ctrl_status)
2535 {
2536         int to_read;
2537
2538         if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {    //next chunck of data -> read fifo
2539                 //Set new state in ISM.
2540                 if ((instance->fifo_irq_threshold < ME4600_AI_FIFO_HALF) && (!(ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA))) {  //There is more data than we ecpected. Propably we aren't fast enough. Read as many as possible.
2541                         if (instance->fifo_irq_threshold) {
2542                                 to_read =
2543                                     ME4600_AI_FIFO_HALF -
2544                                     (ME4600_AI_FIFO_HALF %
2545                                      instance->fifo_irq_threshold);
2546                                 if (to_read > instance->fifo_irq_threshold) {
2547                                         PDEBUG
2548                                             ("Infinite aqusition: Not fast enough data aqusition! TH != 0: correction=%d\n",
2549                                              to_read);
2550                                 }
2551                         } else {        //No threshold specified.
2552                                 to_read = ME4600_AI_FIFO_HALF;
2553                         }
2554                 } else {
2555                         to_read = instance->ISM.next;
2556                 }
2557
2558                 instance->ISM.read += to_read;
2559
2560                 //Get data
2561                 if (ai_read_data(instance, to_read) != to_read) {       //ERROR!
2562                         PERROR("Infinite aqusition: Circular buffer full!\n");
2563                         ai_stop_isr(instance);
2564                         instance->status = ai_status_stream_buffer_error;
2565                 } else {
2566                         ai_infinite_ISM(instance);
2567                         instance->ISM.global_read += instance->ISM.read;
2568                         instance->ISM.read = 0;
2569                 }
2570
2571                 //Signal data to user
2572                 wake_up_interruptible_all(&instance->wait_queue);
2573         } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {  //fifo is half full -> read fifo       Large blocks only!
2574                 instance->ISM.read += ME4600_AI_FIFO_HALF;
2575
2576                 if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) {       //ERROR!
2577                         PERROR("Infinite aqusition: Circular buffer full!\n");
2578                         ai_stop_isr(instance);
2579                         instance->status = ai_status_stream_buffer_error;
2580
2581                         //Signal it.
2582                         wake_up_interruptible_all(&instance->wait_queue);
2583                 } else {
2584                         ai_infinite_ISM(instance);
2585                 }
2586         }
2587 }
2588
2589 static irqreturn_t me4600_ai_isr(int irq, void *dev_id)
2590 {                               /// @note This is time critical function!
2591         uint32_t irq_status;
2592         uint32_t ctrl_status;
2593         me4600_ai_subdevice_t *instance = dev_id;
2594         //int to_read;
2595
2596         PDEBUG("executed. idx=0\n");
2597
2598         if (irq != instance->irq) {
2599                 PERROR("Incorrect interrupt num: %d.\n", irq);
2600                 return IRQ_NONE;
2601         }
2602
2603         irq_status = inl(instance->irq_status_reg);
2604         if (!
2605             (irq_status &
2606              (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC))) {
2607 #ifdef MEDEBUG_INFO
2608                 if ((irq_status & (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC | ME4600_IRQ_STATUS_BIT_LE)) == ME4600_IRQ_STATUS_BIT_LE) {   //This is security check case. LE is unused. This should never ever happend.
2609                         PINFO
2610                             ("%ld Shared interrupt. %s(): irq_status_reg=LE_IRQ\n",
2611                              jiffies, __func__);
2612                 } else {
2613                         PINFO
2614                             ("%ld Shared interrupt. %s(): irq_status_reg=0x%04X\n",
2615                              jiffies, __func__, irq_status);
2616                 }
2617 #endif
2618                 return IRQ_NONE;
2619         }
2620
2621         if (!instance->circ_buf.buf) {  //Security check.
2622                 PERROR_CRITICAL("CIRCULAR BUFFER NOT EXISTS!\n");
2623                 ai_stop_isr(instance);
2624                 return IRQ_HANDLED;
2625         }
2626         //Get the status register.
2627         ctrl_status = inl(instance->status_reg);
2628
2629 #ifdef MEDEBUG_INFO
2630         if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF)
2631                 PINFO("HF interrupt active\n");
2632         if (irq_status & ME4600_IRQ_STATUS_BIT_SC)
2633                 PINFO("SC interrupt active\n");
2634         if (irq_status & ME4600_IRQ_STATUS_BIT_LE)
2635                 PINFO("LE interrupt active\n");
2636 #endif
2637
2638         //This is safety check!
2639         if ((irq_status & ME4600_IRQ_STATUS_BIT_AI_HF)
2640             && (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA)) {
2641                 PDEBUG("HF interrupt active but FIFO under half\n");
2642                 //Reset HF interrupt latch.
2643                 spin_lock(instance->ctrl_reg_lock);
2644                 outl(ctrl_status | ME4600_AI_CTRL_BIT_HF_IRQ_RESET,
2645                      instance->ctrl_reg);
2646                 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2647                            instance->reg_base,
2648                            instance->ctrl_reg - instance->reg_base,
2649                            ctrl_status);
2650                 outl(ctrl_status, instance->ctrl_reg);
2651                 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2652                            instance->reg_base,
2653                            instance->ctrl_reg - instance->reg_base,
2654                            ctrl_status);
2655                 spin_unlock(instance->ctrl_reg_lock);
2656                 return IRQ_HANDLED;
2657         }
2658 #ifdef MEDEBUG_INFO
2659         PINFO("STATUS_BIT_FSM=%s.\n",
2660               (ctrl_status & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2661
2662         PINFO("STATUS_BIT_EF_CHANNEL=%s.\n",
2663               (ctrl_status & ME4600_AI_STATUS_BIT_EF_CHANNEL) ? "not empty" :
2664               "empty");
2665         PINFO("STATUS_BIT_HF_CHANNEL=%s.\n",
2666               (ctrl_status & ME4600_AI_STATUS_BIT_HF_CHANNEL) ? " < HF" :
2667               " > HF");
2668         PINFO("STATUS_BIT_FF_CHANNEL=%s.\n",
2669               (ctrl_status & ME4600_AI_STATUS_BIT_FF_CHANNEL) ? "not full" :
2670               "full");
2671
2672         PINFO("STATUS_BIT_EF_DATA=%s.\n",
2673               (ctrl_status & ME4600_AI_STATUS_BIT_EF_DATA) ? "not empty" :
2674               "empty");
2675         PINFO("STATUS_BIT_HF_DATA=%s.\n",
2676               (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA) ? " < HF" : " > HF");
2677         PINFO("STATUS_BIT_FF_DATA=%s.\n",
2678               (ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA) ? "not full" :
2679               "full");
2680
2681         PINFO("CTRL_BIT_HF_IRQ=%s.\n",
2682               (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ) ? "enable" : "disable");
2683         PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2684               (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" :
2685               "work");
2686         PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2687               (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2688         PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2689               (ctrl_status & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2690         PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2691               (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" :
2692               "work");
2693 #endif
2694
2695         //Look for overflow error.
2696         if (!(ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA)) {
2697                 //FIFO is full. Read datas and reset all settings.
2698                 PERROR("FIFO overflow.\n");
2699                 ai_read_data(instance, ME4600_AI_FIFO_COUNT);
2700                 ai_stop_isr(instance);
2701
2702                 instance->status = ai_status_stream_fifo_error;
2703                 //Signal it.
2704                 wake_up_interruptible_all(&instance->wait_queue);
2705
2706                 return IRQ_HANDLED;
2707         }
2708
2709         if (!instance->data_required) { //This is infinite aqusition.
2710 #ifdef MEDEBUG_ERROR
2711                 if ((irq_status &
2712                      (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC))
2713                     ==
2714                     (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC)) {
2715                         ///In infinite mode only one interrupt source should be reported!
2716                         PERROR
2717                             ("Error in ISM! Infinite aqusition: HF and SC interrupts active! threshold=%d next=%d ctrl=0x%04X irq_status_reg=0x%04X",
2718                              instance->fifo_irq_threshold, instance->ISM.next,
2719                              ctrl_status, irq_status);
2720                 }
2721 #endif
2722
2723                 ai_infinite_isr(instance, irq_status, ctrl_status);
2724
2725 #ifdef MEDEBUG_INFO
2726                 ctrl_status = inl(instance->ctrl_reg);
2727 #endif
2728         } else {
2729
2730                 ai_limited_isr(instance, irq_status, ctrl_status);
2731                 ctrl_status = inl(instance->status_reg);
2732                 if (!(ctrl_status & (ME4600_AI_STATUS_BIT_HF_DATA | ME4600_AI_CTRL_BIT_HF_IRQ_RESET))) {        //HF active, but we have more than half already => HF will never come
2733                         PDEBUG
2734                             ("MISSED HF. data_required=%d ISM.read=%d ISM.global=%d ISM.next=%d\n",
2735                              instance->data_required, instance->ISM.read,
2736                              instance->ISM.global_read, instance->ISM.next);
2737                         ai_limited_isr(instance, ME4600_IRQ_STATUS_BIT_AI_HF,
2738                                        ctrl_status);
2739                 }
2740         }
2741
2742 #ifdef MEDEBUG_INFO
2743         PINFO("STATUS_BIT_FSM=%s.\n",
2744               (ctrl_status & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2745
2746         PINFO("STATUS_BIT_EF_CHANNEL=%s.\n",
2747               (ctrl_status & ME4600_AI_STATUS_BIT_EF_CHANNEL) ? "not empty" :
2748               "empty");
2749         PINFO("STATUS_BIT_HF_CHANNEL=%s.\n",
2750               (ctrl_status & ME4600_AI_STATUS_BIT_HF_CHANNEL) ? " < HF" :
2751               " > HF");
2752         PINFO("STATUS_BIT_FF_CHANNEL=%s.\n",
2753               (ctrl_status & ME4600_AI_STATUS_BIT_FF_CHANNEL) ? "not full" :
2754               "full");
2755
2756         PINFO("STATUS_BIT_EF_DATA=%s.\n",
2757               (ctrl_status & ME4600_AI_STATUS_BIT_EF_DATA) ? "not empty" :
2758               "empty");
2759         PINFO("STATUS_BIT_HF_DATA=%s.\n",
2760               (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA) ? " < HF" : " > HF");
2761         PINFO("STATUS_BIT_FF_DATA=%s.\n",
2762               (ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA) ? "not full" :
2763               "full");
2764
2765         PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2766               (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" :
2767               "work");
2768         PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2769               (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2770         PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2771               (ctrl_status & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2772         PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2773               (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" :
2774               "work");
2775         PINFO("%ld END\n", jiffies);
2776 #endif
2777
2778         return IRQ_HANDLED;
2779 }
2780
2781 /** @brief Stop aqusation of data. Reset interrupts' laches. Clear data's FIFO.
2782 *
2783 * @param instance The subdevice instance (pointer).
2784 */
2785 inline void ai_stop_isr(me4600_ai_subdevice_t *instance)
2786 {                               /// @note This is soft time critical function!
2787         register uint32_t tmp;
2788
2789         spin_lock(instance->ctrl_reg_lock);
2790         //Stop all. Reset interrupt laches. Reset data FIFO.
2791         tmp = inl(instance->ctrl_reg);
2792         tmp |=
2793             (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_HF_IRQ_RESET
2794              | ME4600_AI_CTRL_BIT_LE_IRQ_RESET |
2795              ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
2796         tmp &= ~ME4600_AI_CTRL_BIT_DATA_FIFO;
2797         outl(tmp, instance->ctrl_reg);
2798         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2799                    instance->ctrl_reg - instance->reg_base, tmp);
2800         spin_unlock(instance->ctrl_reg_lock);
2801 }
2802
2803 /** @brief Copy data from fifo to circular buffer.
2804 *
2805 * @param instance The subdevice instance (pointer).
2806 * @param count The number of requested data.
2807 *
2808 * @return On success: Number of copied values.
2809 * @return On error: -ME_ERRNO_RING_BUFFER_OVERFLOW.
2810 */
2811 static inline int ai_read_data(me4600_ai_subdevice_t *instance,
2812                                const int count)
2813 {                               /// @note This is time critical function!
2814         int c = count;
2815         int empty_space;
2816         int copied = 0;
2817         int i, j;
2818
2819         empty_space = me_circ_buf_space_to_end(&instance->circ_buf);
2820         if (empty_space <= 0) {
2821                 PDEBUG("Circular buffer full.\n");
2822                 return -ME_ERRNO_RING_BUFFER_OVERFLOW;
2823         }
2824
2825         if (empty_space < c) {  //Copy first part. Max to end of buffer.
2826                 PDEBUG
2827                     ("Try to copy %d values from FIFO to circular buffer (pass 1).\n",
2828                      empty_space);
2829                 for (i = 0; i < empty_space; i++) {
2830                         *(instance->circ_buf.buf + instance->circ_buf.head) =
2831                             (inw(instance->data_reg) ^ 0x8000);
2832                         instance->circ_buf.head++;
2833                 }
2834                 instance->circ_buf.head &= instance->circ_buf.mask;
2835                 c -= empty_space;
2836                 copied = empty_space;
2837
2838                 empty_space = me_circ_buf_space_to_end(&instance->circ_buf);
2839         }
2840
2841         if (empty_space > 0) {
2842                 j = (empty_space < c) ? empty_space : c;
2843                 PDEBUG
2844                     ("Try to copy %d values from FIFO to circular buffer (pass 2).\n",
2845                      c);
2846                 for (i = 0; i < j; i++) {
2847                         *(instance->circ_buf.buf + instance->circ_buf.head) =
2848                             (inw(instance->data_reg) ^ 0x8000);
2849                         instance->circ_buf.head++;
2850                 }
2851                 instance->circ_buf.head &= instance->circ_buf.mask;
2852                 copied += j;
2853         }
2854         return copied;
2855 }
2856
2857 inline void ai_infinite_ISM(me4600_ai_subdevice_t *instance)
2858 {                               /// @note This is time critical function!
2859         register volatile uint32_t ctrl_set, ctrl_reset, tmp;
2860
2861         if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) {     // Only sample counter with reloadnig is working. Reset it.
2862                 PINFO
2863                     ("Only sample counter with reloadnig is working. Reset it.\n");
2864                 ctrl_set = ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2865                 ctrl_reset = ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2866         } else if (instance->fifo_irq_threshold == instance->ISM.read) {        //This is SC interrupt for large block. The whole section is done. Reset SC_IRQ an HF_IRQ and start everything again from beginning.
2867                 PINFO
2868                     ("This is SC interrupt for large block. The whole section is done. Reset SC_IRQ an HF_IRQ and start everything again from beginning.\n");
2869                 ctrl_set =
2870                     ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
2871                     ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2872                 ctrl_reset =
2873                     ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
2874                       ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
2875         } else if (instance->fifo_irq_threshold >= (ME4600_AI_FIFO_MAX_SC + instance->ISM.read)) {      //This is HF interrupt for large block.The next interrupt should be from HF, also. Reset HF.
2876                 PINFO
2877                     ("This is HF interrupt for large block.The next interrupt should be from HF, also. Reset HF.\n");
2878                 ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2879                 ctrl_reset = ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2880         } else {                //This is HF interrupt for large block.The next interrupt should be from SC. Don't reset HF!
2881                 PINFO
2882                     ("This is HF interrupt for large block.The next interrupt should be from SC. Don't reset HF!\n");
2883                 ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2884                 ctrl_reset = 0xFFFFFFFF;
2885         }
2886
2887         //Reset interrupt latch.
2888         spin_lock(instance->ctrl_reg_lock);
2889         tmp = inl(instance->ctrl_reg);
2890         PINFO("ctrl=0x%x ctrl_set=0x%x ctrl_reset=0x%x\n", tmp, ctrl_set,
2891               ctrl_reset);
2892         tmp |= ctrl_set;
2893         outl(tmp, instance->ctrl_reg);
2894         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2895                    instance->ctrl_reg - instance->reg_base, tmp);
2896         if (ctrl_reset != 0xFFFFFFFF) {
2897                 outl(tmp & ctrl_reset, instance->ctrl_reg);
2898                 PDEBUG_REG("ctrl_reset outl(0x%lX+0x%lX)=0x%x\n",
2899                            instance->reg_base,
2900                            instance->ctrl_reg - instance->reg_base,
2901                            tmp & ctrl_reset);
2902         }
2903         spin_unlock(instance->ctrl_reg_lock);
2904
2905 }
2906
2907 inline void ai_limited_ISM(me4600_ai_subdevice_t *instance,
2908                            uint32_t irq_status)
2909 {                               /// @note This is time critical function!
2910         register volatile uint32_t ctrl_set, ctrl_reset = 0xFFFFFFFF, tmp;
2911
2912         if (!instance->fifo_irq_threshold) {    //No threshold provided. SC ends work.
2913                 PINFO("No threshold provided. SC ends work.\n");
2914                 ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2915                 if (instance->data_required > (ME4600_AI_FIFO_COUNT - 1 + instance->ISM.global_read)) { //HF need reseting.
2916                         ctrl_reset &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2917                 }
2918         } else                  //if(instance->fifo_irq_threshold)
2919         {
2920                 if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2921                         PINFO("Threshold provided. Clear HF latch.\n");
2922                         ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2923
2924                         if (instance->fifo_irq_threshold >= (ME4600_AI_FIFO_MAX_SC + instance->ISM.read)) {     //This is not the last one. HF need reseting.
2925                                 PINFO
2926                                     ("The next interrupt is HF. HF need be activating.\n");
2927                                 ctrl_reset = ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2928                         }
2929                 }
2930
2931                 if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2932                         PINFO("Threshold provided. Restart SC.\n");
2933                         ctrl_set = ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2934                         ctrl_reset &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2935
2936                         if (instance->fifo_irq_threshold >= ME4600_AI_FIFO_MAX_SC) {    //This is not the last one. HF need to be activating.
2937                                 PINFO
2938                                     ("The next interrupt is HF. HF need to be activating.\n");
2939                                 ctrl_reset &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2940                         }
2941                 }
2942         }
2943
2944         //Reset interrupt latch.
2945         spin_lock(instance->ctrl_reg_lock);
2946         tmp = inl(instance->ctrl_reg);
2947         tmp |= ctrl_set;
2948         outl(tmp, instance->ctrl_reg);
2949         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2950                    instance->ctrl_reg - instance->reg_base, tmp);
2951
2952         if (ctrl_reset != 0xFFFFFFFF) {
2953                 outl(tmp & ctrl_reset, instance->ctrl_reg);
2954                 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2955                            instance->reg_base,
2956                            instance->ctrl_reg - instance->reg_base,
2957                            tmp & ctrl_reset);
2958         }
2959         spin_unlock(instance->ctrl_reg_lock);
2960
2961 }
2962
2963 /** @brief Last chunck of datas. We must reschedule sample counter.
2964 *       @note Last chunck.
2965 *       Leaving SC_RELOAD doesn't do any harm, but in some bad case can make extra interrupts.
2966 *       @warning When threshold is wrongly set some IRQ are lost.(!!!)
2967 */
2968 inline void ai_reschedule_SC(me4600_ai_subdevice_t *instance)
2969 {
2970         register uint32_t rest;
2971
2972         if (instance->data_required <= instance->ISM.global_read)
2973                 return;
2974
2975         rest = instance->data_required - instance->ISM.global_read;
2976         if (rest < instance->fifo_irq_threshold) {      //End of work soon ....
2977                 PDEBUG("Rescheduling SC from %d to %d.\n",
2978                        instance->fifo_irq_threshold, rest);
2979                 /// @note Write new value to SC <==  DANGER! This is not safe solution! We can miss some inputs.
2980                 outl(rest, instance->sample_counter_reg);
2981                 PDEBUG_REG("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
2982                            instance->reg_base,
2983                            instance->sample_counter_reg - instance->reg_base,
2984                            rest);
2985                 instance->fifo_irq_threshold = rest;
2986
2987                 if (rest < ME4600_AI_FIFO_MAX_SC) {
2988                         instance->ISM.next = rest;
2989                 } else {
2990                         instance->ISM.next = rest % ME4600_AI_FIFO_HALF;
2991                         if (instance->ISM.next + ME4600_AI_FIFO_HALF <
2992                             ME4600_AI_FIFO_MAX_SC) {
2993                                 instance->ISM.next += ME4600_AI_FIFO_HALF;
2994                         }
2995                 }
2996         }
2997 }
2998
2999 /** Start the ISM. All must be reseted before enter to this function. */
3000 inline void ai_data_acquisition_logic(me4600_ai_subdevice_t *instance)
3001 {
3002         register uint32_t tmp;
3003
3004         if (!instance->data_required) { //This is infinite aqusition.
3005                 if (!instance->fifo_irq_threshold) {    //No threshold provided. Set SC to 0.5*FIFO. Clear the SC's latch.
3006                         //Set the sample counter
3007                         outl(ME4600_AI_FIFO_HALF, instance->sample_counter_reg);
3008                         PDEBUG_REG
3009                             ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3010                              instance->reg_base,
3011                              instance->sample_counter_reg - instance->reg_base,
3012                              ME4600_AI_FIFO_HALF);
3013                 } else {        //Threshold provided. Set SC to treshold. Clear the SC's latch.
3014                         //Set the sample counter
3015                         outl(instance->fifo_irq_threshold,
3016                              instance->sample_counter_reg);
3017                         PDEBUG_REG
3018                             ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3019                              instance->reg_base,
3020                              instance->sample_counter_reg - instance->reg_base,
3021                              instance->fifo_irq_threshold);
3022                 }
3023
3024                 if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) {     //Enable only sample counter's interrupt. Set reload bit. Clear the SC's latch.
3025                         spin_lock(instance->ctrl_reg_lock);
3026                         tmp = inl(instance->ctrl_reg);
3027                         tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3028                         tmp &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
3029                         outl(tmp, instance->ctrl_reg);
3030                         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3031                                    instance->reg_base,
3032                                    instance->ctrl_reg - instance->reg_base,
3033                                    tmp);
3034                         spin_unlock(instance->ctrl_reg_lock);
3035                         if (!instance->fifo_irq_threshold) {    //No threshold provided. Set ISM.next to 0.5*FIFO.
3036                                 instance->ISM.next = ME4600_AI_FIFO_HALF;
3037                         } else {        //Threshold provided. Set ISM.next to treshold.
3038                                 instance->ISM.next =
3039                                     instance->fifo_irq_threshold;
3040                         }
3041                 } else {        //Enable sample counter's and HF's interrupts.
3042                         spin_lock(instance->ctrl_reg_lock);
3043                         tmp = inl(instance->ctrl_reg);
3044                         tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3045                         tmp &=
3046                             ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3047                               ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
3048                         outl(tmp, instance->ctrl_reg);
3049                         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3050                                    instance->reg_base,
3051                                    instance->ctrl_reg - instance->reg_base,
3052                                    tmp);
3053                         spin_unlock(instance->ctrl_reg_lock);
3054
3055                         instance->ISM.next =
3056                             instance->fifo_irq_threshold % ME4600_AI_FIFO_HALF;
3057                         if (instance->ISM.next + ME4600_AI_FIFO_HALF <
3058                             ME4600_AI_FIFO_MAX_SC) {
3059                                 instance->ISM.next += ME4600_AI_FIFO_HALF;
3060                         }
3061                 }
3062         } else {                //This aqusition is limited to set number of data.
3063                 if (instance->fifo_irq_threshold >= instance->data_required) {  //Stupid situation.
3064                         instance->fifo_irq_threshold = 0;
3065                         PDEBUG
3066                             ("Stupid situation: data_required(%d) < threshold(%d).\n",
3067                              instance->fifo_irq_threshold,
3068                              instance->data_required);
3069                 }
3070
3071                 if (!instance->fifo_irq_threshold) {    //No threshold provided. Easy case: HF=read and SC=end.
3072                         //Set the sample counter to data_required.
3073                         outl(instance->data_required,
3074                              instance->sample_counter_reg);
3075                         PDEBUG_REG
3076                             ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3077                              instance->reg_base,
3078                              instance->sample_counter_reg - instance->reg_base,
3079                              instance->data_required);
3080
3081                         //Reset the latches of sample counter and HF (if SC>FIFO).
3082                         //No SC reload!
3083                         spin_lock(instance->ctrl_reg_lock);
3084                         tmp = inl(instance->ctrl_reg);
3085                         tmp &=
3086                             ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3087                               ME4600_AI_CTRL_BIT_SC_RELOAD);
3088                         if (instance->data_required >
3089                             (ME4600_AI_FIFO_COUNT - 1)) {
3090                                 tmp &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
3091                                 instance->ISM.next =
3092                                     instance->data_required %
3093                                     ME4600_AI_FIFO_HALF;
3094                                 instance->ISM.next += ME4600_AI_FIFO_HALF;
3095
3096                         } else {
3097                                 instance->ISM.next = instance->data_required;
3098                         }
3099                         outl(tmp, instance->ctrl_reg);
3100                         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3101                                    instance->reg_base,
3102                                    instance->ctrl_reg - instance->reg_base,
3103                                    tmp);
3104                         spin_unlock(instance->ctrl_reg_lock);
3105
3106                 } else {        //The most general case. We have concret numbe of required data and threshold. SC=TH
3107                         //Set the sample counter to threshold.
3108                         outl(instance->fifo_irq_threshold,
3109                              instance->sample_counter_reg);
3110                         PDEBUG_REG
3111                             ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3112                              instance->reg_base,
3113                              instance->sample_counter_reg - instance->reg_base,
3114                              instance->fifo_irq_threshold);
3115
3116                         spin_lock(instance->ctrl_reg_lock);
3117                         tmp = inl(instance->ctrl_reg);
3118                         //In this moment we are sure that SC will come more than once.
3119                         tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3120
3121                         if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) {     //The threshold is so small that we do need HF.
3122                                 tmp &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
3123                                 instance->ISM.next =
3124                                     instance->fifo_irq_threshold;
3125                         } else {        //The threshold is large. The HF must be use.
3126                                 tmp &=
3127                                     ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3128                                       ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
3129                                 instance->ISM.next =
3130                                     instance->fifo_irq_threshold %
3131                                     ME4600_AI_FIFO_HALF;
3132                                 if (instance->ISM.next + ME4600_AI_FIFO_HALF <
3133                                     ME4600_AI_FIFO_MAX_SC) {
3134                                         instance->ISM.next +=
3135                                             ME4600_AI_FIFO_HALF;
3136                                 }
3137                         }
3138                         outl(tmp, instance->ctrl_reg);
3139                         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3140                                    instance->reg_base,
3141                                    instance->ctrl_reg - instance->reg_base,
3142                                    tmp);
3143                         spin_unlock(instance->ctrl_reg_lock);
3144                 }
3145         }
3146 }
3147
3148 static int ai_mux_toggler(me4600_ai_subdevice_t *instance)
3149 {
3150         uint32_t tmp;
3151
3152         PDEBUG("executed. idx=0\n");
3153
3154         outl(0, instance->scan_pre_timer_low_reg);
3155         PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
3156                    instance->reg_base,
3157                    instance->scan_pre_timer_low_reg - instance->reg_base, 0);
3158         outl(0, instance->scan_pre_timer_high_reg);
3159         PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
3160                    instance->reg_base,
3161                    instance->scan_pre_timer_high_reg - instance->reg_base, 0);
3162         outl(0, instance->scan_timer_low_reg);
3163         PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
3164                    instance->reg_base,
3165                    instance->scan_timer_low_reg - instance->reg_base, 0);
3166         outl(0, instance->scan_timer_high_reg);
3167         PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
3168                    instance->reg_base,
3169                    instance->scan_timer_high_reg - instance->reg_base, 0);
3170         outl(65, instance->chan_timer_reg);
3171         PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
3172                    instance->reg_base,
3173                    instance->chan_timer_reg - instance->reg_base, 65);
3174         outl(65, instance->chan_pre_timer_reg);
3175         PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
3176                    instance->reg_base,
3177                    instance->chan_pre_timer_reg - instance->reg_base, 65);
3178
3179         // Turn on internal reference.
3180         tmp = inl(instance->ctrl_reg);
3181         tmp |= ME4600_AI_CTRL_BIT_FULLSCALE;
3182         outl(tmp, instance->ctrl_reg);
3183         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3184                    instance->ctrl_reg - instance->reg_base, tmp);
3185
3186         // Clear data and channel fifo.
3187         tmp &=
3188             ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
3189         outl(tmp, instance->ctrl_reg);
3190         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3191                    instance->ctrl_reg - instance->reg_base, tmp);
3192         tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
3193         outl(tmp, instance->ctrl_reg);
3194         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3195                    instance->ctrl_reg - instance->reg_base, tmp);
3196
3197         // Write channel entry.
3198         outl(ME4600_AI_LIST_INPUT_DIFFERENTIAL |
3199              ME4600_AI_LIST_RANGE_UNIPOLAR_2_5 | 31,
3200              instance->channel_list_reg);
3201         PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
3202                    instance->reg_base,
3203                    instance->channel_list_reg - instance->reg_base,
3204                    ME4600_AI_LIST_INPUT_DIFFERENTIAL |
3205                    ME4600_AI_LIST_RANGE_UNIPOLAR_2_5 | 31);
3206
3207         // Start conversion.
3208         inl(instance->start_reg);
3209         PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
3210                    instance->start_reg - instance->reg_base);
3211         udelay(10);
3212
3213         // Clear data and channel fifo.
3214         tmp &=
3215             ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
3216         outl(tmp, instance->ctrl_reg);
3217         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3218                    instance->ctrl_reg - instance->reg_base, tmp);
3219         tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
3220         outl(tmp, instance->ctrl_reg);
3221         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3222                    instance->ctrl_reg - instance->reg_base, tmp);
3223
3224         // Write channel entry.
3225         // ME4600_AI_LIST_INPUT_SINGLE_ENDED | ME4600_AI_LIST_RANGE_BIPOLAR_10 <= 0x0000
3226         outl(ME4600_AI_LIST_INPUT_SINGLE_ENDED |
3227              ME4600_AI_LIST_RANGE_BIPOLAR_10, instance->channel_list_reg);
3228         PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
3229                    instance->reg_base,
3230                    instance->channel_list_reg - instance->reg_base,
3231                    ME4600_AI_LIST_INPUT_SINGLE_ENDED |
3232                    ME4600_AI_LIST_RANGE_BIPOLAR_10);
3233
3234         // Start conversion.
3235         inl(instance->start_reg);
3236         PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
3237                    instance->start_reg - instance->reg_base);
3238         udelay(10);
3239
3240         // Clear control register.
3241         tmp &= (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET);
3242         outl(tmp, instance->ctrl_reg);
3243         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3244                    instance->ctrl_reg - instance->reg_base, tmp);
3245
3246         return ME_ERRNO_SUCCESS;
3247 }
3248
3249 /** @brief Copy rest of data from fifo to circular buffer.
3250 * @note Helper for STOP command. After FSM is stopped.
3251 * @note This is slow function that copy all remainig data from FIFO to buffer.
3252 *
3253 * @param instance The subdevice instance (pointer).
3254 *
3255 * @return On success: Number of copied values.
3256 * @return On error: Negative error code -ME_ERRNO_RING_BUFFER_OVERFLOW.
3257 */
3258 static inline int ai_read_data_pooling(me4600_ai_subdevice_t *instance)
3259 {                               /// @note This is time critical function!
3260         int empty_space;
3261         int copied = 0;
3262         int status = ME_ERRNO_SUCCESS;
3263
3264         PDEBUG("Space left in circular buffer = %d.\n",
3265                me_circ_buf_space(&instance->circ_buf));
3266
3267         while ((empty_space = me_circ_buf_space(&instance->circ_buf))) {
3268                 if (!(status = inl(instance->status_reg) & ME4600_AI_STATUS_BIT_EF_DATA)) {     //No more data. status = ME_ERRNO_SUCCESS = 0
3269                         break;
3270                 }
3271                 *(instance->circ_buf.buf + instance->circ_buf.head) =
3272                     (inw(instance->data_reg) ^ 0x8000);
3273                 instance->circ_buf.head++;
3274                 instance->circ_buf.head &= instance->circ_buf.mask;
3275         }
3276
3277 #ifdef MEDEBUG_ERROR
3278         if (!status)
3279                 PDEBUG
3280                     ("Copied all remaining datas (%d) from FIFO to circular buffer.\n",
3281                      copied);
3282         else {
3283                 PDEBUG("No more empty space in buffer.\n");
3284                 PDEBUG("Copied %d datas from FIFO to circular buffer.\n",
3285                        copied);
3286                 PDEBUG("FIFO still not empty.\n");
3287         }
3288 #endif
3289         return (!status) ? copied : -ME_ERRNO_RING_BUFFER_OVERFLOW;
3290 }
3291
3292 static void me4600_ai_work_control_task(struct work_struct *work)
3293 {
3294         me4600_ai_subdevice_t *instance;
3295         uint32_t status;
3296         uint32_t ctrl;
3297         unsigned long cpu_flags = 0;
3298         int reschedule = 0;
3299         int signaling = 0;
3300
3301         instance =
3302             container_of((void *)work, me4600_ai_subdevice_t, ai_control_task);
3303         PINFO("<%s: %ld> executed.\n", __func__, jiffies);
3304
3305         status = inl(instance->status_reg);
3306         PDEBUG_REG("status_reg inl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3307                    instance->status_reg - instance->reg_base, status);
3308
3309         switch (instance->status) {     // Checking actual mode.
3310                 // Not configured for work.
3311         case ai_status_none:
3312                 break;
3313
3314                 //This are stable modes. No need to do anything. (?)
3315         case ai_status_single_configured:
3316         case ai_status_stream_configured:
3317         case ai_status_stream_fifo_error:
3318         case ai_status_stream_buffer_error:
3319         case ai_status_stream_error:
3320                 PERROR("Shouldn't be running!.\n");
3321                 break;
3322
3323                 // Stream modes
3324         case ai_status_stream_run_wait:
3325                 if (status & ME4600_AI_STATUS_BIT_FSM) {        // ISM started..
3326                         instance->status = ai_status_stream_run;
3327                         // Signal the end of wait for start.
3328                         signaling = 1;
3329                         // Wait now for stop.
3330                         reschedule = 1;
3331                         break;
3332
3333                         // Check timeout.
3334                         if ((instance->timeout.delay) && ((jiffies - instance->timeout.start_time) >= instance->timeout.delay)) {       // Timeout
3335                                 PDEBUG("Timeout reached.\n");
3336                                 // Stop all actions. No conditions! Block interrupts. Reset FIFO => Too late!
3337                                 ai_stop_isr(instance);
3338
3339                                 instance->status = ai_status_stream_end;
3340
3341                                 // Signal the end.
3342                                 signaling = 1;
3343                         }
3344                 }
3345                 break;
3346
3347         case ai_status_stream_run:
3348                 // Wait for stop ISM.
3349                 reschedule = 1;
3350                 break;
3351
3352         case ai_status_stream_end_wait:
3353                 if (!(status & ME4600_AI_STATUS_BIT_FSM)) {     // ISM stoped. Overwrite ISR.
3354                         instance->status = ai_status_stream_end;
3355                         // Signal the end of wait for stop.
3356                         signaling = 1;
3357                 } else {
3358                         // Wait for stop ISM.
3359                         reschedule = 1;
3360                 }
3361                 break;
3362
3363         case ai_status_stream_end:
3364                 //End work.
3365                 if (status & ME4600_AI_STATUS_BIT_FSM) {        // Still working? Stop it!
3366                         PERROR
3367                             ("Status is 'ai_status_stream_end' but hardware is still working!\n");
3368                         spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
3369                         ctrl = inl(instance->ctrl_reg);
3370                         ctrl |=
3371                             (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP |
3372                              ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
3373                              ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
3374                         outl(ctrl, instance->ctrl_reg);
3375                         PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3376                                    instance->reg_base,
3377                                    instance->ctrl_reg - instance->reg_base,
3378                                    ctrl);
3379                         spin_unlock_irqrestore(instance->ctrl_reg_lock,
3380                                                cpu_flags);
3381                 }
3382                 break;
3383
3384         default:
3385                 PERROR_CRITICAL("Status is in wrong state (%d)!\n",
3386                                 instance->status);
3387                 instance->status = ai_status_stream_error;
3388                 // Signal the end.
3389                 signaling = 1;
3390                 break;
3391
3392         }
3393
3394         if (signaling) {        //Signal it.
3395                 wake_up_interruptible_all(&instance->wait_queue);
3396         }
3397
3398         if (instance->ai_control_task_flag && reschedule) {     // Reschedule task
3399                 queue_delayed_work(instance->me4600_workqueue,
3400                                    &instance->ai_control_task, 1);
3401         } else {
3402                 PINFO("<%s> Ending control task.\n", __func__);
3403         }
3404
3405 }