drivers/spi/spi-ti-qspi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
   6  * Author: Sourav Poddar <sourav.poddar@ti.com>
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/module.h>
  13 #include <linux/device.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/omap-dma.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/slab.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/of.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/regmap.h>
  28 #include <linux/sizes.h>
  29
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/spi-mem.h>
  32
  33 struct ti_qspi_regs {
  34         u32 clkctrl;
  35 };
  36
  37 struct ti_qspi {
  38         struct completion       transfer_complete;
  39
  40         /* list synchronization */
  41         struct mutex            list_lock;
  42
  43         struct spi_controller   *host;
  44         void __iomem            *base;
  45         void __iomem            *mmap_base;
  46         size_t                  mmap_size;
  47         struct regmap           *ctrl_base;
  48         unsigned int            ctrl_reg;
  49         struct clk              *fclk;
  50         struct device           *dev;
  51
  52         struct ti_qspi_regs     ctx_reg;
  53
  54         dma_addr_t              mmap_phys_base;
  55         dma_addr_t              rx_bb_dma_addr;
  56         void                    *rx_bb_addr;
  57         struct dma_chan         *rx_chan;
  58
  59         u32 cmd;
  60         u32 dc;
  61
  62         bool mmap_enabled;
  63         int current_cs;
  64 };
  65
  66 #define QSPI_PID                        (0x0)
  67 #define QSPI_SYSCONFIG                  (0x10)
  68 #define QSPI_SPI_CLOCK_CNTRL_REG        (0x40)
  69 #define QSPI_SPI_DC_REG                 (0x44)
  70 #define QSPI_SPI_CMD_REG                (0x48)
  71 #define QSPI_SPI_STATUS_REG             (0x4c)
  72 #define QSPI_SPI_DATA_REG               (0x50)
  73 #define QSPI_SPI_SETUP_REG(n)           ((0x54 + 4 * n))
  74 #define QSPI_SPI_SWITCH_REG             (0x64)
  75 #define QSPI_SPI_DATA_REG_1             (0x68)
  76 #define QSPI_SPI_DATA_REG_2             (0x6c)
  77 #define QSPI_SPI_DATA_REG_3             (0x70)
  78
  79 #define QSPI_COMPLETION_TIMEOUT         msecs_to_jiffies(2000)
  80
  81 /* Clock Control */
  82 #define QSPI_CLK_EN                     (1 << 31)
  83 #define QSPI_CLK_DIV_MAX                0xffff
  84
  85 /* Command */
  86 #define QSPI_EN_CS(n)                   (n << 28)
  87 #define QSPI_WLEN(n)                    ((n - 1) << 19)
  88 #define QSPI_3_PIN                      (1 << 18)
  89 #define QSPI_RD_SNGL                    (1 << 16)
  90 #define QSPI_WR_SNGL                    (2 << 16)
  91 #define QSPI_RD_DUAL                    (3 << 16)
  92 #define QSPI_RD_QUAD                    (7 << 16)
  93 #define QSPI_INVAL                      (4 << 16)
  94 #define QSPI_FLEN(n)                    ((n - 1) << 0)
  95 #define QSPI_WLEN_MAX_BITS              128
  96 #define QSPI_WLEN_MAX_BYTES             16
  97 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  98
  99 /* STATUS REGISTER */
 100 #define BUSY                            0x01
 101 #define WC                              0x02
 102
 103 /* Device Control */
 104 #define QSPI_DD(m, n)                   (m << (3 + n * 8))
 105 #define QSPI_CKPHA(n)                   (1 << (2 + n * 8))
 106 #define QSPI_CSPOL(n)                   (1 << (1 + n * 8))
 107 #define QSPI_CKPOL(n)                   (1 << (n * 8))
 108
 109 #define QSPI_FRAME                      4096
 110
 111 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
 112
 113 #define MEM_CS_EN(n)                    ((n + 1) << 8)
 114 #define MEM_CS_MASK                     (7 << 8)
 115
 116 #define MM_SWITCH                       0x1
 117
 118 #define QSPI_SETUP_RD_NORMAL            (0x0 << 12)
 119 #define QSPI_SETUP_RD_DUAL              (0x1 << 12)
 120 #define QSPI_SETUP_RD_QUAD              (0x3 << 12)
 121 #define QSPI_SETUP_ADDR_SHIFT           8
 122 #define QSPI_SETUP_DUMMY_SHIFT          10
 123
 124 #define QSPI_DMA_BUFFER_SIZE            SZ_64K
 125
 126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
 127                 unsigned long reg)
 128 {
 129         return readl(qspi->base + reg);
 130 }
 131
 132 static inline void ti_qspi_write(struct ti_qspi *qspi,
 133                 unsigned long val, unsigned long reg)
 134 {
 135         writel(val, qspi->base + reg);
 136 }
 137
 138 static int ti_qspi_setup(struct spi_device *spi)
 139 {
 140         struct ti_qspi  *qspi = spi_controller_get_devdata(spi->controller);
 141         int ret;
 142
 143         if (spi->controller->busy) {
 144                 dev_dbg(qspi->dev, "host busy doing other transfers\n");
 145                 return -EBUSY;
 146         }
 147
 148         if (!qspi->host->max_speed_hz) {
 149                 dev_err(qspi->dev, "spi max frequency not defined\n");
 150                 return -EINVAL;
 151         }
 152
 153         spi->max_speed_hz = min(spi->max_speed_hz, qspi->host->max_speed_hz);
 154
 155         ret = pm_runtime_resume_and_get(qspi->dev);
 156         if (ret < 0) {
 157                 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
 158                 return ret;
 159         }
 160
 161         pm_runtime_mark_last_busy(qspi->dev);
 162         ret = pm_runtime_put_autosuspend(qspi->dev);
 163         if (ret < 0) {
 164                 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
 165                 return ret;
 166         }
 167
 168         return 0;
 169 }
 170
 171 static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz)
 172 {
 173         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 174         int clk_div;
 175         u32 clk_ctrl_reg, clk_rate, clk_ctrl_new;
 176
 177         clk_rate = clk_get_rate(qspi->fclk);
 178         clk_div = DIV_ROUND_UP(clk_rate, speed_hz) - 1;
 179         clk_div = clamp(clk_div, 0, QSPI_CLK_DIV_MAX);
 180         dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div);
 181
 182         pm_runtime_resume_and_get(qspi->dev);
 183
 184         clk_ctrl_new = QSPI_CLK_EN | clk_div;
 185         if (ctx_reg->clkctrl != clk_ctrl_new) {
 186                 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
 187
 188                 clk_ctrl_reg &= ~QSPI_CLK_EN;
 189
 190                 /* disable SCLK */
 191                 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
 192
 193                 /* enable SCLK */
 194                 ti_qspi_write(qspi, clk_ctrl_new, QSPI_SPI_CLOCK_CNTRL_REG);
 195                 ctx_reg->clkctrl = clk_ctrl_new;
 196         }
 197
 198         pm_runtime_mark_last_busy(qspi->dev);
 199         pm_runtime_put_autosuspend(qspi->dev);
 200 }
 201
 202 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 203 {
 204         struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
 205
 206         ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
 207 }
 208
 209 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
 210 {
 211         u32 stat;
 212         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 213
 214         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 215         while ((stat & BUSY) && time_after(timeout, jiffies)) {
 216                 cpu_relax();
 217                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 218         }
 219
 220         WARN(stat & BUSY, "qspi busy\n");
 221         return stat & BUSY;
 222 }
 223
 224 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
 225 {
 226         u32 stat;
 227         unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
 228
 229         do {
 230                 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 231                 if (stat & WC)
 232                         return 0;
 233                 cpu_relax();
 234         } while (time_after(timeout, jiffies));
 235
 236         stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
 237         if (stat & WC)
 238                 return 0;
 239         return  -ETIMEDOUT;
 240 }
 241
 242 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 243                           int count)
 244 {
 245         int wlen, xfer_len;
 246         unsigned int cmd;
 247         const u8 *txbuf;
 248         u32 data;
 249
 250         txbuf = t->tx_buf;
 251         cmd = qspi->cmd | QSPI_WR_SNGL;
 252         wlen = t->bits_per_word >> 3;   /* in bytes */
 253         xfer_len = wlen;
 254
 255         while (count) {
 256                 if (qspi_is_busy(qspi))
 257                         return -EBUSY;
 258
 259                 switch (wlen) {
 260                 case 1:
 261                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
 262                                         cmd, qspi->dc, *txbuf);
 263                         if (count >= QSPI_WLEN_MAX_BYTES) {
 264                                 u32 *txp = (u32 *)txbuf;
 265
 266                                 data = cpu_to_be32(*txp++);
 267                                 writel(data, qspi->base +
 268                                        QSPI_SPI_DATA_REG_3);
 269                                 data = cpu_to_be32(*txp++);
 270                                 writel(data, qspi->base +
 271                                        QSPI_SPI_DATA_REG_2);
 272                                 data = cpu_to_be32(*txp++);
 273                                 writel(data, qspi->base +
 274                                        QSPI_SPI_DATA_REG_1);
 275                                 data = cpu_to_be32(*txp++);
 276                                 writel(data, qspi->base +
 277                                        QSPI_SPI_DATA_REG);
 278                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 279                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 280                         } else {
 281                                 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
 282                                 cmd = qspi->cmd | QSPI_WR_SNGL;
 283                                 xfer_len = wlen;
 284                                 cmd |= QSPI_WLEN(wlen);
 285                         }
 286                         break;
 287                 case 2:
 288                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
 289                                         cmd, qspi->dc, *txbuf);
 290                         writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 291                         break;
 292                 case 4:
 293                         dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
 294                                         cmd, qspi->dc, *txbuf);
 295                         writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
 296                         break;
 297                 }
 298
 299                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 300                 if (ti_qspi_poll_wc(qspi)) {
 301                         dev_err(qspi->dev, "write timed out\n");
 302                         return -ETIMEDOUT;
 303                 }
 304                 txbuf += xfer_len;
 305                 count -= xfer_len;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 312                          int count)
 313 {
 314         int wlen;
 315         unsigned int cmd;
 316         u32 rx;
 317         u8 rxlen, rx_wlen;
 318         u8 *rxbuf;
 319
 320         rxbuf = t->rx_buf;
 321         cmd = qspi->cmd;
 322         switch (t->rx_nbits) {
 323         case SPI_NBITS_DUAL:
 324                 cmd |= QSPI_RD_DUAL;
 325                 break;
 326         case SPI_NBITS_QUAD:
 327                 cmd |= QSPI_RD_QUAD;
 328                 break;
 329         default:
 330                 cmd |= QSPI_RD_SNGL;
 331                 break;
 332         }
 333         wlen = t->bits_per_word >> 3;   /* in bytes */
 334         rx_wlen = wlen;
 335
 336         while (count) {
 337                 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
 338                 if (qspi_is_busy(qspi))
 339                         return -EBUSY;
 340
 341                 switch (wlen) {
 342                 case 1:
 343                         /*
 344                          * Optimize the 8-bit words transfers, as used by
 345                          * the SPI flash devices.
 346                          */
 347                         if (count >= QSPI_WLEN_MAX_BYTES) {
 348                                 rxlen = QSPI_WLEN_MAX_BYTES;
 349                         } else {
 350                                 rxlen = min(count, 4);
 351                         }
 352                         rx_wlen = rxlen << 3;
 353                         cmd &= ~QSPI_WLEN_MASK;
 354                         cmd |= QSPI_WLEN(rx_wlen);
 355                         break;
 356                 default:
 357                         rxlen = wlen;
 358                         break;
 359                 }
 360
 361                 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
 362                 if (ti_qspi_poll_wc(qspi)) {
 363                         dev_err(qspi->dev, "read timed out\n");
 364                         return -ETIMEDOUT;
 365                 }
 366
 367                 switch (wlen) {
 368                 case 1:
 369                         /*
 370                          * Optimize the 8-bit words transfers, as used by
 371                          * the SPI flash devices.
 372                          */
 373                         if (count >= QSPI_WLEN_MAX_BYTES) {
 374                                 u32 *rxp = (u32 *) rxbuf;
 375                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3);
 376                                 *rxp++ = be32_to_cpu(rx);
 377                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2);
 378                                 *rxp++ = be32_to_cpu(rx);
 379                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1);
 380                                 *rxp++ = be32_to_cpu(rx);
 381                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
 382                                 *rxp++ = be32_to_cpu(rx);
 383                         } else {
 384                                 u8 *rxp = rxbuf;
 385                                 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
 386                                 if (rx_wlen >= 8)
 387                                         *rxp++ = rx >> (rx_wlen - 8);
 388                                 if (rx_wlen >= 16)
 389                                         *rxp++ = rx >> (rx_wlen - 16);
 390                                 if (rx_wlen >= 24)
 391                                         *rxp++ = rx >> (rx_wlen - 24);
 392                                 if (rx_wlen >= 32)
 393                                         *rxp++ = rx;
 394                         }
 395                         break;
 396                 case 2:
 397                         *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
 398                         break;
 399                 case 4:
 400                         *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
 401                         break;
 402                 }
 403                 rxbuf += rxlen;
 404                 count -= rxlen;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
 411                              int count)
 412 {
 413         int ret;
 414
 415         if (t->tx_buf) {
 416                 ret = qspi_write_msg(qspi, t, count);
 417                 if (ret) {
 418                         dev_dbg(qspi->dev, "Error while writing\n");
 419                         return ret;
 420                 }
 421         }
 422
 423         if (t->rx_buf) {
 424                 ret = qspi_read_msg(qspi, t, count);
 425                 if (ret) {
 426                         dev_dbg(qspi->dev, "Error while reading\n");
 427                         return ret;
 428                 }
 429         }
 430
 431         return 0;
 432 }
 433
 434 static void ti_qspi_dma_callback(void *param)
 435 {
 436         struct ti_qspi *qspi = param;
 437
 438         complete(&qspi->transfer_complete);
 439 }
 440
 441 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
 442                             dma_addr_t dma_src, size_t len)
 443 {
 444         struct dma_chan *chan = qspi->rx_chan;
 445         dma_cookie_t cookie;
 446         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 447         struct dma_async_tx_descriptor *tx;
 448         int ret;
 449         unsigned long time_left;
 450
 451         tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
 452         if (!tx) {
 453                 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
 454                 return -EIO;
 455         }
 456
 457         tx->callback = ti_qspi_dma_callback;
 458         tx->callback_param = qspi;
 459         cookie = tx->tx_submit(tx);
 460         reinit_completion(&qspi->transfer_complete);
 461
 462         ret = dma_submit_error(cookie);
 463         if (ret) {
 464                 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
 465                 return -EIO;
 466         }
 467
 468         dma_async_issue_pending(chan);
 469         time_left = wait_for_completion_timeout(&qspi->transfer_complete,
 470                                           msecs_to_jiffies(len));
 471         if (time_left == 0) {
 472                 dmaengine_terminate_sync(chan);
 473                 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
 474                 return -ETIMEDOUT;
 475         }
 476
 477         return 0;
 478 }
 479
 480 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
 481                                      void *to, size_t readsize)
 482 {
 483         dma_addr_t dma_src = qspi->mmap_phys_base + offs;
 484         int ret = 0;
 485
 486         /*
 487          * Use bounce buffer as FS like jffs2, ubifs may pass
 488          * buffers that does not belong to kernel lowmem region.
 489          */
 490         while (readsize != 0) {
 491                 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
 492                                         readsize);
 493
 494                 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
 495                                        dma_src, xfer_len);
 496                 if (ret != 0)
 497                         return ret;
 498                 memcpy(to, qspi->rx_bb_addr, xfer_len);
 499                 readsize -= xfer_len;
 500                 dma_src += xfer_len;
 501                 to += xfer_len;
 502         }
 503
 504         return ret;
 505 }
 506
 507 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
 508                                loff_t from)
 509 {
 510         struct scatterlist *sg;
 511         dma_addr_t dma_src = qspi->mmap_phys_base + from;
 512         dma_addr_t dma_dst;
 513         int i, len, ret;
 514
 515         for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
 516                 dma_dst = sg_dma_address(sg);
 517                 len = sg_dma_len(sg);
 518                 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
 519                 if (ret)
 520                         return ret;
 521                 dma_src += len;
 522         }
 523
 524         return 0;
 525 }
 526
 527 static void ti_qspi_enable_memory_map(struct spi_device *spi)
 528 {
 529         struct ti_qspi  *qspi = spi_controller_get_devdata(spi->controller);
 530
 531         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
 532         if (qspi->ctrl_base) {
 533                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 534                                    MEM_CS_MASK,
 535                                    MEM_CS_EN(spi_get_chipselect(spi, 0)));
 536         }
 537         qspi->mmap_enabled = true;
 538         qspi->current_cs = spi_get_chipselect(spi, 0);
 539 }
 540
 541 static void ti_qspi_disable_memory_map(struct spi_device *spi)
 542 {
 543         struct ti_qspi  *qspi = spi_controller_get_devdata(spi->controller);
 544
 545         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
 546         if (qspi->ctrl_base)
 547                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
 548                                    MEM_CS_MASK, 0);
 549         qspi->mmap_enabled = false;
 550         qspi->current_cs = -1;
 551 }
 552
 553 static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
 554                                     u8 data_nbits, u8 addr_width,
 555                                     u8 dummy_bytes)
 556 {
 557         struct ti_qspi  *qspi = spi_controller_get_devdata(spi->controller);
 558         u32 memval = opcode;
 559
 560         switch (data_nbits) {
 561         case SPI_NBITS_QUAD:
 562                 memval |= QSPI_SETUP_RD_QUAD;
 563                 break;
 564         case SPI_NBITS_DUAL:
 565                 memval |= QSPI_SETUP_RD_DUAL;
 566                 break;
 567         default:
 568                 memval |= QSPI_SETUP_RD_NORMAL;
 569                 break;
 570         }
 571         memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
 572                    dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
 573         ti_qspi_write(qspi, memval,
 574                       QSPI_SPI_SETUP_REG(spi_get_chipselect(spi, 0)));
 575 }
 576
 577 static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
 578 {
 579         struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller);
 580         size_t max_len;
 581
 582         if (op->data.dir == SPI_MEM_DATA_IN) {
 583                 if (op->addr.val < qspi->mmap_size) {
 584                         /* Limit MMIO to the mmaped region */
 585                         if (op->addr.val + op->data.nbytes > qspi->mmap_size) {
 586                                 max_len = qspi->mmap_size - op->addr.val;
 587                                 op->data.nbytes = min((size_t) op->data.nbytes,
 588                                                       max_len);
 589                         }
 590                 } else {
 591                         /*
 592                          * Use fallback mode (SW generated transfers) above the
 593                          * mmaped region.
 594                          * Adjust size to comply with the QSPI max frame length.
 595                          */
 596                         max_len = QSPI_FRAME;
 597                         max_len -= 1 + op->addr.nbytes + op->dummy.nbytes;
 598                         op->data.nbytes = min((size_t) op->data.nbytes,
 599                                               max_len);
 600                 }
 601         }
 602
 603         return 0;
 604 }
 605
 606 static int ti_qspi_exec_mem_op(struct spi_mem *mem,
 607                                const struct spi_mem_op *op)
 608 {
 609         struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->controller);
 610         u32 from = 0;
 611         int ret = 0;
 612
 613         /* Only optimize read path. */
 614         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 615             !op->addr.nbytes || op->addr.nbytes > 4)
 616                 return -EOPNOTSUPP;
 617
 618         /* Address exceeds MMIO window size, fall back to regular mode. */
 619         from = op->addr.val;
 620         if (from + op->data.nbytes > qspi->mmap_size)
 621                 return -EOPNOTSUPP;
 622
 623         mutex_lock(&qspi->list_lock);
 624
 625         if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) {
 626                 ti_qspi_setup_clk(qspi, mem->spi->max_speed_hz);
 627                 ti_qspi_enable_memory_map(mem->spi);
 628         }
 629         ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
 630                                 op->addr.nbytes, op->dummy.nbytes);
 631
 632         if (qspi->rx_chan) {
 633                 struct sg_table sgt;
 634
 635                 if (virt_addr_valid(op->data.buf.in) &&
 636                     !spi_controller_dma_map_mem_op_data(mem->spi->controller, op,
 637                                                         &sgt)) {
 638                         ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
 639                         spi_controller_dma_unmap_mem_op_data(mem->spi->controller,
 640                                                              op, &sgt);
 641                 } else {
 642                         ret = ti_qspi_dma_bounce_buffer(qspi, from,
 643                                                         op->data.buf.in,
 644                                                         op->data.nbytes);
 645                 }
 646         } else {
 647                 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
 648                               op->data.nbytes);
 649         }
 650
 651         mutex_unlock(&qspi->list_lock);
 652
 653         return ret;
 654 }
 655
 656 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 657         .exec_op = ti_qspi_exec_mem_op,
 658         .adjust_op_size = ti_qspi_adjust_op_size,
 659 };
 660
 661 static int ti_qspi_start_transfer_one(struct spi_controller *host,
 662                 struct spi_message *m)
 663 {
 664         struct ti_qspi *qspi = spi_controller_get_devdata(host);
 665         struct spi_device *spi = m->spi;
 666         struct spi_transfer *t;
 667         int status = 0, ret;
 668         unsigned int frame_len_words, transfer_len_words;
 669         int wlen;
 670
 671         /* setup device control reg */
 672         qspi->dc = 0;
 673
 674         if (spi->mode & SPI_CPHA)
 675                 qspi->dc |= QSPI_CKPHA(spi_get_chipselect(spi, 0));
 676         if (spi->mode & SPI_CPOL)
 677                 qspi->dc |= QSPI_CKPOL(spi_get_chipselect(spi, 0));
 678         if (spi->mode & SPI_CS_HIGH)
 679                 qspi->dc |= QSPI_CSPOL(spi_get_chipselect(spi, 0));
 680
 681         frame_len_words = 0;
 682         list_for_each_entry(t, &m->transfers, transfer_list)
 683                 frame_len_words += t->len / (t->bits_per_word >> 3);
 684         frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
 685
 686         /* setup command reg */
 687         qspi->cmd = 0;
 688         qspi->cmd |= QSPI_EN_CS(spi_get_chipselect(spi, 0));
 689         qspi->cmd |= QSPI_FLEN(frame_len_words);
 690
 691         ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
 692
 693         mutex_lock(&qspi->list_lock);
 694
 695         if (qspi->mmap_enabled)
 696                 ti_qspi_disable_memory_map(spi);
 697
 698         list_for_each_entry(t, &m->transfers, transfer_list) {
 699                 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
 700                              QSPI_WLEN(t->bits_per_word));
 701
 702                 wlen = t->bits_per_word >> 3;
 703                 transfer_len_words = min(t->len / wlen, frame_len_words);
 704
 705                 ti_qspi_setup_clk(qspi, t->speed_hz);
 706                 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
 707                 if (ret) {
 708                         dev_dbg(qspi->dev, "transfer message failed\n");
 709                         mutex_unlock(&qspi->list_lock);
 710                         return -EINVAL;
 711                 }
 712
 713                 m->actual_length += transfer_len_words * wlen;
 714                 frame_len_words -= transfer_len_words;
 715                 if (frame_len_words == 0)
 716                         break;
 717         }
 718
 719         mutex_unlock(&qspi->list_lock);
 720
 721         ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
 722         m->status = status;
 723         spi_finalize_current_message(host);
 724
 725         return status;
 726 }
 727
 728 static int ti_qspi_runtime_resume(struct device *dev)
 729 {
 730         struct ti_qspi      *qspi;
 731
 732         qspi = dev_get_drvdata(dev);
 733         ti_qspi_restore_ctx(qspi);
 734
 735         return 0;
 736 }
 737
 738 static void ti_qspi_dma_cleanup(struct ti_qspi *qspi)
 739 {
 740         if (qspi->rx_bb_addr)
 741                 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
 742                                   qspi->rx_bb_addr,
 743                                   qspi->rx_bb_dma_addr);
 744
 745         if (qspi->rx_chan)
 746                 dma_release_channel(qspi->rx_chan);
 747 }
 748
 749 static const struct of_device_id ti_qspi_match[] = {
 750         {.compatible = "ti,dra7xxx-qspi" },
 751         {.compatible = "ti,am4372-qspi" },
 752         {},
 753 };
 754 MODULE_DEVICE_TABLE(of, ti_qspi_match);
 755
 756 static int ti_qspi_probe(struct platform_device *pdev)
 757 {
 758         struct  ti_qspi *qspi;
 759         struct spi_controller *host;
 760         struct resource         *r, *res_mmap;
 761         struct device_node *np = pdev->dev.of_node;
 762         u32 max_freq;
 763         int ret = 0, num_cs, irq;
 764         dma_cap_mask_t mask;
 765
 766         host = spi_alloc_host(&pdev->dev, sizeof(*qspi));
 767         if (!host)
 768                 return -ENOMEM;
 769
 770         host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
 771
 772         host->flags = SPI_CONTROLLER_HALF_DUPLEX;
 773         host->setup = ti_qspi_setup;
 774         host->auto_runtime_pm = true;
 775         host->transfer_one_message = ti_qspi_start_transfer_one;
 776         host->dev.of_node = pdev->dev.of_node;
 777         host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
 778                                    SPI_BPW_MASK(8);
 779         host->mem_ops = &ti_qspi_mem_ops;
 780
 781         if (!of_property_read_u32(np, "num-cs", &num_cs))
 782                 host->num_chipselect = num_cs;
 783
 784         qspi = spi_controller_get_devdata(host);
 785         qspi->host = host;
 786         qspi->dev = &pdev->dev;
 787         platform_set_drvdata(pdev, qspi);
 788
 789         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 790         if (r == NULL) {
 791                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 792                 if (r == NULL) {
 793                         dev_err(&pdev->dev, "missing platform data\n");
 794                         ret = -ENODEV;
 795                         goto free_host;
 796                 }
 797         }
 798
 799         res_mmap = platform_get_resource_byname(pdev,
 800                         IORESOURCE_MEM, "qspi_mmap");
 801         if (res_mmap == NULL) {
 802                 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 803                 if (res_mmap == NULL) {
 804                         dev_err(&pdev->dev,
 805                                 "memory mapped resource not required\n");
 806                 }
 807         }
 808
 809         if (res_mmap)
 810                 qspi->mmap_size = resource_size(res_mmap);
 811
 812         irq = platform_get_irq(pdev, 0);
 813         if (irq < 0) {
 814                 ret = irq;
 815                 goto free_host;
 816         }
 817
 818         mutex_init(&qspi->list_lock);
 819
 820         qspi->base = devm_ioremap_resource(&pdev->dev, r);
 821         if (IS_ERR(qspi->base)) {
 822                 ret = PTR_ERR(qspi->base);
 823                 goto free_host;
 824         }
 825
 826
 827         if (of_property_read_bool(np, "syscon-chipselects")) {
 828                 qspi->ctrl_base =
 829                 syscon_regmap_lookup_by_phandle(np,
 830                                                 "syscon-chipselects");
 831                 if (IS_ERR(qspi->ctrl_base)) {
 832                         ret = PTR_ERR(qspi->ctrl_base);
 833                         goto free_host;
 834                 }
 835                 ret = of_property_read_u32_index(np,
 836                                                  "syscon-chipselects",
 837                                                  1, &qspi->ctrl_reg);
 838                 if (ret) {
 839                         dev_err(&pdev->dev,
 840                                 "couldn't get ctrl_mod reg index\n");
 841                         goto free_host;
 842                 }
 843         }
 844
 845         qspi->fclk = devm_clk_get(&pdev->dev, "fck");
 846         if (IS_ERR(qspi->fclk)) {
 847                 ret = PTR_ERR(qspi->fclk);
 848                 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
 849         }
 850
 851         pm_runtime_use_autosuspend(&pdev->dev);
 852         pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
 853         pm_runtime_enable(&pdev->dev);
 854
 855         if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
 856                 host->max_speed_hz = max_freq;
 857
 858         dma_cap_zero(mask);
 859         dma_cap_set(DMA_MEMCPY, mask);
 860
 861         qspi->rx_chan = dma_request_chan_by_mask(&mask);
 862         if (IS_ERR(qspi->rx_chan)) {
 863                 dev_err(qspi->dev,
 864                         "No Rx DMA available, trying mmap mode\n");
 865                 qspi->rx_chan = NULL;
 866                 ret = 0;
 867                 goto no_dma;
 868         }
 869         qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
 870                                               QSPI_DMA_BUFFER_SIZE,
 871                                               &qspi->rx_bb_dma_addr,
 872                                               GFP_KERNEL | GFP_DMA);
 873         if (!qspi->rx_bb_addr) {
 874                 dev_err(qspi->dev,
 875                         "dma_alloc_coherent failed, using PIO mode\n");
 876                 dma_release_channel(qspi->rx_chan);
 877                 goto no_dma;
 878         }
 879         host->dma_rx = qspi->rx_chan;
 880         init_completion(&qspi->transfer_complete);
 881         if (res_mmap)
 882                 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
 883
 884 no_dma:
 885         if (!qspi->rx_chan && res_mmap) {
 886                 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
 887                 if (IS_ERR(qspi->mmap_base)) {
 888                         dev_info(&pdev->dev,
 889                                  "mmap failed with error %ld using PIO mode\n",
 890                                  PTR_ERR(qspi->mmap_base));
 891                         qspi->mmap_base = NULL;
 892                         host->mem_ops = NULL;
 893                 }
 894         }
 895         qspi->mmap_enabled = false;
 896         qspi->current_cs = -1;
 897
 898         ret = devm_spi_register_controller(&pdev->dev, host);
 899         if (!ret)
 900                 return 0;
 901
 902         ti_qspi_dma_cleanup(qspi);
 903
 904         pm_runtime_disable(&pdev->dev);
 905 free_host:
 906         spi_controller_put(host);
 907         return ret;
 908 }
 909
 910 static void ti_qspi_remove(struct platform_device *pdev)
 911 {
 912         struct ti_qspi *qspi = platform_get_drvdata(pdev);
 913         int rc;
 914
 915         rc = spi_controller_suspend(qspi->host);
 916         if (rc) {
 917                 dev_alert(&pdev->dev, "spi_controller_suspend() failed (%pe)\n",
 918                           ERR_PTR(rc));
 919                 return;
 920         }
 921
 922         pm_runtime_put_sync(&pdev->dev);
 923         pm_runtime_disable(&pdev->dev);
 924
 925         ti_qspi_dma_cleanup(qspi);
 926 }
 927
 928 static const struct dev_pm_ops ti_qspi_pm_ops = {
 929         .runtime_resume = ti_qspi_runtime_resume,
 930 };
 931
 932 static struct platform_driver ti_qspi_driver = {
 933         .probe  = ti_qspi_probe,
 934         .remove_new = ti_qspi_remove,
 935         .driver = {
 936                 .name   = "ti-qspi",
 937                 .pm =   &ti_qspi_pm_ops,
 938                 .of_match_table = ti_qspi_match,
 939         }
 940 };
 941
 942 module_platform_driver(ti_qspi_driver);
 943
 944 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
 945 MODULE_LICENSE("GPL v2");
 946 MODULE_DESCRIPTION("TI QSPI controller driver");
 947 MODULE_ALIAS("platform:ti-qspi");