drivers/spi/spi-rspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH RSPI driver
   4  *
   5  * Copyright (C) 2012, 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2014 Glider bvba
   7  *
   8  * Based on spi-sh.c:
   9  * Copyright (C) 2011 Renesas Solutions Corp.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/clk.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/of.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/reset.h>
  25 #include <linux/sh_dma.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spinlock.h>
  28
  29 #define RSPI_SPCR               0x00    /* Control Register */
  30 #define RSPI_SSLP               0x01    /* Slave Select Polarity Register */
  31 #define RSPI_SPPCR              0x02    /* Pin Control Register */
  32 #define RSPI_SPSR               0x03    /* Status Register */
  33 #define RSPI_SPDR               0x04    /* Data Register */
  34 #define RSPI_SPSCR              0x08    /* Sequence Control Register */
  35 #define RSPI_SPSSR              0x09    /* Sequence Status Register */
  36 #define RSPI_SPBR               0x0a    /* Bit Rate Register */
  37 #define RSPI_SPDCR              0x0b    /* Data Control Register */
  38 #define RSPI_SPCKD              0x0c    /* Clock Delay Register */
  39 #define RSPI_SSLND              0x0d    /* Slave Select Negation Delay Register */
  40 #define RSPI_SPND               0x0e    /* Next-Access Delay Register */
  41 #define RSPI_SPCR2              0x0f    /* Control Register 2 (SH only) */
  42 #define RSPI_SPCMD0             0x10    /* Command Register 0 */
  43 #define RSPI_SPCMD1             0x12    /* Command Register 1 */
  44 #define RSPI_SPCMD2             0x14    /* Command Register 2 */
  45 #define RSPI_SPCMD3             0x16    /* Command Register 3 */
  46 #define RSPI_SPCMD4             0x18    /* Command Register 4 */
  47 #define RSPI_SPCMD5             0x1a    /* Command Register 5 */
  48 #define RSPI_SPCMD6             0x1c    /* Command Register 6 */
  49 #define RSPI_SPCMD7             0x1e    /* Command Register 7 */
  50 #define RSPI_SPCMD(i)           (RSPI_SPCMD0 + (i) * 2)
  51 #define RSPI_NUM_SPCMD          8
  52 #define RSPI_RZ_NUM_SPCMD       4
  53 #define QSPI_NUM_SPCMD          4
  54
  55 /* RSPI on RZ only */
  56 #define RSPI_SPBFCR             0x20    /* Buffer Control Register */
  57 #define RSPI_SPBFDR             0x22    /* Buffer Data Count Setting Register */
  58
  59 /* QSPI only */
  60 #define QSPI_SPBFCR             0x18    /* Buffer Control Register */
  61 #define QSPI_SPBDCR             0x1a    /* Buffer Data Count Register */
  62 #define QSPI_SPBMUL0            0x1c    /* Transfer Data Length Multiplier Setting Register 0 */
  63 #define QSPI_SPBMUL1            0x20    /* Transfer Data Length Multiplier Setting Register 1 */
  64 #define QSPI_SPBMUL2            0x24    /* Transfer Data Length Multiplier Setting Register 2 */
  65 #define QSPI_SPBMUL3            0x28    /* Transfer Data Length Multiplier Setting Register 3 */
  66 #define QSPI_SPBMUL(i)          (QSPI_SPBMUL0 + (i) * 4)
  67
  68 /* SPCR - Control Register */
  69 #define SPCR_SPRIE              0x80    /* Receive Interrupt Enable */
  70 #define SPCR_SPE                0x40    /* Function Enable */
  71 #define SPCR_SPTIE              0x20    /* Transmit Interrupt Enable */
  72 #define SPCR_SPEIE              0x10    /* Error Interrupt Enable */
  73 #define SPCR_MSTR               0x08    /* Master/Slave Mode Select */
  74 #define SPCR_MODFEN             0x04    /* Mode Fault Error Detection Enable */
  75 /* RSPI on SH only */
  76 #define SPCR_TXMD               0x02    /* TX Only Mode (vs. Full Duplex) */
  77 #define SPCR_SPMS               0x01    /* 3-wire Mode (vs. 4-wire) */
  78 /* QSPI on R-Car Gen2 only */
  79 #define SPCR_WSWAP              0x02    /* Word Swap of read-data for DMAC */
  80 #define SPCR_BSWAP              0x01    /* Byte Swap of read-data for DMAC */
  81
  82 /* SSLP - Slave Select Polarity Register */
  83 #define SSLP_SSLP(i)            BIT(i)  /* SSLi Signal Polarity Setting */
  84
  85 /* SPPCR - Pin Control Register */
  86 #define SPPCR_MOIFE             0x20    /* MOSI Idle Value Fixing Enable */
  87 #define SPPCR_MOIFV             0x10    /* MOSI Idle Fixed Value */
  88 #define SPPCR_SPOM              0x04
  89 #define SPPCR_SPLP2             0x02    /* Loopback Mode 2 (non-inverting) */
  90 #define SPPCR_SPLP              0x01    /* Loopback Mode (inverting) */
  91
  92 #define SPPCR_IO3FV             0x04    /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
  93 #define SPPCR_IO2FV             0x04    /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
  94
  95 /* SPSR - Status Register */
  96 #define SPSR_SPRF               0x80    /* Receive Buffer Full Flag */
  97 #define SPSR_TEND               0x40    /* Transmit End */
  98 #define SPSR_SPTEF              0x20    /* Transmit Buffer Empty Flag */
  99 #define SPSR_PERF               0x08    /* Parity Error Flag */
 100 #define SPSR_MODF               0x04    /* Mode Fault Error Flag */
 101 #define SPSR_IDLNF              0x02    /* RSPI Idle Flag */
 102 #define SPSR_OVRF               0x01    /* Overrun Error Flag (RSPI only) */
 103
 104 /* SPSCR - Sequence Control Register */
 105 #define SPSCR_SPSLN_MASK        0x07    /* Sequence Length Specification */
 106
 107 /* SPSSR - Sequence Status Register */
 108 #define SPSSR_SPECM_MASK        0x70    /* Command Error Mask */
 109 #define SPSSR_SPCP_MASK         0x07    /* Command Pointer Mask */
 110
 111 /* SPDCR - Data Control Register */
 112 #define SPDCR_TXDMY             0x80    /* Dummy Data Transmission Enable */
 113 #define SPDCR_SPLW1             0x40    /* Access Width Specification (RZ) */
 114 #define SPDCR_SPLW0             0x20    /* Access Width Specification (RZ) */
 115 #define SPDCR_SPLLWORD          (SPDCR_SPLW1 | SPDCR_SPLW0)
 116 #define SPDCR_SPLWORD           SPDCR_SPLW1
 117 #define SPDCR_SPLBYTE           SPDCR_SPLW0
 118 #define SPDCR_SPLW              0x20    /* Access Width Specification (SH) */
 119 #define SPDCR_SPRDTD            0x10    /* Receive Transmit Data Select (SH) */
 120 #define SPDCR_SLSEL1            0x08
 121 #define SPDCR_SLSEL0            0x04
 122 #define SPDCR_SLSEL_MASK        0x0c    /* SSL1 Output Select (SH) */
 123 #define SPDCR_SPFC1             0x02
 124 #define SPDCR_SPFC0             0x01
 125 #define SPDCR_SPFC_MASK         0x03    /* Frame Count Setting (1-4) (SH) */
 126
 127 /* SPCKD - Clock Delay Register */
 128 #define SPCKD_SCKDL_MASK        0x07    /* Clock Delay Setting (1-8) */
 129
 130 /* SSLND - Slave Select Negation Delay Register */
 131 #define SSLND_SLNDL_MASK        0x07    /* SSL Negation Delay Setting (1-8) */
 132
 133 /* SPND - Next-Access Delay Register */
 134 #define SPND_SPNDL_MASK         0x07    /* Next-Access Delay Setting (1-8) */
 135
 136 /* SPCR2 - Control Register 2 */
 137 #define SPCR2_PTE               0x08    /* Parity Self-Test Enable */
 138 #define SPCR2_SPIE              0x04    /* Idle Interrupt Enable */
 139 #define SPCR2_SPOE              0x02    /* Odd Parity Enable (vs. Even) */
 140 #define SPCR2_SPPE              0x01    /* Parity Enable */
 141
 142 /* SPCMDn - Command Registers */
 143 #define SPCMD_SCKDEN            0x8000  /* Clock Delay Setting Enable */
 144 #define SPCMD_SLNDEN            0x4000  /* SSL Negation Delay Setting Enable */
 145 #define SPCMD_SPNDEN            0x2000  /* Next-Access Delay Enable */
 146 #define SPCMD_LSBF              0x1000  /* LSB First */
 147 #define SPCMD_SPB_MASK          0x0f00  /* Data Length Setting */
 148 #define SPCMD_SPB_8_TO_16(bit)  (((bit - 1) << 8) & SPCMD_SPB_MASK)
 149 #define SPCMD_SPB_8BIT          0x0000  /* QSPI only */
 150 #define SPCMD_SPB_16BIT         0x0100
 151 #define SPCMD_SPB_20BIT         0x0000
 152 #define SPCMD_SPB_24BIT         0x0100
 153 #define SPCMD_SPB_32BIT         0x0200
 154 #define SPCMD_SSLKP             0x0080  /* SSL Signal Level Keeping */
 155 #define SPCMD_SPIMOD_MASK       0x0060  /* SPI Operating Mode (QSPI only) */
 156 #define SPCMD_SPIMOD1           0x0040
 157 #define SPCMD_SPIMOD0           0x0020
 158 #define SPCMD_SPIMOD_SINGLE     0
 159 #define SPCMD_SPIMOD_DUAL       SPCMD_SPIMOD0
 160 #define SPCMD_SPIMOD_QUAD       SPCMD_SPIMOD1
 161 #define SPCMD_SPRW              0x0010  /* SPI Read/Write Access (Dual/Quad) */
 162 #define SPCMD_SSLA(i)           ((i) << 4)      /* SSL Assert Signal Setting */
 163 #define SPCMD_BRDV_MASK         0x000c  /* Bit Rate Division Setting */
 164 #define SPCMD_BRDV(brdv)        ((brdv) << 2)
 165 #define SPCMD_CPOL              0x0002  /* Clock Polarity Setting */
 166 #define SPCMD_CPHA              0x0001  /* Clock Phase Setting */
 167
 168 /* SPBFCR - Buffer Control Register */
 169 #define SPBFCR_TXRST            0x80    /* Transmit Buffer Data Reset */
 170 #define SPBFCR_RXRST            0x40    /* Receive Buffer Data Reset */
 171 #define SPBFCR_TXTRG_MASK       0x30    /* Transmit Buffer Data Triggering Number */
 172 #define SPBFCR_RXTRG_MASK       0x07    /* Receive Buffer Data Triggering Number */
 173 /* QSPI on R-Car Gen2 */
 174 #define SPBFCR_TXTRG_1B         0x00    /* 31 bytes (1 byte available) */
 175 #define SPBFCR_TXTRG_32B        0x30    /* 0 byte (32 bytes available) */
 176 #define SPBFCR_RXTRG_1B         0x00    /* 1 byte (31 bytes available) */
 177 #define SPBFCR_RXTRG_32B        0x07    /* 32 bytes (0 byte available) */
 178
 179 #define QSPI_BUFFER_SIZE        32u
 180
 181 struct rspi_data {
 182         void __iomem *addr;
 183         u32 speed_hz;
 184         struct spi_controller *ctlr;
 185         struct platform_device *pdev;
 186         wait_queue_head_t wait;
 187         spinlock_t lock;                /* Protects RMW-access to RSPI_SSLP */
 188         struct clk *clk;
 189         u16 spcmd;
 190         u8 spsr;
 191         u8 sppcr;
 192         int rx_irq, tx_irq;
 193         const struct spi_ops *ops;
 194
 195         unsigned dma_callbacked:1;
 196         unsigned byte_access:1;
 197 };
 198
 199 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
 200 {
 201         iowrite8(data, rspi->addr + offset);
 202 }
 203
 204 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
 205 {
 206         iowrite16(data, rspi->addr + offset);
 207 }
 208
 209 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
 210 {
 211         iowrite32(data, rspi->addr + offset);
 212 }
 213
 214 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
 215 {
 216         return ioread8(rspi->addr + offset);
 217 }
 218
 219 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
 220 {
 221         return ioread16(rspi->addr + offset);
 222 }
 223
 224 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
 225 {
 226         if (rspi->byte_access)
 227                 rspi_write8(rspi, data, RSPI_SPDR);
 228         else /* 16 bit */
 229                 rspi_write16(rspi, data, RSPI_SPDR);
 230 }
 231
 232 static u16 rspi_read_data(const struct rspi_data *rspi)
 233 {
 234         if (rspi->byte_access)
 235                 return rspi_read8(rspi, RSPI_SPDR);
 236         else /* 16 bit */
 237                 return rspi_read16(rspi, RSPI_SPDR);
 238 }
 239
 240 /* optional functions */
 241 struct spi_ops {
 242         int (*set_config_register)(struct rspi_data *rspi, int access_size);
 243         int (*transfer_one)(struct spi_controller *ctlr,
 244                             struct spi_device *spi, struct spi_transfer *xfer);
 245         u16 extra_mode_bits;
 246         u16 min_div;
 247         u16 max_div;
 248         u16 flags;
 249         u16 fifo_size;
 250         u8 num_hw_ss;
 251 };
 252
 253 static void rspi_set_rate(struct rspi_data *rspi)
 254 {
 255         unsigned long clksrc;
 256         int brdv = 0, spbr;
 257
 258         clksrc = clk_get_rate(rspi->clk);
 259         spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
 260         while (spbr > 255 && brdv < 3) {
 261                 brdv++;
 262                 spbr = DIV_ROUND_UP(spbr + 1, 2) - 1;
 263         }
 264
 265         rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
 266         rspi->spcmd |= SPCMD_BRDV(brdv);
 267         rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1));
 268 }
 269
 270 /*
 271  * functions for RSPI on legacy SH
 272  */
 273 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
 274 {
 275         /* Sets output mode, MOSI signal, and (optionally) loopback */
 276         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
 277
 278         /* Sets transfer bit rate */
 279         rspi_set_rate(rspi);
 280
 281         /* Disable dummy transmission, set 16-bit word access, 1 frame */
 282         rspi_write8(rspi, 0, RSPI_SPDCR);
 283         rspi->byte_access = 0;
 284
 285         /* Sets RSPCK, SSL, next-access delay value */
 286         rspi_write8(rspi, 0x00, RSPI_SPCKD);
 287         rspi_write8(rspi, 0x00, RSPI_SSLND);
 288         rspi_write8(rspi, 0x00, RSPI_SPND);
 289
 290         /* Sets parity, interrupt mask */
 291         rspi_write8(rspi, 0x00, RSPI_SPCR2);
 292
 293         /* Resets sequencer */
 294         rspi_write8(rspi, 0, RSPI_SPSCR);
 295         rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
 296         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
 297
 298         /* Sets RSPI mode */
 299         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
 300
 301         return 0;
 302 }
 303
 304 /*
 305  * functions for RSPI on RZ
 306  */
 307 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
 308 {
 309         /* Sets output mode, MOSI signal, and (optionally) loopback */
 310         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
 311
 312         /* Sets transfer bit rate */
 313         rspi_set_rate(rspi);
 314
 315         /* Disable dummy transmission, set byte access */
 316         rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
 317         rspi->byte_access = 1;
 318
 319         /* Sets RSPCK, SSL, next-access delay value */
 320         rspi_write8(rspi, 0x00, RSPI_SPCKD);
 321         rspi_write8(rspi, 0x00, RSPI_SSLND);
 322         rspi_write8(rspi, 0x00, RSPI_SPND);
 323
 324         /* Resets sequencer */
 325         rspi_write8(rspi, 0, RSPI_SPSCR);
 326         rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
 327         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
 328
 329         /* Sets RSPI mode */
 330         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
 331
 332         return 0;
 333 }
 334
 335 /*
 336  * functions for QSPI
 337  */
 338 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
 339 {
 340         unsigned long clksrc;
 341         int brdv = 0, spbr;
 342
 343         /* Sets output mode, MOSI signal, and (optionally) loopback */
 344         rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
 345
 346         /* Sets transfer bit rate */
 347         clksrc = clk_get_rate(rspi->clk);
 348         if (rspi->speed_hz >= clksrc) {
 349                 spbr = 0;
 350                 rspi->speed_hz = clksrc;
 351         } else {
 352                 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);
 353                 while (spbr > 255 && brdv < 3) {
 354                         brdv++;
 355                         spbr = DIV_ROUND_UP(spbr, 2);
 356                 }
 357                 spbr = clamp(spbr, 0, 255);
 358                 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);
 359         }
 360         rspi_write8(rspi, spbr, RSPI_SPBR);
 361         rspi->spcmd |= SPCMD_BRDV(brdv);
 362
 363         /* Disable dummy transmission, set byte access */
 364         rspi_write8(rspi, 0, RSPI_SPDCR);
 365         rspi->byte_access = 1;
 366
 367         /* Sets RSPCK, SSL, next-access delay value */
 368         rspi_write8(rspi, 0x00, RSPI_SPCKD);
 369         rspi_write8(rspi, 0x00, RSPI_SSLND);
 370         rspi_write8(rspi, 0x00, RSPI_SPND);
 371
 372         /* Data Length Setting */
 373         if (access_size == 8)
 374                 rspi->spcmd |= SPCMD_SPB_8BIT;
 375         else if (access_size == 16)
 376                 rspi->spcmd |= SPCMD_SPB_16BIT;
 377         else
 378                 rspi->spcmd |= SPCMD_SPB_32BIT;
 379
 380         rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
 381
 382         /* Resets transfer data length */
 383         rspi_write32(rspi, 0, QSPI_SPBMUL0);
 384
 385         /* Resets transmit and receive buffer */
 386         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
 387         /* Sets buffer to allow normal operation */
 388         rspi_write8(rspi, 0x00, QSPI_SPBFCR);
 389
 390         /* Resets sequencer */
 391         rspi_write8(rspi, 0, RSPI_SPSCR);
 392         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
 393
 394         /* Sets RSPI mode */
 395         rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
 396
 397         return 0;
 398 }
 399
 400 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
 401 {
 402         u8 data;
 403
 404         data = rspi_read8(rspi, reg);
 405         data &= ~mask;
 406         data |= (val & mask);
 407         rspi_write8(rspi, data, reg);
 408 }
 409
 410 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
 411                                           unsigned int len)
 412 {
 413         unsigned int n;
 414
 415         n = min(len, QSPI_BUFFER_SIZE);
 416
 417         if (len >= QSPI_BUFFER_SIZE) {
 418                 /* sets triggering number to 32 bytes */
 419                 qspi_update(rspi, SPBFCR_TXTRG_MASK,
 420                              SPBFCR_TXTRG_32B, QSPI_SPBFCR);
 421         } else {
 422                 /* sets triggering number to 1 byte */
 423                 qspi_update(rspi, SPBFCR_TXTRG_MASK,
 424                              SPBFCR_TXTRG_1B, QSPI_SPBFCR);
 425         }
 426
 427         return n;
 428 }
 429
 430 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
 431 {
 432         unsigned int n;
 433
 434         n = min(len, QSPI_BUFFER_SIZE);
 435
 436         if (len >= QSPI_BUFFER_SIZE) {
 437                 /* sets triggering number to 32 bytes */
 438                 qspi_update(rspi, SPBFCR_RXTRG_MASK,
 439                              SPBFCR_RXTRG_32B, QSPI_SPBFCR);
 440         } else {
 441                 /* sets triggering number to 1 byte */
 442                 qspi_update(rspi, SPBFCR_RXTRG_MASK,
 443                              SPBFCR_RXTRG_1B, QSPI_SPBFCR);
 444         }
 445         return n;
 446 }
 447
 448 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
 449 {
 450         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
 451 }
 452
 453 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
 454 {
 455         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
 456 }
 457
 458 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
 459                                    u8 enable_bit)
 460 {
 461         int ret;
 462
 463         rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
 464         if (rspi->spsr & wait_mask)
 465                 return 0;
 466
 467         rspi_enable_irq(rspi, enable_bit);
 468         ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
 469         if (ret == 0 && !(rspi->spsr & wait_mask))
 470                 return -ETIMEDOUT;
 471
 472         return 0;
 473 }
 474
 475 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
 476 {
 477         return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
 478 }
 479
 480 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
 481 {
 482         return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
 483 }
 484
 485 static int rspi_data_out(struct rspi_data *rspi, u8 data)
 486 {
 487         int error = rspi_wait_for_tx_empty(rspi);
 488         if (error < 0) {
 489                 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
 490                 return error;
 491         }
 492         rspi_write_data(rspi, data);
 493         return 0;
 494 }
 495
 496 static int rspi_data_in(struct rspi_data *rspi)
 497 {
 498         int error;
 499         u8 data;
 500
 501         error = rspi_wait_for_rx_full(rspi);
 502         if (error < 0) {
 503                 dev_err(&rspi->ctlr->dev, "receive timeout\n");
 504                 return error;
 505         }
 506         data = rspi_read_data(rspi);
 507         return data;
 508 }
 509
 510 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
 511                              unsigned int n)
 512 {
 513         while (n-- > 0) {
 514                 if (tx) {
 515                         int ret = rspi_data_out(rspi, *tx++);
 516                         if (ret < 0)
 517                                 return ret;
 518                 }
 519                 if (rx) {
 520                         int ret = rspi_data_in(rspi);
 521                         if (ret < 0)
 522                                 return ret;
 523                         *rx++ = ret;
 524                 }
 525         }
 526
 527         return 0;
 528 }
 529
 530 static void rspi_dma_complete(void *arg)
 531 {
 532         struct rspi_data *rspi = arg;
 533
 534         rspi->dma_callbacked = 1;
 535         wake_up_interruptible(&rspi->wait);
 536 }
 537
 538 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
 539                              struct sg_table *rx)
 540 {
 541         struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
 542         u8 irq_mask = 0;
 543         unsigned int other_irq = 0;
 544         dma_cookie_t cookie;
 545         int ret;
 546
 547         /* First prepare and submit the DMA request(s), as this may fail */
 548         if (rx) {
 549                 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
 550                                         rx->nents, DMA_DEV_TO_MEM,
 551                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 552                 if (!desc_rx) {
 553                         ret = -EAGAIN;
 554                         goto no_dma_rx;
 555                 }
 556
 557                 desc_rx->callback = rspi_dma_complete;
 558                 desc_rx->callback_param = rspi;
 559                 cookie = dmaengine_submit(desc_rx);
 560                 if (dma_submit_error(cookie)) {
 561                         ret = cookie;
 562                         goto no_dma_rx;
 563                 }
 564
 565                 irq_mask |= SPCR_SPRIE;
 566         }
 567
 568         if (tx) {
 569                 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
 570                                         tx->nents, DMA_MEM_TO_DEV,
 571                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 572                 if (!desc_tx) {
 573                         ret = -EAGAIN;
 574                         goto no_dma_tx;
 575                 }
 576
 577                 if (rx) {
 578                         /* No callback */
 579                         desc_tx->callback = NULL;
 580                 } else {
 581                         desc_tx->callback = rspi_dma_complete;
 582                         desc_tx->callback_param = rspi;
 583                 }
 584                 cookie = dmaengine_submit(desc_tx);
 585                 if (dma_submit_error(cookie)) {
 586                         ret = cookie;
 587                         goto no_dma_tx;
 588                 }
 589
 590                 irq_mask |= SPCR_SPTIE;
 591         }
 592
 593         /*
 594          * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
 595          * called. So, this driver disables the IRQ while DMA transfer.
 596          */
 597         if (tx)
 598                 disable_irq(other_irq = rspi->tx_irq);
 599         if (rx && rspi->rx_irq != other_irq)
 600                 disable_irq(rspi->rx_irq);
 601
 602         rspi_enable_irq(rspi, irq_mask);
 603         rspi->dma_callbacked = 0;
 604
 605         /* Now start DMA */
 606         if (rx)
 607                 dma_async_issue_pending(rspi->ctlr->dma_rx);
 608         if (tx)
 609                 dma_async_issue_pending(rspi->ctlr->dma_tx);
 610
 611         ret = wait_event_interruptible_timeout(rspi->wait,
 612                                                rspi->dma_callbacked, HZ);
 613         if (ret > 0 && rspi->dma_callbacked) {
 614                 ret = 0;
 615                 if (tx)
 616                         dmaengine_synchronize(rspi->ctlr->dma_tx);
 617                 if (rx)
 618                         dmaengine_synchronize(rspi->ctlr->dma_rx);
 619         } else {
 620                 if (!ret) {
 621                         dev_err(&rspi->ctlr->dev, "DMA timeout\n");
 622                         ret = -ETIMEDOUT;
 623                 }
 624                 if (tx)
 625                         dmaengine_terminate_sync(rspi->ctlr->dma_tx);
 626                 if (rx)
 627                         dmaengine_terminate_sync(rspi->ctlr->dma_rx);
 628         }
 629
 630         rspi_disable_irq(rspi, irq_mask);
 631
 632         if (tx)
 633                 enable_irq(rspi->tx_irq);
 634         if (rx && rspi->rx_irq != other_irq)
 635                 enable_irq(rspi->rx_irq);
 636
 637         return ret;
 638
 639 no_dma_tx:
 640         if (rx)
 641                 dmaengine_terminate_sync(rspi->ctlr->dma_rx);
 642 no_dma_rx:
 643         if (ret == -EAGAIN) {
 644                 dev_warn_once(&rspi->ctlr->dev,
 645                               "DMA not available, falling back to PIO\n");
 646         }
 647         return ret;
 648 }
 649
 650 static void rspi_receive_init(const struct rspi_data *rspi)
 651 {
 652         u8 spsr;
 653
 654         spsr = rspi_read8(rspi, RSPI_SPSR);
 655         if (spsr & SPSR_SPRF)
 656                 rspi_read_data(rspi);   /* dummy read */
 657         if (spsr & SPSR_OVRF)
 658                 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
 659                             RSPI_SPSR);
 660 }
 661
 662 static void rspi_rz_receive_init(const struct rspi_data *rspi)
 663 {
 664         rspi_receive_init(rspi);
 665         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
 666         rspi_write8(rspi, 0, RSPI_SPBFCR);
 667 }
 668
 669 static void qspi_receive_init(const struct rspi_data *rspi)
 670 {
 671         u8 spsr;
 672
 673         spsr = rspi_read8(rspi, RSPI_SPSR);
 674         if (spsr & SPSR_SPRF)
 675                 rspi_read_data(rspi);   /* dummy read */
 676         rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
 677         rspi_write8(rspi, 0, QSPI_SPBFCR);
 678 }
 679
 680 static bool __rspi_can_dma(const struct rspi_data *rspi,
 681                            const struct spi_transfer *xfer)
 682 {
 683         return xfer->len > rspi->ops->fifo_size;
 684 }
 685
 686 static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
 687                          struct spi_transfer *xfer)
 688 {
 689         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 690
 691         return __rspi_can_dma(rspi, xfer);
 692 }
 693
 694 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
 695                                          struct spi_transfer *xfer)
 696 {
 697         if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
 698                 return -EAGAIN;
 699
 700         /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
 701         return rspi_dma_transfer(rspi, &xfer->tx_sg,
 702                                 xfer->rx_buf ? &xfer->rx_sg : NULL);
 703 }
 704
 705 static int rspi_common_transfer(struct rspi_data *rspi,
 706                                 struct spi_transfer *xfer)
 707 {
 708         int ret;
 709
 710         xfer->effective_speed_hz = rspi->speed_hz;
 711
 712         ret = rspi_dma_check_then_transfer(rspi, xfer);
 713         if (ret != -EAGAIN)
 714                 return ret;
 715
 716         ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
 717         if (ret < 0)
 718                 return ret;
 719
 720         /* Wait for the last transmission */
 721         rspi_wait_for_tx_empty(rspi);
 722
 723         return 0;
 724 }
 725
 726 static int rspi_transfer_one(struct spi_controller *ctlr,
 727                              struct spi_device *spi, struct spi_transfer *xfer)
 728 {
 729         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 730         u8 spcr;
 731
 732         spcr = rspi_read8(rspi, RSPI_SPCR);
 733         if (xfer->rx_buf) {
 734                 rspi_receive_init(rspi);
 735                 spcr &= ~SPCR_TXMD;
 736         } else {
 737                 spcr |= SPCR_TXMD;
 738         }
 739         rspi_write8(rspi, spcr, RSPI_SPCR);
 740
 741         return rspi_common_transfer(rspi, xfer);
 742 }
 743
 744 static int rspi_rz_transfer_one(struct spi_controller *ctlr,
 745                                 struct spi_device *spi,
 746                                 struct spi_transfer *xfer)
 747 {
 748         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 749
 750         rspi_rz_receive_init(rspi);
 751
 752         return rspi_common_transfer(rspi, xfer);
 753 }
 754
 755 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
 756                                         u8 *rx, unsigned int len)
 757 {
 758         unsigned int i, n;
 759         int ret;
 760
 761         while (len > 0) {
 762                 n = qspi_set_send_trigger(rspi, len);
 763                 qspi_set_receive_trigger(rspi, len);
 764                 ret = rspi_wait_for_tx_empty(rspi);
 765                 if (ret < 0) {
 766                         dev_err(&rspi->ctlr->dev, "transmit timeout\n");
 767                         return ret;
 768                 }
 769                 for (i = 0; i < n; i++)
 770                         rspi_write_data(rspi, *tx++);
 771
 772                 ret = rspi_wait_for_rx_full(rspi);
 773                 if (ret < 0) {
 774                         dev_err(&rspi->ctlr->dev, "receive timeout\n");
 775                         return ret;
 776                 }
 777                 for (i = 0; i < n; i++)
 778                         *rx++ = rspi_read_data(rspi);
 779
 780                 len -= n;
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int qspi_transfer_out_in(struct rspi_data *rspi,
 787                                 struct spi_transfer *xfer)
 788 {
 789         int ret;
 790
 791         qspi_receive_init(rspi);
 792
 793         ret = rspi_dma_check_then_transfer(rspi, xfer);
 794         if (ret != -EAGAIN)
 795                 return ret;
 796
 797         return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
 798                                             xfer->rx_buf, xfer->len);
 799 }
 800
 801 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
 802 {
 803         const u8 *tx = xfer->tx_buf;
 804         unsigned int n = xfer->len;
 805         unsigned int i, len;
 806         int ret;
 807
 808         if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
 809                 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
 810                 if (ret != -EAGAIN)
 811                         return ret;
 812         }
 813
 814         while (n > 0) {
 815                 len = qspi_set_send_trigger(rspi, n);
 816                 ret = rspi_wait_for_tx_empty(rspi);
 817                 if (ret < 0) {
 818                         dev_err(&rspi->ctlr->dev, "transmit timeout\n");
 819                         return ret;
 820                 }
 821                 for (i = 0; i < len; i++)
 822                         rspi_write_data(rspi, *tx++);
 823
 824                 n -= len;
 825         }
 826
 827         /* Wait for the last transmission */
 828         rspi_wait_for_tx_empty(rspi);
 829
 830         return 0;
 831 }
 832
 833 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
 834 {
 835         u8 *rx = xfer->rx_buf;
 836         unsigned int n = xfer->len;
 837         unsigned int i, len;
 838         int ret;
 839
 840         if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
 841                 ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
 842                 if (ret != -EAGAIN)
 843                         return ret;
 844         }
 845
 846         while (n > 0) {
 847                 len = qspi_set_receive_trigger(rspi, n);
 848                 ret = rspi_wait_for_rx_full(rspi);
 849                 if (ret < 0) {
 850                         dev_err(&rspi->ctlr->dev, "receive timeout\n");
 851                         return ret;
 852                 }
 853                 for (i = 0; i < len; i++)
 854                         *rx++ = rspi_read_data(rspi);
 855
 856                 n -= len;
 857         }
 858
 859         return 0;
 860 }
 861
 862 static int qspi_transfer_one(struct spi_controller *ctlr,
 863                              struct spi_device *spi, struct spi_transfer *xfer)
 864 {
 865         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 866
 867         xfer->effective_speed_hz = rspi->speed_hz;
 868         if (spi->mode & SPI_LOOP) {
 869                 return qspi_transfer_out_in(rspi, xfer);
 870         } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
 871                 /* Quad or Dual SPI Write */
 872                 return qspi_transfer_out(rspi, xfer);
 873         } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
 874                 /* Quad or Dual SPI Read */
 875                 return qspi_transfer_in(rspi, xfer);
 876         } else {
 877                 /* Single SPI Transfer */
 878                 return qspi_transfer_out_in(rspi, xfer);
 879         }
 880 }
 881
 882 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
 883 {
 884         if (xfer->tx_buf)
 885                 switch (xfer->tx_nbits) {
 886                 case SPI_NBITS_QUAD:
 887                         return SPCMD_SPIMOD_QUAD;
 888                 case SPI_NBITS_DUAL:
 889                         return SPCMD_SPIMOD_DUAL;
 890                 default:
 891                         return 0;
 892                 }
 893         if (xfer->rx_buf)
 894                 switch (xfer->rx_nbits) {
 895                 case SPI_NBITS_QUAD:
 896                         return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
 897                 case SPI_NBITS_DUAL:
 898                         return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
 899                 default:
 900                         return 0;
 901                 }
 902
 903         return 0;
 904 }
 905
 906 static int qspi_setup_sequencer(struct rspi_data *rspi,
 907                                 const struct spi_message *msg)
 908 {
 909         const struct spi_transfer *xfer;
 910         unsigned int i = 0, len = 0;
 911         u16 current_mode = 0xffff, mode;
 912
 913         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 914                 mode = qspi_transfer_mode(xfer);
 915                 if (mode == current_mode) {
 916                         len += xfer->len;
 917                         continue;
 918                 }
 919
 920                 /* Transfer mode change */
 921                 if (i) {
 922                         /* Set transfer data length of previous transfer */
 923                         rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
 924                 }
 925
 926                 if (i >= QSPI_NUM_SPCMD) {
 927                         dev_err(&msg->spi->dev,
 928                                 "Too many different transfer modes");
 929                         return -EINVAL;
 930                 }
 931
 932                 /* Program transfer mode for this transfer */
 933                 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
 934                 current_mode = mode;
 935                 len = xfer->len;
 936                 i++;
 937         }
 938         if (i) {
 939                 /* Set final transfer data length and sequence length */
 940                 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
 941                 rspi_write8(rspi, i - 1, RSPI_SPSCR);
 942         }
 943
 944         return 0;
 945 }
 946
 947 static int rspi_setup(struct spi_device *spi)
 948 {
 949         struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
 950         u8 sslp;
 951
 952         if (spi_get_csgpiod(spi, 0))
 953                 return 0;
 954
 955         pm_runtime_get_sync(&rspi->pdev->dev);
 956         spin_lock_irq(&rspi->lock);
 957
 958         sslp = rspi_read8(rspi, RSPI_SSLP);
 959         if (spi->mode & SPI_CS_HIGH)
 960                 sslp |= SSLP_SSLP(spi_get_chipselect(spi, 0));
 961         else
 962                 sslp &= ~SSLP_SSLP(spi_get_chipselect(spi, 0));
 963         rspi_write8(rspi, sslp, RSPI_SSLP);
 964
 965         spin_unlock_irq(&rspi->lock);
 966         pm_runtime_put(&rspi->pdev->dev);
 967         return 0;
 968 }
 969
 970 static int rspi_prepare_message(struct spi_controller *ctlr,
 971                                 struct spi_message *msg)
 972 {
 973         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
 974         struct spi_device *spi = msg->spi;
 975         const struct spi_transfer *xfer;
 976         int ret;
 977
 978         /*
 979          * As the Bit Rate Register must not be changed while the device is
 980          * active, all transfers in a message must use the same bit rate.
 981          * In theory, the sequencer could be enabled, and each Command Register
 982          * could divide the base bit rate by a different value.
 983          * However, most RSPI variants do not have Transfer Data Length
 984          * Multiplier Setting Registers, so each sequence step would be limited
 985          * to a single word, making this feature unsuitable for large
 986          * transfers, which would gain most from it.
 987          */
 988         rspi->speed_hz = spi->max_speed_hz;
 989         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 990                 if (xfer->speed_hz < rspi->speed_hz)
 991                         rspi->speed_hz = xfer->speed_hz;
 992         }
 993
 994         rspi->spcmd = SPCMD_SSLKP;
 995         if (spi->mode & SPI_CPOL)
 996                 rspi->spcmd |= SPCMD_CPOL;
 997         if (spi->mode & SPI_CPHA)
 998                 rspi->spcmd |= SPCMD_CPHA;
 999         if (spi->mode & SPI_LSB_FIRST)
1000                 rspi->spcmd |= SPCMD_LSBF;
1001
1002         /* Configure slave signal to assert */
1003         rspi->spcmd |= SPCMD_SSLA(spi_get_csgpiod(spi, 0) ? rspi->ctlr->unused_native_cs
1004                                                 : spi_get_chipselect(spi, 0));
1005
1006         /* CMOS output mode and MOSI signal from previous transfer */
1007         rspi->sppcr = 0;
1008         if (spi->mode & SPI_LOOP)
1009                 rspi->sppcr |= SPPCR_SPLP;
1010
1011         rspi->ops->set_config_register(rspi, 8);
1012
1013         if (msg->spi->mode &
1014             (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
1015                 /* Setup sequencer for messages with multiple transfer modes */
1016                 ret = qspi_setup_sequencer(rspi, msg);
1017                 if (ret < 0)
1018                         return ret;
1019         }
1020
1021         /* Enable SPI function in master mode */
1022         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
1023         return 0;
1024 }
1025
1026 static int rspi_unprepare_message(struct spi_controller *ctlr,
1027                                   struct spi_message *msg)
1028 {
1029         struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
1030
1031         /* Disable SPI function */
1032         rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
1033
1034         /* Reset sequencer for Single SPI Transfers */
1035         rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
1036         rspi_write8(rspi, 0, RSPI_SPSCR);
1037         return 0;
1038 }
1039
1040 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
1041 {
1042         struct rspi_data *rspi = _sr;
1043         u8 spsr;
1044         irqreturn_t ret = IRQ_NONE;
1045         u8 disable_irq = 0;
1046
1047         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1048         if (spsr & SPSR_SPRF)
1049                 disable_irq |= SPCR_SPRIE;
1050         if (spsr & SPSR_SPTEF)
1051                 disable_irq |= SPCR_SPTIE;
1052
1053         if (disable_irq) {
1054                 ret = IRQ_HANDLED;
1055                 rspi_disable_irq(rspi, disable_irq);
1056                 wake_up(&rspi->wait);
1057         }
1058
1059         return ret;
1060 }
1061
1062 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1063 {
1064         struct rspi_data *rspi = _sr;
1065         u8 spsr;
1066
1067         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1068         if (spsr & SPSR_SPRF) {
1069                 rspi_disable_irq(rspi, SPCR_SPRIE);
1070                 wake_up(&rspi->wait);
1071                 return IRQ_HANDLED;
1072         }
1073
1074         return 0;
1075 }
1076
1077 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1078 {
1079         struct rspi_data *rspi = _sr;
1080         u8 spsr;
1081
1082         rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1083         if (spsr & SPSR_SPTEF) {
1084                 rspi_disable_irq(rspi, SPCR_SPTIE);
1085                 wake_up(&rspi->wait);
1086                 return IRQ_HANDLED;
1087         }
1088
1089         return 0;
1090 }
1091
1092 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1093                                               enum dma_transfer_direction dir,
1094                                               unsigned int id,
1095                                               dma_addr_t port_addr)
1096 {
1097         dma_cap_mask_t mask;
1098         struct dma_chan *chan;
1099         struct dma_slave_config cfg;
1100         int ret;
1101
1102         dma_cap_zero(mask);
1103         dma_cap_set(DMA_SLAVE, mask);
1104
1105         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1106                                 (void *)(unsigned long)id, dev,
1107                                 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1108         if (!chan) {
1109                 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1110                 return NULL;
1111         }
1112
1113         memset(&cfg, 0, sizeof(cfg));
1114         cfg.dst_addr = port_addr + RSPI_SPDR;
1115         cfg.src_addr = port_addr + RSPI_SPDR;
1116         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1117         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1118         cfg.direction = dir;
1119
1120         ret = dmaengine_slave_config(chan, &cfg);
1121         if (ret) {
1122                 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1123                 dma_release_channel(chan);
1124                 return NULL;
1125         }
1126
1127         return chan;
1128 }
1129
1130 static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
1131                             const struct resource *res)
1132 {
1133         unsigned int dma_tx_id, dma_rx_id;
1134
1135         if (dev->of_node) {
1136                 /* In the OF case we will get the slave IDs from the DT */
1137                 dma_tx_id = 0;
1138                 dma_rx_id = 0;
1139         } else {
1140                 /* The driver assumes no error. */
1141                 return 0;
1142         }
1143
1144         ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1145                                              res->start);
1146         if (!ctlr->dma_tx)
1147                 return -ENODEV;
1148
1149         ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1150                                              res->start);
1151         if (!ctlr->dma_rx) {
1152                 dma_release_channel(ctlr->dma_tx);
1153                 ctlr->dma_tx = NULL;
1154                 return -ENODEV;
1155         }
1156
1157         ctlr->can_dma = rspi_can_dma;
1158         dev_info(dev, "DMA available");
1159         return 0;
1160 }
1161
1162 static void rspi_release_dma(struct spi_controller *ctlr)
1163 {
1164         if (ctlr->dma_tx)
1165                 dma_release_channel(ctlr->dma_tx);
1166         if (ctlr->dma_rx)
1167                 dma_release_channel(ctlr->dma_rx);
1168 }
1169
1170 static void rspi_remove(struct platform_device *pdev)
1171 {
1172         struct rspi_data *rspi = platform_get_drvdata(pdev);
1173
1174         rspi_release_dma(rspi->ctlr);
1175         pm_runtime_disable(&pdev->dev);
1176 }
1177
1178 static const struct spi_ops rspi_ops = {
1179         .set_config_register =  rspi_set_config_register,
1180         .transfer_one =         rspi_transfer_one,
1181         .min_div =              2,
1182         .max_div =              4096,
1183         .flags =                SPI_CONTROLLER_MUST_TX,
1184         .fifo_size =            8,
1185         .num_hw_ss =            2,
1186 };
1187
1188 static const struct spi_ops rspi_rz_ops __maybe_unused = {
1189         .set_config_register =  rspi_rz_set_config_register,
1190         .transfer_one =         rspi_rz_transfer_one,
1191         .min_div =              2,
1192         .max_div =              4096,
1193         .flags =                SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1194         .fifo_size =            8,      /* 8 for TX, 32 for RX */
1195         .num_hw_ss =            1,
1196 };
1197
1198 static const struct spi_ops qspi_ops __maybe_unused = {
1199         .set_config_register =  qspi_set_config_register,
1200         .transfer_one =         qspi_transfer_one,
1201         .extra_mode_bits =      SPI_TX_DUAL | SPI_TX_QUAD |
1202                                 SPI_RX_DUAL | SPI_RX_QUAD,
1203         .min_div =              1,
1204         .max_div =              4080,
1205         .flags =                SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1206         .fifo_size =            32,
1207         .num_hw_ss =            1,
1208 };
1209
1210 static const struct of_device_id rspi_of_match[] __maybe_unused = {
1211         /* RSPI on legacy SH */
1212         { .compatible = "renesas,rspi", .data = &rspi_ops },
1213         /* RSPI on RZ/A1H */
1214         { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1215         /* QSPI on R-Car Gen2 */
1216         { .compatible = "renesas,qspi", .data = &qspi_ops },
1217         { /* sentinel */ }
1218 };
1219
1220 MODULE_DEVICE_TABLE(of, rspi_of_match);
1221
1222 #ifdef CONFIG_OF
1223 static void rspi_reset_control_assert(void *data)
1224 {
1225         reset_control_assert(data);
1226 }
1227
1228 static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1229 {
1230         struct reset_control *rstc;
1231         u32 num_cs;
1232         int error;
1233
1234         /* Parse DT properties */
1235         error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1236         if (error) {
1237                 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1238                 return error;
1239         }
1240
1241         ctlr->num_chipselect = num_cs;
1242
1243         rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
1244         if (IS_ERR(rstc))
1245                 return dev_err_probe(dev, PTR_ERR(rstc),
1246                                              "failed to get reset ctrl\n");
1247
1248         error = reset_control_deassert(rstc);
1249         if (error) {
1250                 dev_err(dev, "failed to deassert reset %d\n", error);
1251                 return error;
1252         }
1253
1254         error = devm_add_action_or_reset(dev, rspi_reset_control_assert, rstc);
1255         if (error) {
1256                 dev_err(dev, "failed to register assert devm action, %d\n", error);
1257                 return error;
1258         }
1259
1260         return 0;
1261 }
1262 #else
1263 #define rspi_of_match   NULL
1264 static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1265 {
1266         return -EINVAL;
1267 }
1268 #endif /* CONFIG_OF */
1269
1270 static int rspi_request_irq(struct device *dev, unsigned int irq,
1271                             irq_handler_t handler, const char *suffix,
1272                             void *dev_id)
1273 {
1274         const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1275                                           dev_name(dev), suffix);
1276         if (!name)
1277                 return -ENOMEM;
1278
1279         return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1280 }
1281
1282 static int rspi_probe(struct platform_device *pdev)
1283 {
1284         struct resource *res;
1285         struct spi_controller *ctlr;
1286         struct rspi_data *rspi;
1287         int ret;
1288         const struct spi_ops *ops;
1289         unsigned long clksrc;
1290
1291         ctlr = spi_alloc_host(&pdev->dev, sizeof(struct rspi_data));
1292         if (ctlr == NULL)
1293                 return -ENOMEM;
1294
1295         ops = of_device_get_match_data(&pdev->dev);
1296         if (ops) {
1297                 ret = rspi_parse_dt(&pdev->dev, ctlr);
1298                 if (ret)
1299                         goto error1;
1300         } else {
1301                 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1302                 ctlr->num_chipselect = 2; /* default */
1303         }
1304
1305         rspi = spi_controller_get_devdata(ctlr);
1306         platform_set_drvdata(pdev, rspi);
1307         rspi->ops = ops;
1308         rspi->ctlr = ctlr;
1309
1310         rspi->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1311         if (IS_ERR(rspi->addr)) {
1312                 ret = PTR_ERR(rspi->addr);
1313                 goto error1;
1314         }
1315
1316         rspi->clk = devm_clk_get(&pdev->dev, NULL);
1317         if (IS_ERR(rspi->clk)) {
1318                 dev_err(&pdev->dev, "cannot get clock\n");
1319                 ret = PTR_ERR(rspi->clk);
1320                 goto error1;
1321         }
1322
1323         rspi->pdev = pdev;
1324         pm_runtime_enable(&pdev->dev);
1325
1326         init_waitqueue_head(&rspi->wait);
1327         spin_lock_init(&rspi->lock);
1328
1329         ctlr->bus_num = pdev->id;
1330         ctlr->setup = rspi_setup;
1331         ctlr->auto_runtime_pm = true;
1332         ctlr->transfer_one = ops->transfer_one;
1333         ctlr->prepare_message = rspi_prepare_message;
1334         ctlr->unprepare_message = rspi_unprepare_message;
1335         ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1336                           SPI_LOOP | ops->extra_mode_bits;
1337         clksrc = clk_get_rate(rspi->clk);
1338         ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div);
1339         ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div);
1340         ctlr->flags = ops->flags;
1341         ctlr->dev.of_node = pdev->dev.of_node;
1342         ctlr->use_gpio_descriptors = true;
1343         ctlr->max_native_cs = rspi->ops->num_hw_ss;
1344
1345         ret = platform_get_irq_byname_optional(pdev, "rx");
1346         if (ret < 0) {
1347                 ret = platform_get_irq_byname_optional(pdev, "mux");
1348                 if (ret < 0)
1349                         ret = platform_get_irq(pdev, 0);
1350                 if (ret >= 0)
1351                         rspi->rx_irq = rspi->tx_irq = ret;
1352         } else {
1353                 rspi->rx_irq = ret;
1354                 ret = platform_get_irq_byname(pdev, "tx");
1355                 if (ret >= 0)
1356                         rspi->tx_irq = ret;
1357         }
1358
1359         if (rspi->rx_irq == rspi->tx_irq) {
1360                 /* Single multiplexed interrupt */
1361                 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1362                                        "mux", rspi);
1363         } else {
1364                 /* Multi-interrupt mode, only SPRI and SPTI are used */
1365                 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1366                                        "rx", rspi);
1367                 if (!ret)
1368                         ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1369                                                rspi_irq_tx, "tx", rspi);
1370         }
1371         if (ret < 0) {
1372                 dev_err(&pdev->dev, "request_irq error\n");
1373                 goto error2;
1374         }
1375
1376         ret = rspi_request_dma(&pdev->dev, ctlr, res);
1377         if (ret < 0)
1378                 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1379
1380         ret = devm_spi_register_controller(&pdev->dev, ctlr);
1381         if (ret < 0) {
1382                 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1383                 goto error3;
1384         }
1385
1386         dev_info(&pdev->dev, "probed\n");
1387
1388         return 0;
1389
1390 error3:
1391         rspi_release_dma(ctlr);
1392 error2:
1393         pm_runtime_disable(&pdev->dev);
1394 error1:
1395         spi_controller_put(ctlr);
1396
1397         return ret;
1398 }
1399
1400 static const struct platform_device_id spi_driver_ids[] = {
1401         { "rspi",       (kernel_ulong_t)&rspi_ops },
1402         {},
1403 };
1404
1405 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1406
1407 #ifdef CONFIG_PM_SLEEP
1408 static int rspi_suspend(struct device *dev)
1409 {
1410         struct rspi_data *rspi = dev_get_drvdata(dev);
1411
1412         return spi_controller_suspend(rspi->ctlr);
1413 }
1414
1415 static int rspi_resume(struct device *dev)
1416 {
1417         struct rspi_data *rspi = dev_get_drvdata(dev);
1418
1419         return spi_controller_resume(rspi->ctlr);
1420 }
1421
1422 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1423 #define DEV_PM_OPS      &rspi_pm_ops
1424 #else
1425 #define DEV_PM_OPS      NULL
1426 #endif /* CONFIG_PM_SLEEP */
1427
1428 static struct platform_driver rspi_driver = {
1429         .probe =        rspi_probe,
1430         .remove_new =   rspi_remove,
1431         .id_table =     spi_driver_ids,
1432         .driver         = {
1433                 .name = "renesas_spi",
1434                 .pm = DEV_PM_OPS,
1435                 .of_match_table = of_match_ptr(rspi_of_match),
1436         },
1437 };
1438 module_platform_driver(rspi_driver);
1439
1440 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1441 MODULE_LICENSE("GPL v2");
1442 MODULE_AUTHOR("Yoshihiro Shimoda");