drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/omap-dma.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/err.h>
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32 #include <linux/slab.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/gcd.h>
  37
  38 #include <linux/spi/spi.h>
  39 #include <linux/gpio.h>
  40
  41 #include <linux/platform_data/spi-omap2-mcspi.h>
  42
  43 #define OMAP2_MCSPI_MAX_FREQ            48000000
  44 #define OMAP2_MCSPI_MAX_DIVIDER         4096
  45 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
  46 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
  47 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  48
  49 #define OMAP2_MCSPI_REVISION            0x00
  50 #define OMAP2_MCSPI_SYSSTATUS           0x14
  51 #define OMAP2_MCSPI_IRQSTATUS           0x18
  52 #define OMAP2_MCSPI_IRQENABLE           0x1c
  53 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  54 #define OMAP2_MCSPI_SYST                0x24
  55 #define OMAP2_MCSPI_MODULCTRL           0x28
  56 #define OMAP2_MCSPI_XFERLEVEL           0x7c
  57
  58 /* per-channel banks, 0x14 bytes each, first is: */
  59 #define OMAP2_MCSPI_CHCONF0             0x2c
  60 #define OMAP2_MCSPI_CHSTAT0             0x30
  61 #define OMAP2_MCSPI_CHCTRL0             0x34
  62 #define OMAP2_MCSPI_TX0                 0x38
  63 #define OMAP2_MCSPI_RX0                 0x3c
  64
  65 /* per-register bitmasks: */
  66 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
  67
  68 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  69 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  70 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  71
  72 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  73 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  74 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  75 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  76 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  77 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  78 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  79 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  80 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  81 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  82 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  83 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  84 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  85 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  86 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  87 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
  88 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
  89 #define OMAP2_MCSPI_CHCONF_CLKG         BIT(29)
  90
  91 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  92 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  93 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  94 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
  95
  96 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  97 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
  98
  99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
 100
 101 /* We have 2 DMA channels per CS, one for RX and one for TX */
 102 struct omap2_mcspi_dma {
 103         struct dma_chan *dma_tx;
 104         struct dma_chan *dma_rx;
 105
 106         int dma_tx_sync_dev;
 107         int dma_rx_sync_dev;
 108
 109         struct completion dma_tx_completion;
 110         struct completion dma_rx_completion;
 111
 112         char dma_rx_ch_name[14];
 113         char dma_tx_ch_name[14];
 114 };
 115
 116 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 117  * cache operations; better heuristics consider wordsize and bitrate.
 118  */
 119 #define DMA_MIN_BYTES                   160
 120
 121
 122 /*
 123  * Used for context save and restore, structure members to be updated whenever
 124  * corresponding registers are modified.
 125  */
 126 struct omap2_mcspi_regs {
 127         u32 modulctrl;
 128         u32 wakeupenable;
 129         struct list_head cs;
 130 };
 131
 132 struct omap2_mcspi {
 133         struct spi_master       *master;
 134         /* Virtual base address of the controller */
 135         void __iomem            *base;
 136         unsigned long           phys;
 137         /* SPI1 has 4 channels, while SPI2 has 2 */
 138         struct omap2_mcspi_dma  *dma_channels;
 139         struct device           *dev;
 140         struct omap2_mcspi_regs ctx;
 141         int                     fifo_depth;
 142         unsigned int            pin_dir:1;
 143 };
 144
 145 struct omap2_mcspi_cs {
 146         void __iomem            *base;
 147         unsigned long           phys;
 148         int                     word_len;
 149         u16                     mode;
 150         struct list_head        node;
 151         /* Context save and restore shadow register */
 152         u32                     chconf0, chctrl0;
 153 };
 154
 155 static inline void mcspi_write_reg(struct spi_master *master,
 156                 int idx, u32 val)
 157 {
 158         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 159
 160         writel_relaxed(val, mcspi->base + idx);
 161 }
 162
 163 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 164 {
 165         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 166
 167         return readl_relaxed(mcspi->base + idx);
 168 }
 169
 170 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 171                 int idx, u32 val)
 172 {
 173         struct omap2_mcspi_cs   *cs = spi->controller_state;
 174
 175         writel_relaxed(val, cs->base +  idx);
 176 }
 177
 178 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 179 {
 180         struct omap2_mcspi_cs   *cs = spi->controller_state;
 181
 182         return readl_relaxed(cs->base + idx);
 183 }
 184
 185 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 186 {
 187         struct omap2_mcspi_cs *cs = spi->controller_state;
 188
 189         return cs->chconf0;
 190 }
 191
 192 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 193 {
 194         struct omap2_mcspi_cs *cs = spi->controller_state;
 195
 196         cs->chconf0 = val;
 197         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 198         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 199 }
 200
 201 static inline int mcspi_bytes_per_word(int word_len)
 202 {
 203         if (word_len <= 8)
 204                 return 1;
 205         else if (word_len <= 16)
 206                 return 2;
 207         else /* word_len <= 32 */
 208                 return 4;
 209 }
 210
 211 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 212                 int is_read, int enable)
 213 {
 214         u32 l, rw;
 215
 216         l = mcspi_cached_chconf0(spi);
 217
 218         if (is_read) /* 1 is read, 0 write */
 219                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 220         else
 221                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 222
 223         if (enable)
 224                 l |= rw;
 225         else
 226                 l &= ~rw;
 227
 228         mcspi_write_chconf0(spi, l);
 229 }
 230
 231 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 232 {
 233         struct omap2_mcspi_cs *cs = spi->controller_state;
 234         u32 l;
 235
 236         l = cs->chctrl0;
 237         if (enable)
 238                 l |= OMAP2_MCSPI_CHCTRL_EN;
 239         else
 240                 l &= ~OMAP2_MCSPI_CHCTRL_EN;
 241         cs->chctrl0 = l;
 242         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 243         /* Flash post-writes */
 244         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 245 }
 246
 247 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
 248 {
 249         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 250         u32 l;
 251
 252         /* The controller handles the inverted chip selects
 253          * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
 254          * the inversion from the core spi_set_cs function.
 255          */
 256         if (spi->mode & SPI_CS_HIGH)
 257                 enable = !enable;
 258
 259         if (spi->controller_state) {
 260                 int err = pm_runtime_get_sync(mcspi->dev);
 261                 if (err < 0) {
 262                         dev_err(mcspi->dev, "failed to get sync: %d\n", err);
 263                         return;
 264                 }
 265
 266                 l = mcspi_cached_chconf0(spi);
 267
 268                 if (enable)
 269                         l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 270                 else
 271                         l |= OMAP2_MCSPI_CHCONF_FORCE;
 272
 273                 mcspi_write_chconf0(spi, l);
 274
 275                 pm_runtime_mark_last_busy(mcspi->dev);
 276                 pm_runtime_put_autosuspend(mcspi->dev);
 277         }
 278 }
 279
 280 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 281 {
 282         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 283         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 284         u32 l;
 285
 286         /*
 287          * Setup when switching from (reset default) slave mode
 288          * to single-channel master mode
 289          */
 290         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 291         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 292         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 293         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 294
 295         ctx->modulctrl = l;
 296 }
 297
 298 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
 299                                 struct spi_transfer *t, int enable)
 300 {
 301         struct spi_master *master = spi->master;
 302         struct omap2_mcspi_cs *cs = spi->controller_state;
 303         struct omap2_mcspi *mcspi;
 304         unsigned int wcnt;
 305         int max_fifo_depth, fifo_depth, bytes_per_word;
 306         u32 chconf, xferlevel;
 307
 308         mcspi = spi_master_get_devdata(master);
 309
 310         chconf = mcspi_cached_chconf0(spi);
 311         if (enable) {
 312                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
 313                 if (t->len % bytes_per_word != 0)
 314                         goto disable_fifo;
 315
 316                 if (t->rx_buf != NULL && t->tx_buf != NULL)
 317                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
 318                 else
 319                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
 320
 321                 fifo_depth = gcd(t->len, max_fifo_depth);
 322                 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
 323                         goto disable_fifo;
 324
 325                 wcnt = t->len / bytes_per_word;
 326                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
 327                         goto disable_fifo;
 328
 329                 xferlevel = wcnt << 16;
 330                 if (t->rx_buf != NULL) {
 331                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
 332                         xferlevel |= (fifo_depth - 1) << 8;
 333                 }
 334                 if (t->tx_buf != NULL) {
 335                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
 336                         xferlevel |= fifo_depth - 1;
 337                 }
 338
 339                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
 340                 mcspi_write_chconf0(spi, chconf);
 341                 mcspi->fifo_depth = fifo_depth;
 342
 343                 return;
 344         }
 345
 346 disable_fifo:
 347         if (t->rx_buf != NULL)
 348                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
 349
 350         if (t->tx_buf != NULL)
 351                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
 352
 353         mcspi_write_chconf0(spi, chconf);
 354         mcspi->fifo_depth = 0;
 355 }
 356
 357 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 358 {
 359         struct spi_master       *spi_cntrl = mcspi->master;
 360         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 361         struct omap2_mcspi_cs   *cs;
 362
 363         /* McSPI: context restore */
 364         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 365         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 366
 367         list_for_each_entry(cs, &ctx->cs, node)
 368                 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 369 }
 370
 371 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 372 {
 373         unsigned long timeout;
 374
 375         timeout = jiffies + msecs_to_jiffies(1000);
 376         while (!(readl_relaxed(reg) & bit)) {
 377                 if (time_after(jiffies, timeout)) {
 378                         if (!(readl_relaxed(reg) & bit))
 379                                 return -ETIMEDOUT;
 380                         else
 381                                 return 0;
 382                 }
 383                 cpu_relax();
 384         }
 385         return 0;
 386 }
 387
 388 static void omap2_mcspi_rx_callback(void *data)
 389 {
 390         struct spi_device *spi = data;
 391         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 392         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 393
 394         /* We must disable the DMA RX request */
 395         omap2_mcspi_set_dma_req(spi, 1, 0);
 396
 397         complete(&mcspi_dma->dma_rx_completion);
 398 }
 399
 400 static void omap2_mcspi_tx_callback(void *data)
 401 {
 402         struct spi_device *spi = data;
 403         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 404         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 405
 406         /* We must disable the DMA TX request */
 407         omap2_mcspi_set_dma_req(spi, 0, 0);
 408
 409         complete(&mcspi_dma->dma_tx_completion);
 410 }
 411
 412 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 413                                 struct spi_transfer *xfer,
 414                                 struct dma_slave_config cfg)
 415 {
 416         struct omap2_mcspi      *mcspi;
 417         struct omap2_mcspi_dma  *mcspi_dma;
 418         unsigned int            count;
 419
 420         mcspi = spi_master_get_devdata(spi->master);
 421         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 422         count = xfer->len;
 423
 424         if (mcspi_dma->dma_tx) {
 425                 struct dma_async_tx_descriptor *tx;
 426
 427                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 428
 429                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
 430                                              xfer->tx_sg.nents, DMA_MEM_TO_DEV,
 431                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 432                 if (tx) {
 433                         tx->callback = omap2_mcspi_tx_callback;
 434                         tx->callback_param = spi;
 435                         dmaengine_submit(tx);
 436                 } else {
 437                         /* FIXME: fall back to PIO? */
 438                 }
 439         }
 440         dma_async_issue_pending(mcspi_dma->dma_tx);
 441         omap2_mcspi_set_dma_req(spi, 0, 1);
 442
 443 }
 444
 445 static unsigned
 446 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 447                                 struct dma_slave_config cfg,
 448                                 unsigned es)
 449 {
 450         struct omap2_mcspi      *mcspi;
 451         struct omap2_mcspi_dma  *mcspi_dma;
 452         unsigned int            count, dma_count;
 453         u32                     l;
 454         int                     elements = 0;
 455         int                     word_len, element_count;
 456         struct omap2_mcspi_cs   *cs = spi->controller_state;
 457         mcspi = spi_master_get_devdata(spi->master);
 458         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 459         count = xfer->len;
 460         dma_count = xfer->len;
 461
 462         if (mcspi->fifo_depth == 0)
 463                 dma_count -= es;
 464
 465         word_len = cs->word_len;
 466         l = mcspi_cached_chconf0(spi);
 467
 468         if (word_len <= 8)
 469                 element_count = count;
 470         else if (word_len <= 16)
 471                 element_count = count >> 1;
 472         else /* word_len <= 32 */
 473                 element_count = count >> 2;
 474
 475         if (mcspi_dma->dma_rx) {
 476                 struct dma_async_tx_descriptor *tx;
 477
 478                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 479
 480                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
 481                         dma_count -= es;
 482
 483                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, xfer->rx_sg.sgl,
 484                                              xfer->rx_sg.nents, DMA_DEV_TO_MEM,
 485                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 486                 if (tx) {
 487                         tx->callback = omap2_mcspi_rx_callback;
 488                         tx->callback_param = spi;
 489                         dmaengine_submit(tx);
 490                 } else {
 491                                 /* FIXME: fall back to PIO? */
 492                 }
 493         }
 494
 495         dma_async_issue_pending(mcspi_dma->dma_rx);
 496         omap2_mcspi_set_dma_req(spi, 1, 1);
 497
 498         wait_for_completion(&mcspi_dma->dma_rx_completion);
 499
 500         if (mcspi->fifo_depth > 0)
 501                 return count;
 502
 503         omap2_mcspi_set_enable(spi, 0);
 504
 505         elements = element_count - 1;
 506
 507         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 508                 elements--;
 509
 510                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 511                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 512                         u32 w;
 513
 514                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 515                         if (word_len <= 8)
 516                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 517                         else if (word_len <= 16)
 518                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 519                         else /* word_len <= 32 */
 520                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 521                 } else {
 522                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 523                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
 524                         count -= (bytes_per_word << 1);
 525                         omap2_mcspi_set_enable(spi, 1);
 526                         return count;
 527                 }
 528         }
 529         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 530                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 531                 u32 w;
 532
 533                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 534                 if (word_len <= 8)
 535                         ((u8 *)xfer->rx_buf)[elements] = w;
 536                 else if (word_len <= 16)
 537                         ((u16 *)xfer->rx_buf)[elements] = w;
 538                 else /* word_len <= 32 */
 539                         ((u32 *)xfer->rx_buf)[elements] = w;
 540         } else {
 541                 dev_err(&spi->dev, "DMA RX last word empty\n");
 542                 count -= mcspi_bytes_per_word(word_len);
 543         }
 544         omap2_mcspi_set_enable(spi, 1);
 545         return count;
 546 }
 547
 548 static unsigned
 549 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 550 {
 551         struct omap2_mcspi      *mcspi;
 552         struct omap2_mcspi_cs   *cs = spi->controller_state;
 553         struct omap2_mcspi_dma  *mcspi_dma;
 554         unsigned int            count;
 555         u32                     l;
 556         u8                      *rx;
 557         const u8                *tx;
 558         struct dma_slave_config cfg;
 559         enum dma_slave_buswidth width;
 560         unsigned es;
 561         u32                     burst;
 562         void __iomem            *chstat_reg;
 563         void __iomem            *irqstat_reg;
 564         int                     wait_res;
 565
 566         mcspi = spi_master_get_devdata(spi->master);
 567         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 568         l = mcspi_cached_chconf0(spi);
 569
 570
 571         if (cs->word_len <= 8) {
 572                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 573                 es = 1;
 574         } else if (cs->word_len <= 16) {
 575                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 576                 es = 2;
 577         } else {
 578                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 579                 es = 4;
 580         }
 581
 582         count = xfer->len;
 583         burst = 1;
 584
 585         if (mcspi->fifo_depth > 0) {
 586                 if (count > mcspi->fifo_depth)
 587                         burst = mcspi->fifo_depth / es;
 588                 else
 589                         burst = count / es;
 590         }
 591
 592         memset(&cfg, 0, sizeof(cfg));
 593         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 594         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 595         cfg.src_addr_width = width;
 596         cfg.dst_addr_width = width;
 597         cfg.src_maxburst = burst;
 598         cfg.dst_maxburst = burst;
 599
 600         rx = xfer->rx_buf;
 601         tx = xfer->tx_buf;
 602
 603         if (tx != NULL)
 604                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 605
 606         if (rx != NULL)
 607                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 608
 609         if (tx != NULL) {
 610                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 611
 612                 if (mcspi->fifo_depth > 0) {
 613                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
 614
 615                         if (mcspi_wait_for_reg_bit(irqstat_reg,
 616                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
 617                                 dev_err(&spi->dev, "EOW timed out\n");
 618
 619                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
 620                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 621                 }
 622
 623                 /* for TX_ONLY mode, be sure all words have shifted out */
 624                 if (rx == NULL) {
 625                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 626                         if (mcspi->fifo_depth > 0) {
 627                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 628                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
 629                                 if (wait_res < 0)
 630                                         dev_err(&spi->dev, "TXFFE timed out\n");
 631                         } else {
 632                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 633                                                 OMAP2_MCSPI_CHSTAT_TXS);
 634                                 if (wait_res < 0)
 635                                         dev_err(&spi->dev, "TXS timed out\n");
 636                         }
 637                         if (wait_res >= 0 &&
 638                                 (mcspi_wait_for_reg_bit(chstat_reg,
 639                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
 640                                 dev_err(&spi->dev, "EOT timed out\n");
 641                 }
 642         }
 643         return count;
 644 }
 645
 646 static unsigned
 647 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 648 {
 649         struct omap2_mcspi      *mcspi;
 650         struct omap2_mcspi_cs   *cs = spi->controller_state;
 651         unsigned int            count, c;
 652         u32                     l;
 653         void __iomem            *base = cs->base;
 654         void __iomem            *tx_reg;
 655         void __iomem            *rx_reg;
 656         void __iomem            *chstat_reg;
 657         int                     word_len;
 658
 659         mcspi = spi_master_get_devdata(spi->master);
 660         count = xfer->len;
 661         c = count;
 662         word_len = cs->word_len;
 663
 664         l = mcspi_cached_chconf0(spi);
 665
 666         /* We store the pre-calculated register addresses on stack to speed
 667          * up the transfer loop. */
 668         tx_reg          = base + OMAP2_MCSPI_TX0;
 669         rx_reg          = base + OMAP2_MCSPI_RX0;
 670         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 671
 672         if (c < (word_len>>3))
 673                 return 0;
 674
 675         if (word_len <= 8) {
 676                 u8              *rx;
 677                 const u8        *tx;
 678
 679                 rx = xfer->rx_buf;
 680                 tx = xfer->tx_buf;
 681
 682                 do {
 683                         c -= 1;
 684                         if (tx != NULL) {
 685                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 686                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 687                                         dev_err(&spi->dev, "TXS timed out\n");
 688                                         goto out;
 689                                 }
 690                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 691                                                 word_len, *tx);
 692                                 writel_relaxed(*tx++, tx_reg);
 693                         }
 694                         if (rx != NULL) {
 695                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 696                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 697                                         dev_err(&spi->dev, "RXS timed out\n");
 698                                         goto out;
 699                                 }
 700
 701                                 if (c == 1 && tx == NULL &&
 702                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 703                                         omap2_mcspi_set_enable(spi, 0);
 704                                         *rx++ = readl_relaxed(rx_reg);
 705                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 706                                                     word_len, *(rx - 1));
 707                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 708                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 709                                                 dev_err(&spi->dev,
 710                                                         "RXS timed out\n");
 711                                                 goto out;
 712                                         }
 713                                         c = 0;
 714                                 } else if (c == 0 && tx == NULL) {
 715                                         omap2_mcspi_set_enable(spi, 0);
 716                                 }
 717
 718                                 *rx++ = readl_relaxed(rx_reg);
 719                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 720                                                 word_len, *(rx - 1));
 721                         }
 722                 } while (c);
 723         } else if (word_len <= 16) {
 724                 u16             *rx;
 725                 const u16       *tx;
 726
 727                 rx = xfer->rx_buf;
 728                 tx = xfer->tx_buf;
 729                 do {
 730                         c -= 2;
 731                         if (tx != NULL) {
 732                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 733                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 734                                         dev_err(&spi->dev, "TXS timed out\n");
 735                                         goto out;
 736                                 }
 737                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 738                                                 word_len, *tx);
 739                                 writel_relaxed(*tx++, tx_reg);
 740                         }
 741                         if (rx != NULL) {
 742                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 743                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 744                                         dev_err(&spi->dev, "RXS timed out\n");
 745                                         goto out;
 746                                 }
 747
 748                                 if (c == 2 && tx == NULL &&
 749                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 750                                         omap2_mcspi_set_enable(spi, 0);
 751                                         *rx++ = readl_relaxed(rx_reg);
 752                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 753                                                     word_len, *(rx - 1));
 754                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 755                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 756                                                 dev_err(&spi->dev,
 757                                                         "RXS timed out\n");
 758                                                 goto out;
 759                                         }
 760                                         c = 0;
 761                                 } else if (c == 0 && tx == NULL) {
 762                                         omap2_mcspi_set_enable(spi, 0);
 763                                 }
 764
 765                                 *rx++ = readl_relaxed(rx_reg);
 766                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 767                                                 word_len, *(rx - 1));
 768                         }
 769                 } while (c >= 2);
 770         } else if (word_len <= 32) {
 771                 u32             *rx;
 772                 const u32       *tx;
 773
 774                 rx = xfer->rx_buf;
 775                 tx = xfer->tx_buf;
 776                 do {
 777                         c -= 4;
 778                         if (tx != NULL) {
 779                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 780                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 781                                         dev_err(&spi->dev, "TXS timed out\n");
 782                                         goto out;
 783                                 }
 784                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 785                                                 word_len, *tx);
 786                                 writel_relaxed(*tx++, tx_reg);
 787                         }
 788                         if (rx != NULL) {
 789                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 790                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 791                                         dev_err(&spi->dev, "RXS timed out\n");
 792                                         goto out;
 793                                 }
 794
 795                                 if (c == 4 && tx == NULL &&
 796                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 797                                         omap2_mcspi_set_enable(spi, 0);
 798                                         *rx++ = readl_relaxed(rx_reg);
 799                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 800                                                     word_len, *(rx - 1));
 801                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 802                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 803                                                 dev_err(&spi->dev,
 804                                                         "RXS timed out\n");
 805                                                 goto out;
 806                                         }
 807                                         c = 0;
 808                                 } else if (c == 0 && tx == NULL) {
 809                                         omap2_mcspi_set_enable(spi, 0);
 810                                 }
 811
 812                                 *rx++ = readl_relaxed(rx_reg);
 813                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 814                                                 word_len, *(rx - 1));
 815                         }
 816                 } while (c >= 4);
 817         }
 818
 819         /* for TX_ONLY mode, be sure all words have shifted out */
 820         if (xfer->rx_buf == NULL) {
 821                 if (mcspi_wait_for_reg_bit(chstat_reg,
 822                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 823                         dev_err(&spi->dev, "TXS timed out\n");
 824                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 825                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 826                         dev_err(&spi->dev, "EOT timed out\n");
 827
 828                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 829                  * otherwise these rx datas will affect the direct following
 830                  * RX_ONLY transfer.
 831                  */
 832                 omap2_mcspi_set_enable(spi, 0);
 833         }
 834 out:
 835         omap2_mcspi_set_enable(spi, 1);
 836         return count - c;
 837 }
 838
 839 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 840 {
 841         u32 div;
 842
 843         for (div = 0; div < 15; div++)
 844                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 845                         return div;
 846
 847         return 15;
 848 }
 849
 850 /* called only when no transfer is active to this device */
 851 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 852                 struct spi_transfer *t)
 853 {
 854         struct omap2_mcspi_cs *cs = spi->controller_state;
 855         struct omap2_mcspi *mcspi;
 856         struct spi_master *spi_cntrl;
 857         u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
 858         u8 word_len = spi->bits_per_word;
 859         u32 speed_hz = spi->max_speed_hz;
 860
 861         mcspi = spi_master_get_devdata(spi->master);
 862         spi_cntrl = mcspi->master;
 863
 864         if (t != NULL && t->bits_per_word)
 865                 word_len = t->bits_per_word;
 866
 867         cs->word_len = word_len;
 868
 869         if (t && t->speed_hz)
 870                 speed_hz = t->speed_hz;
 871
 872         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 873         if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
 874                 clkd = omap2_mcspi_calc_divisor(speed_hz);
 875                 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
 876                 clkg = 0;
 877         } else {
 878                 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
 879                 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
 880                 clkd = (div - 1) & 0xf;
 881                 extclk = (div - 1) >> 4;
 882                 clkg = OMAP2_MCSPI_CHCONF_CLKG;
 883         }
 884
 885         l = mcspi_cached_chconf0(spi);
 886
 887         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 888          * REVISIT: this controller could support SPI_3WIRE mode.
 889          */
 890         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 891                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 892                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 893                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 894         } else {
 895                 l |= OMAP2_MCSPI_CHCONF_IS;
 896                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 897                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 898         }
 899
 900         /* wordlength */
 901         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 902         l |= (word_len - 1) << 7;
 903
 904         /* set chipselect polarity; manage with FORCE */
 905         if (!(spi->mode & SPI_CS_HIGH))
 906                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 907         else
 908                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 909
 910         /* set clock divisor */
 911         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 912         l |= clkd << 2;
 913
 914         /* set clock granularity */
 915         l &= ~OMAP2_MCSPI_CHCONF_CLKG;
 916         l |= clkg;
 917         if (clkg) {
 918                 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
 919                 cs->chctrl0 |= extclk << 8;
 920                 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 921         }
 922
 923         /* set SPI mode 0..3 */
 924         if (spi->mode & SPI_CPOL)
 925                 l |= OMAP2_MCSPI_CHCONF_POL;
 926         else
 927                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 928         if (spi->mode & SPI_CPHA)
 929                 l |= OMAP2_MCSPI_CHCONF_PHA;
 930         else
 931                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 932
 933         mcspi_write_chconf0(spi, l);
 934
 935         cs->mode = spi->mode;
 936
 937         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 938                         speed_hz,
 939                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 940                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 941
 942         return 0;
 943 }
 944
 945 /*
 946  * Note that we currently allow DMA only if we get a channel
 947  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 948  */
 949 static int omap2_mcspi_request_dma(struct spi_device *spi)
 950 {
 951         struct spi_master       *master = spi->master;
 952         struct omap2_mcspi      *mcspi;
 953         struct omap2_mcspi_dma  *mcspi_dma;
 954         dma_cap_mask_t mask;
 955         unsigned sig;
 956
 957         mcspi = spi_master_get_devdata(master);
 958         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 959
 960         init_completion(&mcspi_dma->dma_rx_completion);
 961         init_completion(&mcspi_dma->dma_tx_completion);
 962
 963         dma_cap_zero(mask);
 964         dma_cap_set(DMA_SLAVE, mask);
 965         sig = mcspi_dma->dma_rx_sync_dev;
 966
 967         mcspi_dma->dma_rx =
 968                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
 969                                                  &sig, &master->dev,
 970                                                  mcspi_dma->dma_rx_ch_name);
 971         if (!mcspi_dma->dma_rx)
 972                 goto no_dma;
 973
 974         sig = mcspi_dma->dma_tx_sync_dev;
 975         mcspi_dma->dma_tx =
 976                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
 977                                                  &sig, &master->dev,
 978                                                  mcspi_dma->dma_tx_ch_name);
 979
 980         if (!mcspi_dma->dma_tx) {
 981                 dma_release_channel(mcspi_dma->dma_rx);
 982                 mcspi_dma->dma_rx = NULL;
 983                 goto no_dma;
 984         }
 985
 986         return 0;
 987
 988 no_dma:
 989         dev_warn(&spi->dev, "not using DMA for McSPI\n");
 990         return -EAGAIN;
 991 }
 992
 993 static int omap2_mcspi_setup(struct spi_device *spi)
 994 {
 995         int                     ret;
 996         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 997         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 998         struct omap2_mcspi_dma  *mcspi_dma;
 999         struct omap2_mcspi_cs   *cs = spi->controller_state;
1000
1001         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1002
1003         if (!cs) {
1004                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1005                 if (!cs)
1006                         return -ENOMEM;
1007                 cs->base = mcspi->base + spi->chip_select * 0x14;
1008                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1009                 cs->mode = 0;
1010                 cs->chconf0 = 0;
1011                 cs->chctrl0 = 0;
1012                 spi->controller_state = cs;
1013                 /* Link this to context save list */
1014                 list_add_tail(&cs->node, &ctx->cs);
1015
1016                 if (gpio_is_valid(spi->cs_gpio)) {
1017                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1018                         if (ret) {
1019                                 dev_err(&spi->dev, "failed to request gpio\n");
1020                                 return ret;
1021                         }
1022                         gpio_direction_output(spi->cs_gpio,
1023                                          !(spi->mode & SPI_CS_HIGH));
1024                 }
1025         }
1026
1027         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1028                 ret = omap2_mcspi_request_dma(spi);
1029                 if (ret < 0 && ret != -EAGAIN)
1030                         return ret;
1031         }
1032
1033         ret = pm_runtime_get_sync(mcspi->dev);
1034         if (ret < 0)
1035                 return ret;
1036
1037         ret = omap2_mcspi_setup_transfer(spi, NULL);
1038         pm_runtime_mark_last_busy(mcspi->dev);
1039         pm_runtime_put_autosuspend(mcspi->dev);
1040
1041         return ret;
1042 }
1043
1044 static void omap2_mcspi_cleanup(struct spi_device *spi)
1045 {
1046         struct omap2_mcspi      *mcspi;
1047         struct omap2_mcspi_dma  *mcspi_dma;
1048         struct omap2_mcspi_cs   *cs;
1049
1050         mcspi = spi_master_get_devdata(spi->master);
1051
1052         if (spi->controller_state) {
1053                 /* Unlink controller state from context save list */
1054                 cs = spi->controller_state;
1055                 list_del(&cs->node);
1056
1057                 kfree(cs);
1058         }
1059
1060         if (spi->chip_select < spi->master->num_chipselect) {
1061                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1062
1063                 if (mcspi_dma->dma_rx) {
1064                         dma_release_channel(mcspi_dma->dma_rx);
1065                         mcspi_dma->dma_rx = NULL;
1066                 }
1067                 if (mcspi_dma->dma_tx) {
1068                         dma_release_channel(mcspi_dma->dma_tx);
1069                         mcspi_dma->dma_tx = NULL;
1070                 }
1071         }
1072
1073         if (gpio_is_valid(spi->cs_gpio))
1074                 gpio_free(spi->cs_gpio);
1075 }
1076
1077 static bool omap2_mcspi_can_dma(struct spi_master *master,
1078                                 struct spi_device *spi,
1079                                 struct spi_transfer *xfer)
1080 {
1081         if (xfer->len < DMA_MIN_BYTES)
1082                 return false;
1083
1084         return true;
1085 }
1086
1087 static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi,
1088                 struct spi_device *spi, struct spi_transfer *t)
1089 {
1090
1091         /* We only enable one channel at a time -- the one whose message is
1092          * -- although this controller would gladly
1093          * arbitrate among multiple channels.  This corresponds to "single
1094          * channel" master mode.  As a side effect, we need to manage the
1095          * chipselect with the FORCE bit ... CS != channel enable.
1096          */
1097
1098         struct spi_master               *master;
1099         struct omap2_mcspi_dma          *mcspi_dma;
1100         struct omap2_mcspi_cs           *cs;
1101         struct omap2_mcspi_device_config *cd;
1102         int                             par_override = 0;
1103         int                             status = 0;
1104         u32                             chconf;
1105
1106         master = spi->master;
1107         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1108         cs = spi->controller_state;
1109         cd = spi->controller_data;
1110
1111         /*
1112          * The slave driver could have changed spi->mode in which case
1113          * it will be different from cs->mode (the current hardware setup).
1114          * If so, set par_override (even though its not a parity issue) so
1115          * omap2_mcspi_setup_transfer will be called to configure the hardware
1116          * with the correct mode on the first iteration of the loop below.
1117          */
1118         if (spi->mode != cs->mode)
1119                 par_override = 1;
1120
1121         omap2_mcspi_set_enable(spi, 0);
1122
1123         if (gpio_is_valid(spi->cs_gpio))
1124                 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1125
1126         if (par_override ||
1127             (t->speed_hz != spi->max_speed_hz) ||
1128             (t->bits_per_word != spi->bits_per_word)) {
1129                 par_override = 1;
1130                 status = omap2_mcspi_setup_transfer(spi, t);
1131                 if (status < 0)
1132                         goto out;
1133                 if (t->speed_hz == spi->max_speed_hz &&
1134                     t->bits_per_word == spi->bits_per_word)
1135                         par_override = 0;
1136         }
1137         if (cd && cd->cs_per_word) {
1138                 chconf = mcspi->ctx.modulctrl;
1139                 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1140                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1141                 mcspi->ctx.modulctrl =
1142                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1143         }
1144
1145         chconf = mcspi_cached_chconf0(spi);
1146         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1147         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1148
1149         if (t->tx_buf == NULL)
1150                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1151         else if (t->rx_buf == NULL)
1152                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1153
1154         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1155                 /* Turbo mode is for more than one word */
1156                 if (t->len > ((cs->word_len + 7) >> 3))
1157                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1158         }
1159
1160         mcspi_write_chconf0(spi, chconf);
1161
1162         if (t->len) {
1163                 unsigned        count;
1164
1165                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1166                     (t->len >= DMA_MIN_BYTES))
1167                         omap2_mcspi_set_fifo(spi, t, 1);
1168
1169                 omap2_mcspi_set_enable(spi, 1);
1170
1171                 /* RX_ONLY mode needs dummy data in TX reg */
1172                 if (t->tx_buf == NULL)
1173                         writel_relaxed(0, cs->base
1174                                         + OMAP2_MCSPI_TX0);
1175
1176                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1177                     (t->len >= DMA_MIN_BYTES))
1178                         count = omap2_mcspi_txrx_dma(spi, t);
1179                 else
1180                         count = omap2_mcspi_txrx_pio(spi, t);
1181
1182                 if (count != t->len) {
1183                         status = -EIO;
1184                         goto out;
1185                 }
1186         }
1187
1188         omap2_mcspi_set_enable(spi, 0);
1189
1190         if (mcspi->fifo_depth > 0)
1191                 omap2_mcspi_set_fifo(spi, t, 0);
1192
1193 out:
1194         /* Restore defaults if they were overriden */
1195         if (par_override) {
1196                 par_override = 0;
1197                 status = omap2_mcspi_setup_transfer(spi, NULL);
1198         }
1199
1200         if (cd && cd->cs_per_word) {
1201                 chconf = mcspi->ctx.modulctrl;
1202                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1203                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1204                 mcspi->ctx.modulctrl =
1205                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1206         }
1207
1208         omap2_mcspi_set_enable(spi, 0);
1209
1210         if (gpio_is_valid(spi->cs_gpio))
1211                 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1212
1213         if (mcspi->fifo_depth > 0 && t)
1214                 omap2_mcspi_set_fifo(spi, t, 0);
1215
1216         return status;
1217 }
1218
1219 static int omap2_mcspi_prepare_message(struct spi_master *master,
1220                                        struct spi_message *msg)
1221 {
1222         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1223         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1224         struct omap2_mcspi_cs   *cs;
1225
1226         /* Only a single channel can have the FORCE bit enabled
1227          * in its chconf0 register.
1228          * Scan all channels and disable them except the current one.
1229          * A FORCE can remain from a last transfer having cs_change enabled
1230          */
1231         list_for_each_entry(cs, &ctx->cs, node) {
1232                 if (msg->spi->controller_state == cs)
1233                         continue;
1234
1235                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1236                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1237                         writel_relaxed(cs->chconf0,
1238                                         cs->base + OMAP2_MCSPI_CHCONF0);
1239                         readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1240                 }
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int omap2_mcspi_transfer_one(struct spi_master *master,
1247                 struct spi_device *spi, struct spi_transfer *t)
1248 {
1249         struct omap2_mcspi      *mcspi;
1250         struct omap2_mcspi_dma  *mcspi_dma;
1251         const void      *tx_buf = t->tx_buf;
1252         void            *rx_buf = t->rx_buf;
1253         unsigned        len = t->len;
1254
1255         mcspi = spi_master_get_devdata(master);
1256         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1257
1258         if ((len && !(rx_buf || tx_buf))) {
1259                 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1260                                 t->speed_hz,
1261                                 len,
1262                                 tx_buf ? "tx" : "",
1263                                 rx_buf ? "rx" : "",
1264                                 t->bits_per_word);
1265                 return -EINVAL;
1266         }
1267
1268         return omap2_mcspi_work_one(mcspi, spi, t);
1269 }
1270
1271 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1272 {
1273         struct spi_master       *master = mcspi->master;
1274         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1275         int                     ret = 0;
1276
1277         ret = pm_runtime_get_sync(mcspi->dev);
1278         if (ret < 0)
1279                 return ret;
1280
1281         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1282                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1283         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1284
1285         omap2_mcspi_set_master_mode(master);
1286         pm_runtime_mark_last_busy(mcspi->dev);
1287         pm_runtime_put_autosuspend(mcspi->dev);
1288         return 0;
1289 }
1290
1291 static int omap_mcspi_runtime_resume(struct device *dev)
1292 {
1293         struct omap2_mcspi      *mcspi;
1294         struct spi_master       *master;
1295
1296         master = dev_get_drvdata(dev);
1297         mcspi = spi_master_get_devdata(master);
1298         omap2_mcspi_restore_ctx(mcspi);
1299
1300         return 0;
1301 }
1302
1303 static struct omap2_mcspi_platform_config omap2_pdata = {
1304         .regs_offset = 0,
1305 };
1306
1307 static struct omap2_mcspi_platform_config omap4_pdata = {
1308         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1309 };
1310
1311 static const struct of_device_id omap_mcspi_of_match[] = {
1312         {
1313                 .compatible = "ti,omap2-mcspi",
1314                 .data = &omap2_pdata,
1315         },
1316         {
1317                 .compatible = "ti,omap4-mcspi",
1318                 .data = &omap4_pdata,
1319         },
1320         { },
1321 };
1322 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1323
1324 static int omap2_mcspi_probe(struct platform_device *pdev)
1325 {
1326         struct spi_master       *master;
1327         const struct omap2_mcspi_platform_config *pdata;
1328         struct omap2_mcspi      *mcspi;
1329         struct resource         *r;
1330         int                     status = 0, i;
1331         u32                     regs_offset = 0;
1332         static int              bus_num = 1;
1333         struct device_node      *node = pdev->dev.of_node;
1334         const struct of_device_id *match;
1335
1336         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1337         if (master == NULL) {
1338                 dev_dbg(&pdev->dev, "master allocation failed\n");
1339                 return -ENOMEM;
1340         }
1341
1342         /* the spi->mode bits understood by this driver: */
1343         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1344         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1345         master->setup = omap2_mcspi_setup;
1346         master->auto_runtime_pm = true;
1347         master->prepare_message = omap2_mcspi_prepare_message;
1348         master->transfer_one = omap2_mcspi_transfer_one;
1349         master->set_cs = omap2_mcspi_set_cs;
1350         master->cleanup = omap2_mcspi_cleanup;
1351         master->can_dma = omap2_mcspi_can_dma;
1352         master->dev.of_node = node;
1353         master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1354         master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1355
1356         platform_set_drvdata(pdev, master);
1357
1358         mcspi = spi_master_get_devdata(master);
1359         mcspi->master = master;
1360
1361         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1362         if (match) {
1363                 u32 num_cs = 1; /* default number of chipselect */
1364                 pdata = match->data;
1365
1366                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1367                 master->num_chipselect = num_cs;
1368                 master->bus_num = bus_num++;
1369                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1370                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1371         } else {
1372                 pdata = dev_get_platdata(&pdev->dev);
1373                 master->num_chipselect = pdata->num_cs;
1374                 if (pdev->id != -1)
1375                         master->bus_num = pdev->id;
1376                 mcspi->pin_dir = pdata->pin_dir;
1377         }
1378         regs_offset = pdata->regs_offset;
1379
1380         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1381         if (r == NULL) {
1382                 status = -ENODEV;
1383                 goto free_master;
1384         }
1385
1386         r->start += regs_offset;
1387         r->end += regs_offset;
1388         mcspi->phys = r->start;
1389
1390         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1391         if (IS_ERR(mcspi->base)) {
1392                 status = PTR_ERR(mcspi->base);
1393                 goto free_master;
1394         }
1395
1396         mcspi->dev = &pdev->dev;
1397
1398         INIT_LIST_HEAD(&mcspi->ctx.cs);
1399
1400         mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1401                                            sizeof(struct omap2_mcspi_dma),
1402                                            GFP_KERNEL);
1403         if (mcspi->dma_channels == NULL) {
1404                 status = -ENOMEM;
1405                 goto free_master;
1406         }
1407
1408         for (i = 0; i < master->num_chipselect; i++) {
1409                 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1410                 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1411                 struct resource *dma_res;
1412
1413                 sprintf(dma_rx_ch_name, "rx%d", i);
1414                 if (!pdev->dev.of_node) {
1415                         dma_res =
1416                                 platform_get_resource_byname(pdev,
1417                                                              IORESOURCE_DMA,
1418                                                              dma_rx_ch_name);
1419                         if (!dma_res) {
1420                                 dev_dbg(&pdev->dev,
1421                                         "cannot get DMA RX channel\n");
1422                                 status = -ENODEV;
1423                                 break;
1424                         }
1425
1426                         mcspi->dma_channels[i].dma_rx_sync_dev =
1427                                 dma_res->start;
1428                 }
1429                 sprintf(dma_tx_ch_name, "tx%d", i);
1430                 if (!pdev->dev.of_node) {
1431                         dma_res =
1432                                 platform_get_resource_byname(pdev,
1433                                                              IORESOURCE_DMA,
1434                                                              dma_tx_ch_name);
1435                         if (!dma_res) {
1436                                 dev_dbg(&pdev->dev,
1437                                         "cannot get DMA TX channel\n");
1438                                 status = -ENODEV;
1439                                 break;
1440                         }
1441
1442                         mcspi->dma_channels[i].dma_tx_sync_dev =
1443                                 dma_res->start;
1444                 }
1445         }
1446
1447         if (status < 0)
1448                 goto free_master;
1449
1450         pm_runtime_use_autosuspend(&pdev->dev);
1451         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1452         pm_runtime_enable(&pdev->dev);
1453
1454         status = omap2_mcspi_master_setup(mcspi);
1455         if (status < 0)
1456                 goto disable_pm;
1457
1458         status = devm_spi_register_master(&pdev->dev, master);
1459         if (status < 0)
1460                 goto disable_pm;
1461
1462         return status;
1463
1464 disable_pm:
1465         pm_runtime_dont_use_autosuspend(&pdev->dev);
1466         pm_runtime_put_sync(&pdev->dev);
1467         pm_runtime_disable(&pdev->dev);
1468 free_master:
1469         spi_master_put(master);
1470         return status;
1471 }
1472
1473 static int omap2_mcspi_remove(struct platform_device *pdev)
1474 {
1475         struct spi_master *master = platform_get_drvdata(pdev);
1476         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1477
1478         pm_runtime_dont_use_autosuspend(mcspi->dev);
1479         pm_runtime_put_sync(mcspi->dev);
1480         pm_runtime_disable(&pdev->dev);
1481
1482         return 0;
1483 }
1484
1485 /* work with hotplug and coldplug */
1486 MODULE_ALIAS("platform:omap2_mcspi");
1487
1488 #ifdef  CONFIG_SUSPEND
1489 /*
1490  * When SPI wake up from off-mode, CS is in activate state. If it was in
1491  * unactive state when driver was suspend, then force it to unactive state at
1492  * wake up.
1493  */
1494 static int omap2_mcspi_resume(struct device *dev)
1495 {
1496         struct spi_master       *master = dev_get_drvdata(dev);
1497         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1498         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1499         struct omap2_mcspi_cs   *cs;
1500
1501         pm_runtime_get_sync(mcspi->dev);
1502         list_for_each_entry(cs, &ctx->cs, node) {
1503                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1504                         /*
1505                          * We need to toggle CS state for OMAP take this
1506                          * change in account.
1507                          */
1508                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1509                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1510                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1511                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1512                 }
1513         }
1514         pm_runtime_mark_last_busy(mcspi->dev);
1515         pm_runtime_put_autosuspend(mcspi->dev);
1516
1517         return pinctrl_pm_select_default_state(dev);
1518 }
1519
1520 static int omap2_mcspi_suspend(struct device *dev)
1521 {
1522         return pinctrl_pm_select_sleep_state(dev);
1523 }
1524
1525 #else
1526 #define omap2_mcspi_suspend     NULL
1527 #define omap2_mcspi_resume      NULL
1528 #endif
1529
1530 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1531         .resume = omap2_mcspi_resume,
1532         .suspend = omap2_mcspi_suspend,
1533         .runtime_resume = omap_mcspi_runtime_resume,
1534 };
1535
1536 static struct platform_driver omap2_mcspi_driver = {
1537         .driver = {
1538                 .name =         "omap2_mcspi",
1539                 .pm =           &omap2_mcspi_pm_ops,
1540                 .of_match_table = omap_mcspi_of_match,
1541         },
1542         .probe =        omap2_mcspi_probe,
1543         .remove =       omap2_mcspi_remove,
1544 };
1545
1546 module_platform_driver(omap2_mcspi_driver);
1547 MODULE_LICENSE("GPL");