drivers/spi/au1550_spi.c

   1 /*
   2  * au1550_spi.c - au1550 psc spi controller driver
   3  * may work also with au1200, au1210, au1250
   4  * will not work on au1000, au1100 and au1500 (no full spi controller there)
   5  *
   6  * Copyright (c) 2006 ATRON electronic GmbH
   7  * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/errno.h>
  27 #include <linux/device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/resource.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/spi_bitbang.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/completion.h>
  34 #include <asm/mach-au1x00/au1000.h>
  35 #include <asm/mach-au1x00/au1xxx_psc.h>
  36 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  37
  38 #include <asm/mach-au1x00/au1550_spi.h>
  39
  40 static unsigned usedma = 1;
  41 module_param(usedma, uint, 0644);
  42
  43 /*
  44 #define AU1550_SPI_DEBUG_LOOPBACK
  45 */
  46
  47
  48 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
  49 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
  50
  51 struct au1550_spi {
  52         struct spi_bitbang bitbang;
  53
  54         volatile psc_spi_t __iomem *regs;
  55         int irq;
  56         unsigned freq_max;
  57         unsigned freq_min;
  58
  59         unsigned len;
  60         unsigned tx_count;
  61         unsigned rx_count;
  62         const u8 *tx;
  63         u8 *rx;
  64
  65         void (*rx_word)(struct au1550_spi *hw);
  66         void (*tx_word)(struct au1550_spi *hw);
  67         int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
  68         irqreturn_t (*irq_callback)(struct au1550_spi *hw);
  69
  70         struct completion master_done;
  71
  72         unsigned usedma;
  73         u32 dma_tx_id;
  74         u32 dma_rx_id;
  75         u32 dma_tx_ch;
  76         u32 dma_rx_ch;
  77
  78         u8 *dma_rx_tmpbuf;
  79         unsigned dma_rx_tmpbuf_size;
  80         u32 dma_rx_tmpbuf_addr;
  81
  82         struct spi_master *master;
  83         struct device *dev;
  84         struct au1550_spi_info *pdata;
  85         struct resource *ioarea;
  86 };
  87
  88
  89 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
  90 static dbdev_tab_t au1550_spi_mem_dbdev =
  91 {
  92         .dev_id                 = DBDMA_MEM_CHAN,
  93         .dev_flags              = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
  94         .dev_tsize              = 0,
  95         .dev_devwidth           = 8,
  96         .dev_physaddr           = 0x00000000,
  97         .dev_intlevel           = 0,
  98         .dev_intpolarity        = 0
  99 };
 100
 101 static int ddma_memid;  /* id to above mem dma device */
 102
 103 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
 104
 105
 106 /*
 107  *  compute BRG and DIV bits to setup spi clock based on main input clock rate
 108  *  that was specified in platform data structure
 109  *  according to au1550 datasheet:
 110  *    psc_tempclk = psc_mainclk / (2 << DIV)
 111  *    spiclk = psc_tempclk / (2 * (BRG + 1))
 112  *    BRG valid range is 4..63
 113  *    DIV valid range is 0..3
 114  */
 115 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
 116 {
 117         u32 mainclk_hz = hw->pdata->mainclk_hz;
 118         u32 div, brg;
 119
 120         for (div = 0; div < 4; div++) {
 121                 brg = mainclk_hz / speed_hz / (4 << div);
 122                 /* now we have BRG+1 in brg, so count with that */
 123                 if (brg < (4 + 1)) {
 124                         brg = (4 + 1);  /* speed_hz too big */
 125                         break;          /* set lowest brg (div is == 0) */
 126                 }
 127                 if (brg <= (63 + 1))
 128                         break;          /* we have valid brg and div */
 129         }
 130         if (div == 4) {
 131                 div = 3;                /* speed_hz too small */
 132                 brg = (63 + 1);         /* set highest brg and div */
 133         }
 134         brg--;
 135         return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
 136 }
 137
 138 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
 139 {
 140         hw->regs->psc_spimsk =
 141                   PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
 142                 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
 143                 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
 144         au_sync();
 145
 146         hw->regs->psc_spievent =
 147                   PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
 148                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
 149                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
 150         au_sync();
 151 }
 152
 153 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
 154 {
 155         u32 pcr;
 156
 157         hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
 158         au_sync();
 159         do {
 160                 pcr = hw->regs->psc_spipcr;
 161                 au_sync();
 162         } while (pcr != 0);
 163 }
 164
 165 /*
 166  * dma transfers are used for the most common spi word size of 8-bits
 167  * we cannot easily change already set up dma channels' width, so if we wanted
 168  * dma support for more than 8-bit words (up to 24 bits), we would need to
 169  * setup dma channels from scratch on each spi transfer, based on bits_per_word
 170  * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
 171  * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
 172  * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
 173  */
 174 static void au1550_spi_chipsel(struct spi_device *spi, int value)
 175 {
 176         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 177         unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 178         u32 cfg, stat;
 179
 180         switch (value) {
 181         case BITBANG_CS_INACTIVE:
 182                 if (hw->pdata->deactivate_cs)
 183                         hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
 184                                         cspol);
 185                 break;
 186
 187         case BITBANG_CS_ACTIVE:
 188                 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
 189
 190                 cfg = hw->regs->psc_spicfg;
 191                 au_sync();
 192                 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
 193                 au_sync();
 194
 195                 if (spi->mode & SPI_CPOL)
 196                         cfg |= PSC_SPICFG_BI;
 197                 else
 198                         cfg &= ~PSC_SPICFG_BI;
 199                 if (spi->mode & SPI_CPHA)
 200                         cfg &= ~PSC_SPICFG_CDE;
 201                 else
 202                         cfg |= PSC_SPICFG_CDE;
 203
 204                 if (spi->mode & SPI_LSB_FIRST)
 205                         cfg |= PSC_SPICFG_MLF;
 206                 else
 207                         cfg &= ~PSC_SPICFG_MLF;
 208
 209                 if (hw->usedma && spi->bits_per_word <= 8)
 210                         cfg &= ~PSC_SPICFG_DD_DISABLE;
 211                 else
 212                         cfg |= PSC_SPICFG_DD_DISABLE;
 213                 cfg = PSC_SPICFG_CLR_LEN(cfg);
 214                 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
 215
 216                 cfg = PSC_SPICFG_CLR_BAUD(cfg);
 217                 cfg &= ~PSC_SPICFG_SET_DIV(3);
 218                 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
 219
 220                 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
 221                 au_sync();
 222                 do {
 223                         stat = hw->regs->psc_spistat;
 224                         au_sync();
 225                 } while ((stat & PSC_SPISTAT_DR) == 0);
 226
 227                 if (hw->pdata->activate_cs)
 228                         hw->pdata->activate_cs(hw->pdata, spi->chip_select,
 229                                         cspol);
 230                 break;
 231         }
 232 }
 233
 234 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
 235 {
 236         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 237         unsigned bpw, hz;
 238         u32 cfg, stat;
 239
 240         bpw = t ? t->bits_per_word : spi->bits_per_word;
 241         hz = t ? t->speed_hz : spi->max_speed_hz;
 242
 243         if (bpw < 4 || bpw > 24) {
 244                 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
 245                         bpw);
 246                 return -EINVAL;
 247         }
 248         if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
 249                 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
 250                         hz);
 251                 return -EINVAL;
 252         }
 253
 254         au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
 255
 256         cfg = hw->regs->psc_spicfg;
 257         au_sync();
 258         hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
 259         au_sync();
 260
 261         if (hw->usedma && bpw <= 8)
 262                 cfg &= ~PSC_SPICFG_DD_DISABLE;
 263         else
 264                 cfg |= PSC_SPICFG_DD_DISABLE;
 265         cfg = PSC_SPICFG_CLR_LEN(cfg);
 266         cfg |= PSC_SPICFG_SET_LEN(bpw);
 267
 268         cfg = PSC_SPICFG_CLR_BAUD(cfg);
 269         cfg &= ~PSC_SPICFG_SET_DIV(3);
 270         cfg |= au1550_spi_baudcfg(hw, hz);
 271
 272         hw->regs->psc_spicfg = cfg;
 273         au_sync();
 274
 275         if (cfg & PSC_SPICFG_DE_ENABLE) {
 276                 do {
 277                         stat = hw->regs->psc_spistat;
 278                         au_sync();
 279                 } while ((stat & PSC_SPISTAT_DR) == 0);
 280         }
 281
 282         au1550_spi_reset_fifos(hw);
 283         au1550_spi_mask_ack_all(hw);
 284         return 0;
 285 }
 286
 287 /* the spi->mode bits understood by this driver: */
 288 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
 289
 290 static int au1550_spi_setup(struct spi_device *spi)
 291 {
 292         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 293
 294         if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
 295                 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
 296                         spi->bits_per_word);
 297                 return -EINVAL;
 298         }
 299
 300         if (spi->mode & ~MODEBITS) {
 301                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 302                         spi->mode & ~MODEBITS);
 303                 return -EINVAL;
 304         }
 305
 306         if (spi->max_speed_hz == 0)
 307                 spi->max_speed_hz = hw->freq_max;
 308         if (spi->max_speed_hz > hw->freq_max
 309                         || spi->max_speed_hz < hw->freq_min)
 310                 return -EINVAL;
 311         /*
 312          * NOTE: cannot change speed and other hw settings immediately,
 313          *       otherwise sharing of spi bus is not possible,
 314          *       so do not call setupxfer(spi, NULL) here
 315          */
 316         return 0;
 317 }
 318
 319 /*
 320  * for dma spi transfers, we have to setup rx channel, otherwise there is
 321  * no reliable way how to recognize that spi transfer is done
 322  * dma complete callbacks are called before real spi transfer is finished
 323  * and if only tx dma channel is set up (and rx fifo overflow event masked)
 324  * spi master done event irq is not generated unless rx fifo is empty (emptied)
 325  * so we need rx tmp buffer to use for rx dma if user does not provide one
 326  */
 327 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
 328 {
 329         hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
 330         if (!hw->dma_rx_tmpbuf)
 331                 return -ENOMEM;
 332         hw->dma_rx_tmpbuf_size = size;
 333         hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
 334                         size, DMA_FROM_DEVICE);
 335         if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
 336                 kfree(hw->dma_rx_tmpbuf);
 337                 hw->dma_rx_tmpbuf = 0;
 338                 hw->dma_rx_tmpbuf_size = 0;
 339                 return -EFAULT;
 340         }
 341         return 0;
 342 }
 343
 344 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
 345 {
 346         dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
 347                         hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
 348         kfree(hw->dma_rx_tmpbuf);
 349         hw->dma_rx_tmpbuf = 0;
 350         hw->dma_rx_tmpbuf_size = 0;
 351 }
 352
 353 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
 354 {
 355         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 356         dma_addr_t dma_tx_addr;
 357         dma_addr_t dma_rx_addr;
 358         u32 res;
 359
 360         hw->len = t->len;
 361         hw->tx_count = 0;
 362         hw->rx_count = 0;
 363
 364         hw->tx = t->tx_buf;
 365         hw->rx = t->rx_buf;
 366         dma_tx_addr = t->tx_dma;
 367         dma_rx_addr = t->rx_dma;
 368
 369         /*
 370          * check if buffers are already dma mapped, map them otherwise:
 371          * - first map the TX buffer, so cache data gets written to memory
 372          * - then map the RX buffer, so that cache entries (with
 373          *   soon-to-be-stale data) get removed
 374          * use rx buffer in place of tx if tx buffer was not provided
 375          * use temp rx buffer (preallocated or realloc to fit) for rx dma
 376          */
 377         if (t->tx_buf) {
 378                 if (t->tx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
 379                         dma_tx_addr = dma_map_single(hw->dev,
 380                                         (void *)t->tx_buf,
 381                                         t->len, DMA_TO_DEVICE);
 382                         if (dma_mapping_error(hw->dev, dma_tx_addr))
 383                                 dev_err(hw->dev, "tx dma map error\n");
 384                 }
 385         }
 386
 387         if (t->rx_buf) {
 388                 if (t->rx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
 389                         dma_rx_addr = dma_map_single(hw->dev,
 390                                         (void *)t->rx_buf,
 391                                         t->len, DMA_FROM_DEVICE);
 392                         if (dma_mapping_error(hw->dev, dma_rx_addr))
 393                                 dev_err(hw->dev, "rx dma map error\n");
 394                 }
 395         } else {
 396                 if (t->len > hw->dma_rx_tmpbuf_size) {
 397                         int ret;
 398
 399                         au1550_spi_dma_rxtmp_free(hw);
 400                         ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
 401                                         AU1550_SPI_DMA_RXTMP_MINSIZE));
 402                         if (ret < 0)
 403                                 return ret;
 404                 }
 405                 hw->rx = hw->dma_rx_tmpbuf;
 406                 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
 407                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
 408                         t->len, DMA_FROM_DEVICE);
 409         }
 410
 411         if (!t->tx_buf) {
 412                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
 413                                 t->len, DMA_BIDIRECTIONAL);
 414                 hw->tx = hw->rx;
 415         }
 416
 417         /* put buffers on the ring */
 418         res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
 419         if (!res)
 420                 dev_err(hw->dev, "rx dma put dest error\n");
 421
 422         res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
 423         if (!res)
 424                 dev_err(hw->dev, "tx dma put source error\n");
 425
 426         au1xxx_dbdma_start(hw->dma_rx_ch);
 427         au1xxx_dbdma_start(hw->dma_tx_ch);
 428
 429         /* by default enable nearly all events interrupt */
 430         hw->regs->psc_spimsk = PSC_SPIMSK_SD;
 431         au_sync();
 432
 433         /* start the transfer */
 434         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
 435         au_sync();
 436
 437         wait_for_completion(&hw->master_done);
 438
 439         au1xxx_dbdma_stop(hw->dma_tx_ch);
 440         au1xxx_dbdma_stop(hw->dma_rx_ch);
 441
 442         if (!t->rx_buf) {
 443                 /* using the temporal preallocated and premapped buffer */
 444                 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
 445                         DMA_FROM_DEVICE);
 446         }
 447         /* unmap buffers if mapped above */
 448         if (t->rx_buf && t->rx_dma == 0 )
 449                 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
 450                         DMA_FROM_DEVICE);
 451         if (t->tx_buf && t->tx_dma == 0 )
 452                 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
 453                         DMA_TO_DEVICE);
 454
 455         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
 456 }
 457
 458 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
 459 {
 460         u32 stat, evnt;
 461
 462         stat = hw->regs->psc_spistat;
 463         evnt = hw->regs->psc_spievent;
 464         au_sync();
 465         if ((stat & PSC_SPISTAT_DI) == 0) {
 466                 dev_err(hw->dev, "Unexpected IRQ!\n");
 467                 return IRQ_NONE;
 468         }
 469
 470         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
 471                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
 472                                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
 473                         != 0) {
 474                 /*
 475                  * due to an spi error we consider transfer as done,
 476                  * so mask all events until before next transfer start
 477                  * and stop the possibly running dma immediatelly
 478                  */
 479                 au1550_spi_mask_ack_all(hw);
 480                 au1xxx_dbdma_stop(hw->dma_rx_ch);
 481                 au1xxx_dbdma_stop(hw->dma_tx_ch);
 482
 483                 /* get number of transfered bytes */
 484                 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
 485                 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
 486
 487                 au1xxx_dbdma_reset(hw->dma_rx_ch);
 488                 au1xxx_dbdma_reset(hw->dma_tx_ch);
 489                 au1550_spi_reset_fifos(hw);
 490
 491                 if (evnt == PSC_SPIEVNT_RO)
 492                         dev_err(hw->dev,
 493                                 "dma transfer: receive FIFO overflow!\n");
 494                 else
 495                         dev_err(hw->dev,
 496                                 "dma transfer: unexpected SPI error "
 497                                 "(event=0x%x stat=0x%x)!\n", evnt, stat);
 498
 499                 complete(&hw->master_done);
 500                 return IRQ_HANDLED;
 501         }
 502
 503         if ((evnt & PSC_SPIEVNT_MD) != 0) {
 504                 /* transfer completed successfully */
 505                 au1550_spi_mask_ack_all(hw);
 506                 hw->rx_count = hw->len;
 507                 hw->tx_count = hw->len;
 508                 complete(&hw->master_done);
 509         }
 510         return IRQ_HANDLED;
 511 }
 512
 513
 514 /* routines to handle different word sizes in pio mode */
 515 #define AU1550_SPI_RX_WORD(size, mask)                                  \
 516 static void au1550_spi_rx_word_##size(struct au1550_spi *hw)            \
 517 {                                                                       \
 518         u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask);             \
 519         au_sync();                                                      \
 520         if (hw->rx) {                                                   \
 521                 *(u##size *)hw->rx = (u##size)fifoword;                 \
 522                 hw->rx += (size) / 8;                                   \
 523         }                                                               \
 524         hw->rx_count += (size) / 8;                                     \
 525 }
 526
 527 #define AU1550_SPI_TX_WORD(size, mask)                                  \
 528 static void au1550_spi_tx_word_##size(struct au1550_spi *hw)            \
 529 {                                                                       \
 530         u32 fifoword = 0;                                               \
 531         if (hw->tx) {                                                   \
 532                 fifoword = *(u##size *)hw->tx & (u32)(mask);            \
 533                 hw->tx += (size) / 8;                                   \
 534         }                                                               \
 535         hw->tx_count += (size) / 8;                                     \
 536         if (hw->tx_count >= hw->len)                                    \
 537                 fifoword |= PSC_SPITXRX_LC;                             \
 538         hw->regs->psc_spitxrx = fifoword;                               \
 539         au_sync();                                                      \
 540 }
 541
 542 AU1550_SPI_RX_WORD(8,0xff)
 543 AU1550_SPI_RX_WORD(16,0xffff)
 544 AU1550_SPI_RX_WORD(32,0xffffff)
 545 AU1550_SPI_TX_WORD(8,0xff)
 546 AU1550_SPI_TX_WORD(16,0xffff)
 547 AU1550_SPI_TX_WORD(32,0xffffff)
 548
 549 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
 550 {
 551         u32 stat, mask;
 552         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 553
 554         hw->tx = t->tx_buf;
 555         hw->rx = t->rx_buf;
 556         hw->len = t->len;
 557         hw->tx_count = 0;
 558         hw->rx_count = 0;
 559
 560         /* by default enable nearly all events after filling tx fifo */
 561         mask = PSC_SPIMSK_SD;
 562
 563         /* fill the transmit FIFO */
 564         while (hw->tx_count < hw->len) {
 565
 566                 hw->tx_word(hw);
 567
 568                 if (hw->tx_count >= hw->len) {
 569                         /* mask tx fifo request interrupt as we are done */
 570                         mask |= PSC_SPIMSK_TR;
 571                 }
 572
 573                 stat = hw->regs->psc_spistat;
 574                 au_sync();
 575                 if (stat & PSC_SPISTAT_TF)
 576                         break;
 577         }
 578
 579         /* enable event interrupts */
 580         hw->regs->psc_spimsk = mask;
 581         au_sync();
 582
 583         /* start the transfer */
 584         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
 585         au_sync();
 586
 587         wait_for_completion(&hw->master_done);
 588
 589         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
 590 }
 591
 592 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
 593 {
 594         int busy;
 595         u32 stat, evnt;
 596
 597         stat = hw->regs->psc_spistat;
 598         evnt = hw->regs->psc_spievent;
 599         au_sync();
 600         if ((stat & PSC_SPISTAT_DI) == 0) {
 601                 dev_err(hw->dev, "Unexpected IRQ!\n");
 602                 return IRQ_NONE;
 603         }
 604
 605         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
 606                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
 607                                 | PSC_SPIEVNT_SD))
 608                         != 0) {
 609                 /*
 610                  * due to an error we consider transfer as done,
 611                  * so mask all events until before next transfer start
 612                  */
 613                 au1550_spi_mask_ack_all(hw);
 614                 au1550_spi_reset_fifos(hw);
 615                 dev_err(hw->dev,
 616                         "pio transfer: unexpected SPI error "
 617                         "(event=0x%x stat=0x%x)!\n", evnt, stat);
 618                 complete(&hw->master_done);
 619                 return IRQ_HANDLED;
 620         }
 621
 622         /*
 623          * while there is something to read from rx fifo
 624          * or there is a space to write to tx fifo:
 625          */
 626         do {
 627                 busy = 0;
 628                 stat = hw->regs->psc_spistat;
 629                 au_sync();
 630
 631                 /*
 632                  * Take care to not let the Rx FIFO overflow.
 633                  *
 634                  * We only write a byte if we have read one at least. Initially,
 635                  * the write fifo is full, so we should read from the read fifo
 636                  * first.
 637                  * In case we miss a word from the read fifo, we should get a
 638                  * RO event and should back out.
 639                  */
 640                 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
 641                         hw->rx_word(hw);
 642                         busy = 1;
 643
 644                         if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
 645                                 hw->tx_word(hw);
 646                 }
 647         } while (busy);
 648
 649         hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
 650         au_sync();
 651
 652         /*
 653          * Restart the SPI transmission in case of a transmit underflow.
 654          * This seems to work despite the notes in the Au1550 data book
 655          * of Figure 8-4 with flowchart for SPI master operation:
 656          *
 657          * """Note 1: An XFR Error Interrupt occurs, unless masked,
 658          * for any of the following events: Tx FIFO Underflow,
 659          * Rx FIFO Overflow, or Multiple-master Error
 660          *    Note 2: In case of a Tx Underflow Error, all zeroes are
 661          * transmitted."""
 662          *
 663          * By simply restarting the spi transfer on Tx Underflow Error,
 664          * we assume that spi transfer was paused instead of zeroes
 665          * transmittion mentioned in the Note 2 of Au1550 data book.
 666          */
 667         if (evnt & PSC_SPIEVNT_TU) {
 668                 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
 669                 au_sync();
 670                 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
 671                 au_sync();
 672         }
 673
 674         if (hw->rx_count >= hw->len) {
 675                 /* transfer completed successfully */
 676                 au1550_spi_mask_ack_all(hw);
 677                 complete(&hw->master_done);
 678         }
 679         return IRQ_HANDLED;
 680 }
 681
 682 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 683 {
 684         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 685         return hw->txrx_bufs(spi, t);
 686 }
 687
 688 static irqreturn_t au1550_spi_irq(int irq, void *dev)
 689 {
 690         struct au1550_spi *hw = dev;
 691         return hw->irq_callback(hw);
 692 }
 693
 694 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
 695 {
 696         if (bpw <= 8) {
 697                 if (hw->usedma) {
 698                         hw->txrx_bufs = &au1550_spi_dma_txrxb;
 699                         hw->irq_callback = &au1550_spi_dma_irq_callback;
 700                 } else {
 701                         hw->rx_word = &au1550_spi_rx_word_8;
 702                         hw->tx_word = &au1550_spi_tx_word_8;
 703                         hw->txrx_bufs = &au1550_spi_pio_txrxb;
 704                         hw->irq_callback = &au1550_spi_pio_irq_callback;
 705                 }
 706         } else if (bpw <= 16) {
 707                 hw->rx_word = &au1550_spi_rx_word_16;
 708                 hw->tx_word = &au1550_spi_tx_word_16;
 709                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
 710                 hw->irq_callback = &au1550_spi_pio_irq_callback;
 711         } else {
 712                 hw->rx_word = &au1550_spi_rx_word_32;
 713                 hw->tx_word = &au1550_spi_tx_word_32;
 714                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
 715                 hw->irq_callback = &au1550_spi_pio_irq_callback;
 716         }
 717 }
 718
 719 static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
 720 {
 721         u32 stat, cfg;
 722
 723         /* set up the PSC for SPI mode */
 724         hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
 725         au_sync();
 726         hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
 727         au_sync();
 728
 729         hw->regs->psc_spicfg = 0;
 730         au_sync();
 731
 732         hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
 733         au_sync();
 734
 735         do {
 736                 stat = hw->regs->psc_spistat;
 737                 au_sync();
 738         } while ((stat & PSC_SPISTAT_SR) == 0);
 739
 740
 741         cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
 742         cfg |= PSC_SPICFG_SET_LEN(8);
 743         cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
 744         /* use minimal allowed brg and div values as initial setting: */
 745         cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
 746
 747 #ifdef AU1550_SPI_DEBUG_LOOPBACK
 748         cfg |= PSC_SPICFG_LB;
 749 #endif
 750
 751         hw->regs->psc_spicfg = cfg;
 752         au_sync();
 753
 754         au1550_spi_mask_ack_all(hw);
 755
 756         hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
 757         au_sync();
 758
 759         do {
 760                 stat = hw->regs->psc_spistat;
 761                 au_sync();
 762         } while ((stat & PSC_SPISTAT_DR) == 0);
 763
 764         au1550_spi_reset_fifos(hw);
 765 }
 766
 767
 768 static int __init au1550_spi_probe(struct platform_device *pdev)
 769 {
 770         struct au1550_spi *hw;
 771         struct spi_master *master;
 772         struct resource *r;
 773         int err = 0;
 774
 775         master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
 776         if (master == NULL) {
 777                 dev_err(&pdev->dev, "No memory for spi_master\n");
 778                 err = -ENOMEM;
 779                 goto err_nomem;
 780         }
 781
 782         hw = spi_master_get_devdata(master);
 783
 784         hw->master = spi_master_get(master);
 785         hw->pdata = pdev->dev.platform_data;
 786         hw->dev = &pdev->dev;
 787
 788         if (hw->pdata == NULL) {
 789                 dev_err(&pdev->dev, "No platform data supplied\n");
 790                 err = -ENOENT;
 791                 goto err_no_pdata;
 792         }
 793
 794         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 795         if (!r) {
 796                 dev_err(&pdev->dev, "no IRQ\n");
 797                 err = -ENODEV;
 798                 goto err_no_iores;
 799         }
 800         hw->irq = r->start;
 801
 802         hw->usedma = 0;
 803         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 804         if (r) {
 805                 hw->dma_tx_id = r->start;
 806                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 807                 if (r) {
 808                         hw->dma_rx_id = r->start;
 809                         if (usedma && ddma_memid) {
 810                                 if (pdev->dev.dma_mask == NULL)
 811                                         dev_warn(&pdev->dev, "no dma mask\n");
 812                                 else
 813                                         hw->usedma = 1;
 814                         }
 815                 }
 816         }
 817
 818         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 819         if (!r) {
 820                 dev_err(&pdev->dev, "no mmio resource\n");
 821                 err = -ENODEV;
 822                 goto err_no_iores;
 823         }
 824
 825         hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
 826                                         pdev->name);
 827         if (!hw->ioarea) {
 828                 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
 829                 err = -ENXIO;
 830                 goto err_no_iores;
 831         }
 832
 833         hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
 834         if (!hw->regs) {
 835                 dev_err(&pdev->dev, "cannot ioremap\n");
 836                 err = -ENXIO;
 837                 goto err_ioremap;
 838         }
 839
 840         platform_set_drvdata(pdev, hw);
 841
 842         init_completion(&hw->master_done);
 843
 844         hw->bitbang.master = hw->master;
 845         hw->bitbang.setup_transfer = au1550_spi_setupxfer;
 846         hw->bitbang.chipselect = au1550_spi_chipsel;
 847         hw->bitbang.master->setup = au1550_spi_setup;
 848         hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
 849
 850         if (hw->usedma) {
 851                 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
 852                         hw->dma_tx_id, NULL, (void *)hw);
 853                 if (hw->dma_tx_ch == 0) {
 854                         dev_err(&pdev->dev,
 855                                 "Cannot allocate tx dma channel\n");
 856                         err = -ENXIO;
 857                         goto err_no_txdma;
 858                 }
 859                 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
 860                 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
 861                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
 862                         dev_err(&pdev->dev,
 863                                 "Cannot allocate tx dma descriptors\n");
 864                         err = -ENXIO;
 865                         goto err_no_txdma_descr;
 866                 }
 867
 868
 869                 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
 870                         ddma_memid, NULL, (void *)hw);
 871                 if (hw->dma_rx_ch == 0) {
 872                         dev_err(&pdev->dev,
 873                                 "Cannot allocate rx dma channel\n");
 874                         err = -ENXIO;
 875                         goto err_no_rxdma;
 876                 }
 877                 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
 878                 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
 879                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
 880                         dev_err(&pdev->dev,
 881                                 "Cannot allocate rx dma descriptors\n");
 882                         err = -ENXIO;
 883                         goto err_no_rxdma_descr;
 884                 }
 885
 886                 err = au1550_spi_dma_rxtmp_alloc(hw,
 887                         AU1550_SPI_DMA_RXTMP_MINSIZE);
 888                 if (err < 0) {
 889                         dev_err(&pdev->dev,
 890                                 "Cannot allocate initial rx dma tmp buffer\n");
 891                         goto err_dma_rxtmp_alloc;
 892                 }
 893         }
 894
 895         au1550_spi_bits_handlers_set(hw, 8);
 896
 897         err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
 898         if (err) {
 899                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 900                 goto err_no_irq;
 901         }
 902
 903         master->bus_num = pdev->id;
 904         master->num_chipselect = hw->pdata->num_chipselect;
 905
 906         /*
 907          *  precompute valid range for spi freq - from au1550 datasheet:
 908          *    psc_tempclk = psc_mainclk / (2 << DIV)
 909          *    spiclk = psc_tempclk / (2 * (BRG + 1))
 910          *    BRG valid range is 4..63
 911          *    DIV valid range is 0..3
 912          *  round the min and max frequencies to values that would still
 913          *  produce valid brg and div
 914          */
 915         {
 916                 int min_div = (2 << 0) * (2 * (4 + 1));
 917                 int max_div = (2 << 3) * (2 * (63 + 1));
 918                 hw->freq_max = hw->pdata->mainclk_hz / min_div;
 919                 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
 920         }
 921
 922         au1550_spi_setup_psc_as_spi(hw);
 923
 924         err = spi_bitbang_start(&hw->bitbang);
 925         if (err) {
 926                 dev_err(&pdev->dev, "Failed to register SPI master\n");
 927                 goto err_register;
 928         }
 929
 930         dev_info(&pdev->dev,
 931                 "spi master registered: bus_num=%d num_chipselect=%d\n",
 932                 master->bus_num, master->num_chipselect);
 933
 934         return 0;
 935
 936 err_register:
 937         free_irq(hw->irq, hw);
 938
 939 err_no_irq:
 940         au1550_spi_dma_rxtmp_free(hw);
 941
 942 err_dma_rxtmp_alloc:
 943 err_no_rxdma_descr:
 944         if (hw->usedma)
 945                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
 946
 947 err_no_rxdma:
 948 err_no_txdma_descr:
 949         if (hw->usedma)
 950                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
 951
 952 err_no_txdma:
 953         iounmap((void __iomem *)hw->regs);
 954
 955 err_ioremap:
 956         release_resource(hw->ioarea);
 957         kfree(hw->ioarea);
 958
 959 err_no_iores:
 960 err_no_pdata:
 961         spi_master_put(hw->master);
 962
 963 err_nomem:
 964         return err;
 965 }
 966
 967 static int __exit au1550_spi_remove(struct platform_device *pdev)
 968 {
 969         struct au1550_spi *hw = platform_get_drvdata(pdev);
 970
 971         dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
 972                 hw->master->bus_num);
 973
 974         spi_bitbang_stop(&hw->bitbang);
 975         free_irq(hw->irq, hw);
 976         iounmap((void __iomem *)hw->regs);
 977         release_resource(hw->ioarea);
 978         kfree(hw->ioarea);
 979
 980         if (hw->usedma) {
 981                 au1550_spi_dma_rxtmp_free(hw);
 982                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
 983                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
 984         }
 985
 986         platform_set_drvdata(pdev, NULL);
 987
 988         spi_master_put(hw->master);
 989         return 0;
 990 }
 991
 992 /* work with hotplug and coldplug */
 993 MODULE_ALIAS("platform:au1550-spi");
 994
 995 static struct platform_driver au1550_spi_drv = {
 996         .remove = __exit_p(au1550_spi_remove),
 997         .driver = {
 998                 .name = "au1550-spi",
 999                 .owner = THIS_MODULE,
1000         },
1001 };
1002
1003 static int __init au1550_spi_init(void)
1004 {
1005         /*
1006          * create memory device with 8 bits dev_devwidth
1007          * needed for proper byte ordering to spi fifo
1008          */
1009         if (usedma) {
1010                 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
1011                 if (!ddma_memid)
1012                         printk(KERN_ERR "au1550-spi: cannot add memory"
1013                                         "dbdma device\n");
1014         }
1015         return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
1016 }
1017 module_init(au1550_spi_init);
1018
1019 static void __exit au1550_spi_exit(void)
1020 {
1021         if (usedma && ddma_memid)
1022                 au1xxx_ddma_del_device(ddma_memid);
1023         platform_driver_unregister(&au1550_spi_drv);
1024 }
1025 module_exit(au1550_spi_exit);
1026
1027 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
1028 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
1029 MODULE_LICENSE("GPL");