drivers/scsi/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *  The contents of this file are subject to the Open
  11  *  Software License version 1.1 that can be found at
  12  *  http://www.opensource.org/licenses/osl-1.1.txt and is included herein
  13  *  by reference.
  14  *
  15  *  Alternatively, the contents of this file may be used under the terms
  16  *  of the GNU General Public License version 2 (the "GPL") as distributed
  17  *  in the kernel source COPYING file, in which case the provisions of
  18  *  the GPL are applicable instead of the above.  If you wish to allow
  19  *  the use of your version of this file only under the terms of the
  20  *  GPL and not to allow others to use your version of this file under
  21  *  the OSL, indicate your decision by deleting the provisions above and
  22  *  replace them with the notice and other provisions required by the GPL.
  23  *  If you do not delete the provisions above, a recipient may use your
  24  *  version of this file under either the OSL or the GPL.
  25  *
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/init.h>
  32 #include <linux/blkdev.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/sched.h>
  36 #include "scsi.h"
  37 #include <scsi/scsi_host.h>
  38 #include <linux/libata.h>
  39 #include <asm/io.h>
  40 #include "sata_promise.h"
  41
  42 #define DRV_NAME        "sata_sx4"
  43 #define DRV_VERSION     "0.7"
  44
  45
  46 enum {
  47         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  48
  49         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  50         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  51         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  52         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  53
  54         PDC_20621_SEQCTL        = 0x400,
  55         PDC_20621_SEQMASK       = 0x480,
  56         PDC_20621_GENERAL_CTL   = 0x484,
  57         PDC_20621_PAGE_SIZE     = (32 * 1024),
  58
  59         /* chosen, not constant, values; we design our own DIMM mem map */
  60         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  61         PDC_20621_DIMM_BASE     = 0x00200000,
  62         PDC_20621_DIMM_DATA     = (64 * 1024),
  63         PDC_DIMM_DATA_STEP      = (256 * 1024),
  64         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  65         PDC_DIMM_HOST_PRD       = (6 * 1024),
  66         PDC_DIMM_HOST_PKT       = (128 * 0),
  67         PDC_DIMM_HPKT_PRD       = (128 * 1),
  68         PDC_DIMM_ATA_PKT        = (128 * 2),
  69         PDC_DIMM_APKT_PRD       = (128 * 3),
  70         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  71         PDC_PAGE_WINDOW         = 0x40,
  72         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  73                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  74         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  75
  76         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  77
  78         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  79                                   (1<<23),
  80
  81         board_20621             = 0,    /* FastTrak S150 SX4 */
  82
  83         PDC_RESET               = (1 << 11), /* HDMA reset */
  84
  85         PDC_MAX_HDMA            = 32,
  86         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  87
  88         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
  89         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
  90         PDC_MAX_DIMM_MODULE           = 0x02,
  91         PDC_I2C_CONTROL_OFFSET        = 0x48,
  92         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
  93         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
  94         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
  95         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
  96         PDC_I2C_WRITE                 = 0x00000000,
  97         PDC_I2C_READ                  = 0x00000040,
  98         PDC_I2C_START                 = 0x00000080,
  99         PDC_I2C_MASK_INT              = 0x00000020,
 100         PDC_I2C_COMPLETE              = 0x00010000,
 101         PDC_I2C_NO_ACK                = 0x00100000,
 102         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
 103         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
 104         PDC_DIMM_SPD_ROW_NUM          = 3,
 105         PDC_DIMM_SPD_COLUMN_NUM       = 4,
 106         PDC_DIMM_SPD_MODULE_ROW       = 5,
 107         PDC_DIMM_SPD_TYPE             = 11,
 108         PDC_DIMM_SPD_FRESH_RATE       = 12,
 109         PDC_DIMM_SPD_BANK_NUM         = 17,
 110         PDC_DIMM_SPD_CAS_LATENCY      = 18,
 111         PDC_DIMM_SPD_ATTRIBUTE        = 21,
 112         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
 113         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
 114         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
 115         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
 116         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
 117         PDC_CTL_STATUS                = 0x08,
 118         PDC_DIMM_WINDOW_CTLR          = 0x0C,
 119         PDC_TIME_CONTROL              = 0x3C,
 120         PDC_TIME_PERIOD               = 0x40,
 121         PDC_TIME_COUNTER              = 0x44,
 122         PDC_GENERAL_CTLR              = 0x484,
 123         PCI_PLL_INIT                  = 0x8A531824,
 124         PCI_X_TCOUNT                  = 0xEE1E5CFF
 125 };
 126
 127
 128 struct pdc_port_priv {
 129         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 130         u8                      *pkt;
 131         dma_addr_t              pkt_dma;
 132 };
 133
 134 struct pdc_host_priv {
 135         void                    *dimm_mmio;
 136
 137         unsigned int            doing_hdma;
 138         unsigned int            hdma_prod;
 139         unsigned int            hdma_cons;
 140         struct {
 141                 struct ata_queued_cmd *qc;
 142                 unsigned int    seq;
 143                 unsigned long   pkt_ofs;
 144         } hdma[32];
 145 };
 146
 147
 148 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 149 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
 150 static void pdc_eng_timeout(struct ata_port *ap);
 151 static void pdc_20621_phy_reset (struct ata_port *ap);
 152 static int pdc_port_start(struct ata_port *ap);
 153 static void pdc_port_stop(struct ata_port *ap);
 154 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
 155 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
 156 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
 157 static void pdc20621_host_stop(struct ata_host_set *host_set);
 158 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
 159 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
 160 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
 161                                       u32 device, u32 subaddr, u32 *pdata);
 162 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
 163 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
 164 #ifdef ATA_VERBOSE_DEBUG
 165 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
 166                                    void *psource, u32 offset, u32 size);
 167 #endif
 168 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
 169                                  void *psource, u32 offset, u32 size);
 170 static void pdc20621_irq_clear(struct ata_port *ap);
 171 static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
 172
 173
 174 static Scsi_Host_Template pdc_sata_sht = {
 175         .module                 = THIS_MODULE,
 176         .name                   = DRV_NAME,
 177         .ioctl                  = ata_scsi_ioctl,
 178         .queuecommand           = ata_scsi_queuecmd,
 179         .eh_strategy_handler    = ata_scsi_error,
 180         .can_queue              = ATA_DEF_QUEUE,
 181         .this_id                = ATA_SHT_THIS_ID,
 182         .sg_tablesize           = LIBATA_MAX_PRD,
 183         .max_sectors            = ATA_MAX_SECTORS,
 184         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 185         .emulated               = ATA_SHT_EMULATED,
 186         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 187         .proc_name              = DRV_NAME,
 188         .dma_boundary           = ATA_DMA_BOUNDARY,
 189         .slave_configure        = ata_scsi_slave_config,
 190         .bios_param             = ata_std_bios_param,
 191         .ordered_flush          = 1,
 192 };
 193
 194 static struct ata_port_operations pdc_20621_ops = {
 195         .port_disable           = ata_port_disable,
 196         .tf_load                = pdc_tf_load_mmio,
 197         .tf_read                = ata_tf_read,
 198         .check_status           = ata_check_status,
 199         .exec_command           = pdc_exec_command_mmio,
 200         .dev_select             = ata_std_dev_select,
 201         .phy_reset              = pdc_20621_phy_reset,
 202         .qc_prep                = pdc20621_qc_prep,
 203         .qc_issue               = pdc20621_qc_issue_prot,
 204         .eng_timeout            = pdc_eng_timeout,
 205         .irq_handler            = pdc20621_interrupt,
 206         .irq_clear              = pdc20621_irq_clear,
 207         .port_start             = pdc_port_start,
 208         .port_stop              = pdc_port_stop,
 209         .host_stop              = pdc20621_host_stop,
 210 };
 211
 212 static struct ata_port_info pdc_port_info[] = {
 213         /* board_20621 */
 214         {
 215                 .sht            = &pdc_sata_sht,
 216                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 217                                   ATA_FLAG_SRST | ATA_FLAG_MMIO,
 218                 .pio_mask       = 0x1f, /* pio0-4 */
 219                 .mwdma_mask     = 0x07, /* mwdma0-2 */
 220                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 221                 .port_ops       = &pdc_20621_ops,
 222         },
 223
 224 };
 225
 226 static struct pci_device_id pdc_sata_pci_tbl[] = {
 227         { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 228           board_20621 },
 229         { }     /* terminate list */
 230 };
 231
 232
 233 static struct pci_driver pdc_sata_pci_driver = {
 234         .name                   = DRV_NAME,
 235         .id_table               = pdc_sata_pci_tbl,
 236         .probe                  = pdc_sata_init_one,
 237         .remove                 = ata_pci_remove_one,
 238 };
 239
 240
 241 static void pdc20621_host_stop(struct ata_host_set *host_set)
 242 {
 243         struct pdc_host_priv *hpriv = host_set->private_data;
 244         void *dimm_mmio = hpriv->dimm_mmio;
 245
 246         iounmap(dimm_mmio);
 247         kfree(hpriv);
 248 }
 249
 250 static int pdc_port_start(struct ata_port *ap)
 251 {
 252         struct device *dev = ap->host_set->dev;
 253         struct pdc_port_priv *pp;
 254         int rc;
 255
 256         rc = ata_port_start(ap);
 257         if (rc)
 258                 return rc;
 259
 260         pp = kmalloc(sizeof(*pp), GFP_KERNEL);
 261         if (!pp) {
 262                 rc = -ENOMEM;
 263                 goto err_out;
 264         }
 265         memset(pp, 0, sizeof(*pp));
 266
 267         pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
 268         if (!pp->pkt) {
 269                 rc = -ENOMEM;
 270                 goto err_out_kfree;
 271         }
 272
 273         ap->private_data = pp;
 274
 275         return 0;
 276
 277 err_out_kfree:
 278         kfree(pp);
 279 err_out:
 280         ata_port_stop(ap);
 281         return rc;
 282 }
 283
 284
 285 static void pdc_port_stop(struct ata_port *ap)
 286 {
 287         struct device *dev = ap->host_set->dev;
 288         struct pdc_port_priv *pp = ap->private_data;
 289
 290         ap->private_data = NULL;
 291         dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
 292         kfree(pp);
 293         ata_port_stop(ap);
 294 }
 295
 296
 297 static void pdc_20621_phy_reset (struct ata_port *ap)
 298 {
 299         VPRINTK("ENTER\n");
 300         ap->cbl = ATA_CBL_SATA;
 301         ata_port_probe(ap);
 302         ata_bus_reset(ap);
 303 }
 304
 305 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 306                                            unsigned int portno,
 307                                            unsigned int total_len)
 308 {
 309         u32 addr;
 310         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 311         u32 *buf32 = (u32 *) buf;
 312
 313         /* output ATA packet S/G table */
 314         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 315                (PDC_DIMM_DATA_STEP * portno);
 316         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 317         buf32[dw] = cpu_to_le32(addr);
 318         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 319
 320         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 321                 PDC_20621_DIMM_BASE +
 322                        (PDC_DIMM_WINDOW_STEP * portno) +
 323                        PDC_DIMM_APKT_PRD,
 324                 buf32[dw], buf32[dw + 1]);
 325 }
 326
 327 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 328                                             unsigned int portno,
 329                                             unsigned int total_len)
 330 {
 331         u32 addr;
 332         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 333         u32 *buf32 = (u32 *) buf;
 334
 335         /* output Host DMA packet S/G table */
 336         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 337                (PDC_DIMM_DATA_STEP * portno);
 338
 339         buf32[dw] = cpu_to_le32(addr);
 340         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 341
 342         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 343                 PDC_20621_DIMM_BASE +
 344                        (PDC_DIMM_WINDOW_STEP * portno) +
 345                        PDC_DIMM_HPKT_PRD,
 346                 buf32[dw], buf32[dw + 1]);
 347 }
 348
 349 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 350                                             unsigned int devno, u8 *buf,
 351                                             unsigned int portno)
 352 {
 353         unsigned int i, dw;
 354         u32 *buf32 = (u32 *) buf;
 355         u8 dev_reg;
 356
 357         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 358                                (PDC_DIMM_WINDOW_STEP * portno) +
 359                                PDC_DIMM_APKT_PRD;
 360         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 361
 362         i = PDC_DIMM_ATA_PKT;
 363
 364         /*
 365          * Set up ATA packet
 366          */
 367         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 368                 buf[i++] = PDC_PKT_READ;
 369         else if (tf->protocol == ATA_PROT_NODATA)
 370                 buf[i++] = PDC_PKT_NODATA;
 371         else
 372                 buf[i++] = 0;
 373         buf[i++] = 0;                   /* reserved */
 374         buf[i++] = portno + 1;          /* seq. id */
 375         buf[i++] = 0xff;                /* delay seq. id */
 376
 377         /* dimm dma S/G, and next-pkt */
 378         dw = i >> 2;
 379         if (tf->protocol == ATA_PROT_NODATA)
 380                 buf32[dw] = 0;
 381         else
 382                 buf32[dw] = cpu_to_le32(dimm_sg);
 383         buf32[dw + 1] = 0;
 384         i += 8;
 385
 386         if (devno == 0)
 387                 dev_reg = ATA_DEVICE_OBS;
 388         else
 389                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 390
 391         /* select device */
 392         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 393         buf[i++] = dev_reg;
 394
 395         /* device control register */
 396         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 397         buf[i++] = tf->ctl;
 398
 399         return i;
 400 }
 401
 402 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 403                                      unsigned int portno)
 404 {
 405         unsigned int dw;
 406         u32 tmp, *buf32 = (u32 *) buf;
 407
 408         unsigned int host_sg = PDC_20621_DIMM_BASE +
 409                                (PDC_DIMM_WINDOW_STEP * portno) +
 410                                PDC_DIMM_HOST_PRD;
 411         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 412                                (PDC_DIMM_WINDOW_STEP * portno) +
 413                                PDC_DIMM_HPKT_PRD;
 414         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 415         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 416
 417         dw = PDC_DIMM_HOST_PKT >> 2;
 418
 419         /*
 420          * Set up Host DMA packet
 421          */
 422         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 423                 tmp = PDC_PKT_READ;
 424         else
 425                 tmp = 0;
 426         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 427         tmp |= (0xff << 24);                    /* delay seq. id */
 428         buf32[dw + 0] = cpu_to_le32(tmp);
 429         buf32[dw + 1] = cpu_to_le32(host_sg);
 430         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 431         buf32[dw + 3] = 0;
 432
 433         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 434                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 435                         PDC_DIMM_HOST_PKT,
 436                 buf32[dw + 0],
 437                 buf32[dw + 1],
 438                 buf32[dw + 2],
 439                 buf32[dw + 3]);
 440 }
 441
 442 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 443 {
 444         struct scatterlist *sg = qc->sg;
 445         struct ata_port *ap = qc->ap;
 446         struct pdc_port_priv *pp = ap->private_data;
 447         void *mmio = ap->host_set->mmio_base;
 448         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 449         void *dimm_mmio = hpriv->dimm_mmio;
 450         unsigned int portno = ap->port_no;
 451         unsigned int i, last, idx, total_len = 0, sgt_len;
 452         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 453
 454         assert(qc->flags & ATA_QCFLAG_DMAMAP);
 455
 456         VPRINTK("ata%u: ENTER\n", ap->id);
 457
 458         /* hard-code chip #0 */
 459         mmio += PDC_CHIP0_OFS;
 460
 461         /*
 462          * Build S/G table
 463          */
 464         last = qc->n_elem;
 465         idx = 0;
 466         for (i = 0; i < last; i++) {
 467                 buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i]));
 468                 buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i]));
 469                 total_len += sg[i].length;
 470         }
 471         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 472         sgt_len = idx * 4;
 473
 474         /*
 475          * Build ATA, host DMA packets
 476          */
 477         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 478         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 479
 480         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 481         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 482
 483         if (qc->tf.flags & ATA_TFLAG_LBA48)
 484                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 485         else
 486                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 487
 488         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 489
 490         /* copy three S/G tables and two packets to DIMM MMIO window */
 491         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 492                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 493         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 494                     PDC_DIMM_HOST_PRD,
 495                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 496
 497         /* force host FIFO dump */
 498         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 499
 500         readl(dimm_mmio);       /* MMIO PCI posting flush */
 501
 502         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 503 }
 504
 505 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 506 {
 507         struct ata_port *ap = qc->ap;
 508         struct pdc_port_priv *pp = ap->private_data;
 509         void *mmio = ap->host_set->mmio_base;
 510         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 511         void *dimm_mmio = hpriv->dimm_mmio;
 512         unsigned int portno = ap->port_no;
 513         unsigned int i;
 514
 515         VPRINTK("ata%u: ENTER\n", ap->id);
 516
 517         /* hard-code chip #0 */
 518         mmio += PDC_CHIP0_OFS;
 519
 520         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 521
 522         if (qc->tf.flags & ATA_TFLAG_LBA48)
 523                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 524         else
 525                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 526
 527         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 528
 529         /* copy three S/G tables and two packets to DIMM MMIO window */
 530         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 531                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 532
 533         /* force host FIFO dump */
 534         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 535
 536         readl(dimm_mmio);       /* MMIO PCI posting flush */
 537
 538         VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
 539 }
 540
 541 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
 542 {
 543         switch (qc->tf.protocol) {
 544         case ATA_PROT_DMA:
 545                 pdc20621_dma_prep(qc);
 546                 break;
 547         case ATA_PROT_NODATA:
 548                 pdc20621_nodata_prep(qc);
 549                 break;
 550         default:
 551                 break;
 552         }
 553 }
 554
 555 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 556                                  unsigned int seq,
 557                                  u32 pkt_ofs)
 558 {
 559         struct ata_port *ap = qc->ap;
 560         struct ata_host_set *host_set = ap->host_set;
 561         void *mmio = host_set->mmio_base;
 562
 563         /* hard-code chip #0 */
 564         mmio += PDC_CHIP0_OFS;
 565
 566         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 567         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 568
 569         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 570         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 571 }
 572
 573 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 574                                 unsigned int seq,
 575                                 u32 pkt_ofs)
 576 {
 577         struct ata_port *ap = qc->ap;
 578         struct pdc_host_priv *pp = ap->host_set->private_data;
 579         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 580
 581         if (!pp->doing_hdma) {
 582                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 583                 pp->doing_hdma = 1;
 584                 return;
 585         }
 586
 587         pp->hdma[idx].qc = qc;
 588         pp->hdma[idx].seq = seq;
 589         pp->hdma[idx].pkt_ofs = pkt_ofs;
 590         pp->hdma_prod++;
 591 }
 592
 593 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 594 {
 595         struct ata_port *ap = qc->ap;
 596         struct pdc_host_priv *pp = ap->host_set->private_data;
 597         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 598
 599         /* if nothing on queue, we're done */
 600         if (pp->hdma_prod == pp->hdma_cons) {
 601                 pp->doing_hdma = 0;
 602                 return;
 603         }
 604
 605         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 606                              pp->hdma[idx].pkt_ofs);
 607         pp->hdma_cons++;
 608 }
 609
 610 #ifdef ATA_VERBOSE_DEBUG
 611 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 612 {
 613         struct ata_port *ap = qc->ap;
 614         unsigned int port_no = ap->port_no;
 615         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 616         void *dimm_mmio = hpriv->dimm_mmio;
 617
 618         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 619         dimm_mmio += PDC_DIMM_HOST_PKT;
 620
 621         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 622         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 623         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 624         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 625 }
 626 #else
 627 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 628 #endif /* ATA_VERBOSE_DEBUG */
 629
 630 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 631 {
 632         struct ata_port *ap = qc->ap;
 633         struct ata_host_set *host_set = ap->host_set;
 634         unsigned int port_no = ap->port_no;
 635         void *mmio = host_set->mmio_base;
 636         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 637         u8 seq = (u8) (port_no + 1);
 638         unsigned int port_ofs;
 639
 640         /* hard-code chip #0 */
 641         mmio += PDC_CHIP0_OFS;
 642
 643         VPRINTK("ata%u: ENTER\n", ap->id);
 644
 645         wmb();                  /* flush PRD, pkt writes */
 646
 647         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 648
 649         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 650         if (rw && qc->tf.protocol == ATA_PROT_DMA) {
 651                 seq += 4;
 652
 653                 pdc20621_dump_hdma(qc);
 654                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 655                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 656                         port_ofs + PDC_DIMM_HOST_PKT,
 657                         port_ofs + PDC_DIMM_HOST_PKT,
 658                         seq);
 659         } else {
 660                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 661                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 662
 663                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 664                        (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 665                 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 666                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 667                         port_ofs + PDC_DIMM_ATA_PKT,
 668                         port_ofs + PDC_DIMM_ATA_PKT,
 669                         seq);
 670         }
 671 }
 672
 673 static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
 674 {
 675         switch (qc->tf.protocol) {
 676         case ATA_PROT_DMA:
 677         case ATA_PROT_NODATA:
 678                 pdc20621_packet_start(qc);
 679                 return 0;
 680
 681         case ATA_PROT_ATAPI_DMA:
 682                 BUG();
 683                 break;
 684
 685         default:
 686                 break;
 687         }
 688
 689         return ata_qc_issue_prot(qc);
 690 }
 691
 692 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 693                                           struct ata_queued_cmd *qc,
 694                                           unsigned int doing_hdma,
 695                                           void *mmio)
 696 {
 697         unsigned int port_no = ap->port_no;
 698         unsigned int port_ofs =
 699                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 700         u8 status;
 701         unsigned int handled = 0;
 702
 703         VPRINTK("ENTER\n");
 704
 705         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 706             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 707
 708                 /* step two - DMA from DIMM to host */
 709                 if (doing_hdma) {
 710                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
 711                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 712                         /* get drive status; clear intr; complete txn */
 713                         ata_qc_complete(qc, ata_wait_idle(ap));
 714                         pdc20621_pop_hdma(qc);
 715                 }
 716
 717                 /* step one - exec ATA command */
 718                 else {
 719                         u8 seq = (u8) (port_no + 1 + 4);
 720                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
 721                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 722
 723                         /* submit hdma pkt */
 724                         pdc20621_dump_hdma(qc);
 725                         pdc20621_push_hdma(qc, seq,
 726                                            port_ofs + PDC_DIMM_HOST_PKT);
 727                 }
 728                 handled = 1;
 729
 730         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 731
 732                 /* step one - DMA from host to DIMM */
 733                 if (doing_hdma) {
 734                         u8 seq = (u8) (port_no + 1);
 735                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
 736                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 737
 738                         /* submit ata pkt */
 739                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 740                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 741                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 742                                (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 743                         readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 744                 }
 745
 746                 /* step two - execute ATA command */
 747                 else {
 748                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
 749                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 750                         /* get drive status; clear intr; complete txn */
 751                         ata_qc_complete(qc, ata_wait_idle(ap));
 752                         pdc20621_pop_hdma(qc);
 753                 }
 754                 handled = 1;
 755
 756         /* command completion, but no data xfer */
 757         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 758
 759                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 760                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 761                 ata_qc_complete(qc, status);
 762                 handled = 1;
 763
 764         } else {
 765                 ap->stats.idle_irq++;
 766         }
 767
 768         return handled;
 769 }
 770
 771 static void pdc20621_irq_clear(struct ata_port *ap)
 772 {
 773         struct ata_host_set *host_set = ap->host_set;
 774         void *mmio = host_set->mmio_base;
 775
 776         mmio += PDC_CHIP0_OFS;
 777
 778         readl(mmio + PDC_20621_SEQMASK);
 779 }
 780
 781 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
 782 {
 783         struct ata_host_set *host_set = dev_instance;
 784         struct ata_port *ap;
 785         u32 mask = 0;
 786         unsigned int i, tmp, port_no;
 787         unsigned int handled = 0;
 788         void *mmio_base;
 789
 790         VPRINTK("ENTER\n");
 791
 792         if (!host_set || !host_set->mmio_base) {
 793                 VPRINTK("QUICK EXIT\n");
 794                 return IRQ_NONE;
 795         }
 796
 797         mmio_base = host_set->mmio_base;
 798
 799         /* reading should also clear interrupts */
 800         mmio_base += PDC_CHIP0_OFS;
 801         mask = readl(mmio_base + PDC_20621_SEQMASK);
 802         VPRINTK("mask == 0x%x\n", mask);
 803
 804         if (mask == 0xffffffff) {
 805                 VPRINTK("QUICK EXIT 2\n");
 806                 return IRQ_NONE;
 807         }
 808         mask &= 0xffff;         /* only 16 tags possible */
 809         if (!mask) {
 810                 VPRINTK("QUICK EXIT 3\n");
 811                 return IRQ_NONE;
 812         }
 813
 814         spin_lock(&host_set->lock);
 815
 816         for (i = 1; i < 9; i++) {
 817                 port_no = i - 1;
 818                 if (port_no > 3)
 819                         port_no -= 4;
 820                 if (port_no >= host_set->n_ports)
 821                         ap = NULL;
 822                 else
 823                         ap = host_set->ports[port_no];
 824                 tmp = mask & (1 << i);
 825                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 826                 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
 827                         struct ata_queued_cmd *qc;
 828
 829                         qc = ata_qc_from_tag(ap, ap->active_tag);
 830                         if (qc && (!(qc->tf.ctl & ATA_NIEN)))
 831                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 832                                                               mmio_base);
 833                 }
 834         }
 835
 836         spin_unlock(&host_set->lock);
 837
 838         VPRINTK("mask == 0x%x\n", mask);
 839
 840         VPRINTK("EXIT\n");
 841
 842         return IRQ_RETVAL(handled);
 843 }
 844
 845 static void pdc_eng_timeout(struct ata_port *ap)
 846 {
 847         u8 drv_stat;
 848         struct ata_queued_cmd *qc;
 849
 850         DPRINTK("ENTER\n");
 851
 852         qc = ata_qc_from_tag(ap, ap->active_tag);
 853         if (!qc) {
 854                 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
 855                        ap->id);
 856                 goto out;
 857         }
 858
 859         /* hack alert!  We cannot use the supplied completion
 860          * function from inside the ->eh_strategy_handler() thread.
 861          * libata is the only user of ->eh_strategy_handler() in
 862          * any kernel, so the default scsi_done() assumes it is
 863          * not being called from the SCSI EH.
 864          */
 865         qc->scsidone = scsi_finish_command;
 866
 867         switch (qc->tf.protocol) {
 868         case ATA_PROT_DMA:
 869         case ATA_PROT_NODATA:
 870                 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
 871                 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
 872                 break;
 873
 874         default:
 875                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 876
 877                 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
 878                        ap->id, qc->tf.command, drv_stat);
 879
 880                 ata_qc_complete(qc, drv_stat);
 881                 break;
 882         }
 883
 884 out:
 885         DPRINTK("EXIT\n");
 886 }
 887
 888 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
 889 {
 890         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 891                  tf->protocol == ATA_PROT_NODATA);
 892         ata_tf_load(ap, tf);
 893 }
 894
 895
 896 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
 897 {
 898         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 899                  tf->protocol == ATA_PROT_NODATA);
 900         ata_exec_command(ap, tf);
 901 }
 902
 903
 904 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 905 {
 906         port->cmd_addr          = base;
 907         port->data_addr         = base;
 908         port->feature_addr      =
 909         port->error_addr        = base + 0x4;
 910         port->nsect_addr        = base + 0x8;
 911         port->lbal_addr         = base + 0xc;
 912         port->lbam_addr         = base + 0x10;
 913         port->lbah_addr         = base + 0x14;
 914         port->device_addr       = base + 0x18;
 915         port->command_addr      =
 916         port->status_addr       = base + 0x1c;
 917         port->altstatus_addr    =
 918         port->ctl_addr          = base + 0x38;
 919 }
 920
 921
 922 #ifdef ATA_VERBOSE_DEBUG
 923 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
 924                                    u32 offset, u32 size)
 925 {
 926         u32 window_size;
 927         u16 idx;
 928         u8 page_mask;
 929         long dist;
 930         void *mmio = pe->mmio_base;
 931         struct pdc_host_priv *hpriv = pe->private_data;
 932         void *dimm_mmio = hpriv->dimm_mmio;
 933
 934         /* hard-code chip #0 */
 935         mmio += PDC_CHIP0_OFS;
 936
 937         page_mask = 0x00;
 938         window_size = 0x2000 * 4; /* 32K byte uchar size */
 939         idx = (u16) (offset / window_size);
 940
 941         writel(0x01, mmio + PDC_GENERAL_CTLR);
 942         readl(mmio + PDC_GENERAL_CTLR);
 943         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 944         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 945
 946         offset -= (idx * window_size);
 947         idx++;
 948         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 949                 (long) (window_size - offset);
 950         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 951                       dist);
 952
 953         psource += dist;
 954         size -= dist;
 955         for (; (long) size >= (long) window_size ;) {
 956                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 957                 readl(mmio + PDC_GENERAL_CTLR);
 958                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 959                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 960                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 961                               window_size / 4);
 962                 psource += window_size;
 963                 size -= window_size;
 964                 idx ++;
 965         }
 966
 967         if (size) {
 968                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 969                 readl(mmio + PDC_GENERAL_CTLR);
 970                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 971                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 972                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 973                               size / 4);
 974         }
 975 }
 976 #endif
 977
 978
 979 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
 980                                  u32 offset, u32 size)
 981 {
 982         u32 window_size;
 983         u16 idx;
 984         u8 page_mask;
 985         long dist;
 986         void *mmio = pe->mmio_base;
 987         struct pdc_host_priv *hpriv = pe->private_data;
 988         void *dimm_mmio = hpriv->dimm_mmio;
 989
 990         /* hard-code chip #0 */
 991         mmio += PDC_CHIP0_OFS;
 992
 993         page_mask = 0x00;
 994         window_size = 0x2000 * 4;       /* 32K byte uchar size */
 995         idx = (u16) (offset / window_size);
 996
 997         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 998         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 999         offset -= (idx * window_size);
1000         idx++;
1001         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1002                 (long) (window_size - offset);
1003         memcpy_toio((char *) (dimm_mmio + offset / 4), (char *) psource, dist);
1004         writel(0x01, mmio + PDC_GENERAL_CTLR);
1005         readl(mmio + PDC_GENERAL_CTLR);
1006
1007         psource += dist;
1008         size -= dist;
1009         for (; (long) size >= (long) window_size ;) {
1010                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1011                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1012                 memcpy_toio((char *) (dimm_mmio), (char *) psource,
1013                             window_size / 4);
1014                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1015                 readl(mmio + PDC_GENERAL_CTLR);
1016                 psource += window_size;
1017                 size -= window_size;
1018                 idx ++;
1019         }
1020
1021         if (size) {
1022                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1023                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1024                 memcpy_toio((char *) (dimm_mmio), (char *) psource, size / 4);
1025                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1026                 readl(mmio + PDC_GENERAL_CTLR);
1027         }
1028 }
1029
1030
1031 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1032                                       u32 subaddr, u32 *pdata)
1033 {
1034         void *mmio = pe->mmio_base;
1035         u32 i2creg  = 0;
1036         u32 status;
1037         u32 count =0;
1038
1039         /* hard-code chip #0 */
1040         mmio += PDC_CHIP0_OFS;
1041
1042         i2creg |= device << 24;
1043         i2creg |= subaddr << 16;
1044
1045         /* Set the device and subaddress */
1046         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1047         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1048
1049         /* Write Control to perform read operation, mask int */
1050         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1051                mmio + PDC_I2C_CONTROL_OFFSET);
1052
1053         for (count = 0; count <= 1000; count ++) {
1054                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1055                 if (status & PDC_I2C_COMPLETE) {
1056                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1057                         break;
1058                 } else if (count == 1000)
1059                         return 0;
1060         }
1061
1062         *pdata = (status >> 8) & 0x000000ff;
1063         return 1;
1064 }
1065
1066
1067 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1068 {
1069         u32 data=0 ;
1070         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1071                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1072                 if (data == 100)
1073                         return 100;
1074         } else
1075                 return 0;
1076
1077         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1078                 if(data <= 0x75)
1079                         return 133;
1080         } else
1081                 return 0;
1082
1083         return 0;
1084 }
1085
1086
1087 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1088 {
1089         u32 spd0[50];
1090         u32 data = 0;
1091         int size, i;
1092         u8 bdimmsize;
1093         void *mmio = pe->mmio_base;
1094         static const struct {
1095                 unsigned int reg;
1096                 unsigned int ofs;
1097         } pdc_i2c_read_data [] = {
1098                 { PDC_DIMM_SPD_TYPE, 11 },
1099                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1100                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1101                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1102                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1103                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1104                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1105                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1106                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1107                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1108                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1109                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1110         };
1111
1112         /* hard-code chip #0 */
1113         mmio += PDC_CHIP0_OFS;
1114
1115         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1116                 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1117                                   pdc_i2c_read_data[i].reg,
1118                                   &spd0[pdc_i2c_read_data[i].ofs]);
1119
1120         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1121         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1122                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1123         data |= (((((spd0[29] > spd0[28])
1124                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1125         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1126
1127         if (spd0[18] & 0x08)
1128                 data |= ((0x03) << 14);
1129         else if (spd0[18] & 0x04)
1130                 data |= ((0x02) << 14);
1131         else if (spd0[18] & 0x01)
1132                 data |= ((0x01) << 14);
1133         else
1134                 data |= (0 << 14);
1135
1136         /*
1137            Calculate the size of bDIMMSize (power of 2) and
1138            merge the DIMM size by program start/end address.
1139         */
1140
1141         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1142         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1143         data |= (((size / 16) - 1) << 16);
1144         data |= (0 << 23);
1145         data |= 8;
1146         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1147         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1148         return size;
1149 }
1150
1151
1152 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1153 {
1154         u32 data, spd0;
1155         int error, i;
1156         void *mmio = pe->mmio_base;
1157
1158         /* hard-code chip #0 */
1159         mmio += PDC_CHIP0_OFS;
1160
1161         /*
1162           Set To Default : DIMM Module Global Control Register (0x022259F1)
1163           DIMM Arbitration Disable (bit 20)
1164           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1165           Refresh Enable (bit 17)
1166         */
1167
1168         data = 0x022259F1;
1169         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1170         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1171
1172         /* Turn on for ECC */
1173         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1174                           PDC_DIMM_SPD_TYPE, &spd0);
1175         if (spd0 == 0x02) {
1176                 data |= (0x01 << 16);
1177                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1178                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1179                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1180         }
1181
1182         /* DIMM Initialization Select/Enable (bit 18/19) */
1183         data &= (~(1<<18));
1184         data |= (1<<19);
1185         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1186
1187         error = 1;
1188         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1189                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1190                 if (!(data & (1<<19))) {
1191                         error = 0;
1192                         break;
1193                 }
1194                 msleep(i*100);
1195         }
1196         return error;
1197 }
1198
1199
1200 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1201 {
1202         int speed, size, length;
1203         u32 addr,spd0,pci_status;
1204         u32 tmp=0;
1205         u32 time_period=0;
1206         u32 tcount=0;
1207         u32 ticks=0;
1208         u32 clock=0;
1209         u32 fparam=0;
1210         void *mmio = pe->mmio_base;
1211
1212         /* hard-code chip #0 */
1213         mmio += PDC_CHIP0_OFS;
1214
1215         /* Initialize PLL based upon PCI Bus Frequency */
1216
1217         /* Initialize Time Period Register */
1218         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1219         time_period = readl(mmio + PDC_TIME_PERIOD);
1220         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1221
1222         /* Enable timer */
1223         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1224         readl(mmio + PDC_TIME_CONTROL);
1225
1226         /* Wait 3 seconds */
1227         msleep(3000);
1228
1229         /*
1230            When timer is enabled, counter is decreased every internal
1231            clock cycle.
1232         */
1233
1234         tcount = readl(mmio + PDC_TIME_COUNTER);
1235         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1236
1237         /*
1238            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1239            register should be >= (0xffffffff - 3x10^8).
1240         */
1241         if(tcount >= PCI_X_TCOUNT) {
1242                 ticks = (time_period - tcount);
1243                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1244
1245                 clock = (ticks / 300000);
1246                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1247
1248                 clock = (clock * 33);
1249                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1250
1251                 /* PLL F Param (bit 22:16) */
1252                 fparam = (1400000 / clock) - 2;
1253                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1254
1255                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1256                 pci_status = (0x8a001824 | (fparam << 16));
1257         } else
1258                 pci_status = PCI_PLL_INIT;
1259
1260         /* Initialize PLL. */
1261         VPRINTK("pci_status: 0x%x\n", pci_status);
1262         writel(pci_status, mmio + PDC_CTL_STATUS);
1263         readl(mmio + PDC_CTL_STATUS);
1264
1265         /*
1266            Read SPD of DIMM by I2C interface,
1267            and program the DIMM Module Controller.
1268         */
1269         if (!(speed = pdc20621_detect_dimm(pe))) {
1270                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1271                 return 1;       /* DIMM error */
1272         }
1273         VPRINTK("Local DIMM Speed = %d\n", speed);
1274
1275         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1276         size = pdc20621_prog_dimm0(pe);
1277         VPRINTK("Local DIMM Size = %dMB\n",size);
1278
1279         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1280         if (pdc20621_prog_dimm_global(pe)) {
1281                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1282                 return 1;
1283         }
1284
1285 #ifdef ATA_VERBOSE_DEBUG
1286         {
1287                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1288                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1289                                  '1','.','1','0',
1290                                 '9','8','0','3','1','6','1','2',0,0};
1291                 u8 test_parttern2[40] = {0};
1292
1293                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1294                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1295
1296                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1297                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1298                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1299                        test_parttern2[1], &(test_parttern2[2]));
1300                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1301                                        40);
1302                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1303                        test_parttern2[1], &(test_parttern2[2]));
1304
1305                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1306                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1307                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1308                        test_parttern2[1], &(test_parttern2[2]));
1309         }
1310 #endif
1311
1312         /* ECC initiliazation. */
1313
1314         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1315                           PDC_DIMM_SPD_TYPE, &spd0);
1316         if (spd0 == 0x02) {
1317                 VPRINTK("Start ECC initialization\n");
1318                 addr = 0;
1319                 length = size * 1024 * 1024;
1320                 while (addr < length) {
1321                         pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1322                                              sizeof(u32));
1323                         addr += sizeof(u32);
1324                 }
1325                 VPRINTK("Finish ECC initialization\n");
1326         }
1327         return 0;
1328 }
1329
1330
1331 static void pdc_20621_init(struct ata_probe_ent *pe)
1332 {
1333         u32 tmp;
1334         void *mmio = pe->mmio_base;
1335
1336         /* hard-code chip #0 */
1337         mmio += PDC_CHIP0_OFS;
1338
1339         /*
1340          * Select page 0x40 for our 32k DIMM window
1341          */
1342         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1343         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1344         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1345
1346         /*
1347          * Reset Host DMA
1348          */
1349         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1350         tmp |= PDC_RESET;
1351         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1352         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1353
1354         udelay(10);
1355
1356         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1357         tmp &= ~PDC_RESET;
1358         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1359         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1360 }
1361
1362 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1363 {
1364         static int printed_version;
1365         struct ata_probe_ent *probe_ent = NULL;
1366         unsigned long base;
1367         void *mmio_base, *dimm_mmio = NULL;
1368         struct pdc_host_priv *hpriv = NULL;
1369         unsigned int board_idx = (unsigned int) ent->driver_data;
1370         int pci_dev_busy = 0;
1371         int rc;
1372
1373         if (!printed_version++)
1374                 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1375
1376         /*
1377          * If this driver happens to only be useful on Apple's K2, then
1378          * we should check that here as it has a normal Serverworks ID
1379          */
1380         rc = pci_enable_device(pdev);
1381         if (rc)
1382                 return rc;
1383
1384         rc = pci_request_regions(pdev, DRV_NAME);
1385         if (rc) {
1386                 pci_dev_busy = 1;
1387                 goto err_out;
1388         }
1389
1390         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1391         if (rc)
1392                 goto err_out_regions;
1393         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1394         if (rc)
1395                 goto err_out_regions;
1396
1397         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1398         if (probe_ent == NULL) {
1399                 rc = -ENOMEM;
1400                 goto err_out_regions;
1401         }
1402
1403         memset(probe_ent, 0, sizeof(*probe_ent));
1404         probe_ent->dev = pci_dev_to_dev(pdev);
1405         INIT_LIST_HEAD(&probe_ent->node);
1406
1407         mmio_base = ioremap(pci_resource_start(pdev, 3),
1408                             pci_resource_len(pdev, 3));
1409         if (mmio_base == NULL) {
1410                 rc = -ENOMEM;
1411                 goto err_out_free_ent;
1412         }
1413         base = (unsigned long) mmio_base;
1414
1415         hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1416         if (!hpriv) {
1417                 rc = -ENOMEM;
1418                 goto err_out_iounmap;
1419         }
1420         memset(hpriv, 0, sizeof(*hpriv));
1421
1422         dimm_mmio = ioremap(pci_resource_start(pdev, 4),
1423                             pci_resource_len(pdev, 4));
1424         if (!dimm_mmio) {
1425                 kfree(hpriv);
1426                 rc = -ENOMEM;
1427                 goto err_out_iounmap;
1428         }
1429
1430         hpriv->dimm_mmio = dimm_mmio;
1431
1432         probe_ent->sht          = pdc_port_info[board_idx].sht;
1433         probe_ent->host_flags   = pdc_port_info[board_idx].host_flags;
1434         probe_ent->pio_mask     = pdc_port_info[board_idx].pio_mask;
1435         probe_ent->mwdma_mask   = pdc_port_info[board_idx].mwdma_mask;
1436         probe_ent->udma_mask    = pdc_port_info[board_idx].udma_mask;
1437         probe_ent->port_ops     = pdc_port_info[board_idx].port_ops;
1438
1439         probe_ent->irq = pdev->irq;
1440         probe_ent->irq_flags = SA_SHIRQ;
1441         probe_ent->mmio_base = mmio_base;
1442
1443         probe_ent->private_data = hpriv;
1444         base += PDC_CHIP0_OFS;
1445
1446         probe_ent->n_ports = 4;
1447         pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1448         pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1449         pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1450         pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1451
1452         pci_set_master(pdev);
1453
1454         /* initialize adapter */
1455         /* initialize local dimm */
1456         if (pdc20621_dimm_init(probe_ent)) {
1457                 rc = -ENOMEM;
1458                 goto err_out_iounmap_dimm;
1459         }
1460         pdc_20621_init(probe_ent);
1461
1462         /* FIXME: check ata_device_add return value */
1463         ata_device_add(probe_ent);
1464         kfree(probe_ent);
1465
1466         return 0;
1467
1468 err_out_iounmap_dimm:           /* only get to this label if 20621 */
1469         kfree(hpriv);
1470         iounmap(dimm_mmio);
1471 err_out_iounmap:
1472         iounmap(mmio_base);
1473 err_out_free_ent:
1474         kfree(probe_ent);
1475 err_out_regions:
1476         pci_release_regions(pdev);
1477 err_out:
1478         if (!pci_dev_busy)
1479                 pci_disable_device(pdev);
1480         return rc;
1481 }
1482
1483
1484 static int __init pdc_sata_init(void)
1485 {
1486         return pci_module_init(&pdc_sata_pci_driver);
1487 }
1488
1489
1490 static void __exit pdc_sata_exit(void)
1491 {
1492         pci_unregister_driver(&pdc_sata_pci_driver);
1493 }
1494
1495
1496 MODULE_AUTHOR("Jeff Garzik");
1497 MODULE_DESCRIPTION("Promise SATA low-level driver");
1498 MODULE_LICENSE("GPL");
1499 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1500 MODULE_VERSION(DRV_VERSION);
1501
1502 module_init(pdc_sata_init);
1503 module_exit(pdc_sata_exit);