2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
37 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
44 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
56 #define QLA2XXX_DRIVER_NAME "qla2xxx"
57 #define QLA2XXX_APIDEV "ql2xapidev"
58 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
61 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
62 * but that's fine as we don't look at the last 24 ones for
65 #define MAILBOX_REGISTER_COUNT_2100 8
66 #define MAILBOX_REGISTER_COUNT_2200 24
67 #define MAILBOX_REGISTER_COUNT 32
69 #define QLA2200A_RISC_ROM_VER 4
73 #include "qla_settings.h"
75 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
78 * Data bit definitions
96 #define BIT_16 0x10000
97 #define BIT_17 0x20000
98 #define BIT_18 0x40000
99 #define BIT_19 0x80000
100 #define BIT_20 0x100000
101 #define BIT_21 0x200000
102 #define BIT_22 0x400000
103 #define BIT_23 0x800000
104 #define BIT_24 0x1000000
105 #define BIT_25 0x2000000
106 #define BIT_26 0x4000000
107 #define BIT_27 0x8000000
108 #define BIT_28 0x10000000
109 #define BIT_29 0x20000000
110 #define BIT_30 0x40000000
111 #define BIT_31 0x80000000
113 #define LSB(x) ((uint8_t)(x))
114 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
116 #define LSW(x) ((uint16_t)(x))
117 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
119 #define LSD(x) ((uint32_t)((uint64_t)(x)))
120 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
122 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
128 #define RD_REG_BYTE(addr) readb(addr)
129 #define RD_REG_WORD(addr) readw(addr)
130 #define RD_REG_DWORD(addr) readl(addr)
131 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
132 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
133 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
134 #define WRT_REG_BYTE(addr, data) writeb(data, addr)
135 #define WRT_REG_WORD(addr, data) writew(data, addr)
136 #define WRT_REG_DWORD(addr, data) writel(data, addr)
139 * ISP83XX specific remote register addresses
141 #define QLA83XX_LED_PORT0 0x00201320
142 #define QLA83XX_LED_PORT1 0x00201328
143 #define QLA83XX_IDC_DEV_STATE 0x22102384
144 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
145 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
146 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
147 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
148 #define QLA83XX_IDC_CONTROL 0x22102390
149 #define QLA83XX_IDC_AUDIT 0x22102394
150 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
151 #define QLA83XX_DRIVER_LOCKID 0x22102104
152 #define QLA83XX_DRIVER_LOCK 0x8111c028
153 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
154 #define QLA83XX_FLASH_LOCKID 0x22102100
155 #define QLA83XX_FLASH_LOCK 0x8111c010
156 #define QLA83XX_FLASH_UNLOCK 0x8111c014
157 #define QLA83XX_DEV_PARTINFO1 0x221023e0
158 #define QLA83XX_DEV_PARTINFO2 0x221023e4
159 #define QLA83XX_FW_HEARTBEAT 0x221020b0
160 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
161 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
163 /* 83XX: Macros defining 8200 AEN Reason codes */
164 #define IDC_DEVICE_STATE_CHANGE BIT_0
165 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
166 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
167 #define IDC_HEARTBEAT_FAILURE BIT_3
169 /* 83XX: Macros defining 8200 AEN Error-levels */
170 #define ERR_LEVEL_NON_FATAL 0x1
171 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
172 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
174 /* 83XX: Macros for IDC Version */
175 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
176 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
178 /* 83XX: Macros for scheduling dpc tasks */
179 #define QLA83XX_NIC_CORE_RESET 0x1
180 #define QLA83XX_IDC_STATE_HANDLER 0x2
181 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
183 /* 83XX: Macros for defining IDC-Control bits */
184 #define QLA83XX_IDC_RESET_DISABLED BIT_0
185 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
187 /* 83XX: Macros for different timeouts */
188 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
189 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
190 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
192 /* 83XX: Macros for defining class in DEV-Partition Info register */
193 #define QLA83XX_CLASS_TYPE_NONE 0x0
194 #define QLA83XX_CLASS_TYPE_NIC 0x1
195 #define QLA83XX_CLASS_TYPE_FCOE 0x2
196 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
198 /* 83XX: Macros for IDC Lock-Recovery stages */
199 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
202 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
204 /* 83XX: Macros for IDC Audit type */
205 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
206 * dev-state change to NEED-RESET
209 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
210 * reset-recovery completion is
213 /* ISP2031: Values for laser on/off */
214 #define PORT_0_2031 0x00201340
215 #define PORT_1_2031 0x00201350
216 #define LASER_ON_2031 0x01800100
217 #define LASER_OFF_2031 0x01800180
220 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
223 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
224 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
227 * Fibre Channel device definitions.
229 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
230 #define MAX_FIBRE_DEVICES_2100 512
231 #define MAX_FIBRE_DEVICES_2400 2048
232 #define MAX_FIBRE_DEVICES_LOOP 128
233 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
234 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
235 #define MAX_FIBRE_LUNS 0xFFFF
236 #define MAX_HOST_COUNT 16
239 * Host adapter default definitions.
241 #define MAX_BUSES 1 /* We only have one bus today */
243 #define MAX_LUNS MAX_FIBRE_LUNS
244 #define MAX_CMDS_PER_LUN 255
247 * Fibre Channel device definitions.
249 #define SNS_LAST_LOOP_ID_2100 0xfe
250 #define SNS_LAST_LOOP_ID_2300 0x7ff
252 #define LAST_LOCAL_LOOP_ID 0x7d
253 #define SNS_FL_PORT 0x7e
254 #define FABRIC_CONTROLLER 0x7f
255 #define SIMPLE_NAME_SERVER 0x80
256 #define SNS_FIRST_LOOP_ID 0x81
257 #define MANAGEMENT_SERVER 0xfe
258 #define BROADCAST 0xff
261 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
262 * valid range of an N-PORT id is 0 through 0x7ef.
264 #define NPH_LAST_HANDLE 0x7ee
265 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
266 #define NPH_SNS 0x7fc /* FFFFFC */
267 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
268 #define NPH_F_PORT 0x7fe /* FFFFFE */
269 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
271 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
273 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
276 struct name_list_extended {
277 struct get_name_list_extended *l;
279 struct list_head fcports;
284 * Timeout timer counts in seconds
286 #define PORT_RETRY_TIME 1
287 #define LOOP_DOWN_TIMEOUT 60
288 #define LOOP_DOWN_TIME 255 /* 240 */
289 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
291 #define DEFAULT_OUTSTANDING_COMMANDS 4096
292 #define MIN_OUTSTANDING_COMMANDS 128
294 /* ISP request and response entry counts (37-65535) */
295 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
296 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
297 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
298 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
299 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
300 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
301 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
302 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
303 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
304 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
305 #define FW_DEF_EXCHANGES_CNT 2048
306 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
307 #define REDUCE_EXCHANGES_CNT (8 * 1024)
316 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
317 uint32_t request_sense_length;
318 uint32_t fw_sense_length;
319 uint8_t *request_sense_ptr;
324 * SRB flag definitions
326 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
327 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
328 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
329 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
330 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
331 #define SRB_WAKEUP_ON_COMP BIT_6
332 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
334 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
335 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
338 * 24 bit port ID type definition.
348 #elif defined(__LITTLE_ENDIAN)
353 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
358 #define INVALID_PORT_ID 0xFFFFFF
360 static inline le_id_t be_id_to_le(be_id_t id)
364 res.domain = id.domain;
366 res.al_pa = id.al_pa;
371 static inline be_id_t le_id_to_be(le_id_t id)
375 res.domain = id.domain;
377 res.al_pa = id.al_pa;
382 static inline port_id_t be_to_port_id(be_id_t id)
386 res.b.domain = id.domain;
387 res.b.area = id.area;
388 res.b.al_pa = id.al_pa;
394 static inline be_id_t port_id_to_be_id(port_id_t port_id)
398 res.domain = port_id.b.domain;
399 res.area = port_id.b.area;
400 res.al_pa = port_id.b.al_pa;
405 struct els_logo_payload {
410 uint8_t wwpn[WWN_SIZE];
413 struct els_plogi_payload {
426 u32 req_allocated_size;
427 u32 rsp_allocated_size;
440 #define SRB_LOGIN_RETRIED BIT_0
441 #define SRB_LOGIN_COND_PLOGI BIT_1
442 #define SRB_LOGIN_SKIP_PRLI BIT_2
443 #define SRB_LOGIN_NVME_PRLI BIT_3
444 #define SRB_LOGIN_PRLI_ONLY BIT_4
449 #define ELS_DCMD_TIMEOUT 20
450 #define ELS_DCMD_LOGO 0x5
453 struct completion comp;
454 struct els_logo_payload *els_logo_pyld;
455 dma_addr_t els_logo_pyld_dma;
458 #define ELS_DCMD_PLOGI 0x3
461 struct completion comp;
462 struct els_plogi_payload *els_plogi_pyld;
463 struct els_plogi_payload *els_resp_pyld;
466 dma_addr_t els_plogi_pyld_dma;
467 dma_addr_t els_resp_pyld_dma;
468 uint32_t fw_status[3];
474 * Values for flags field below are as
475 * defined in tsk_mgmt_entry struct
476 * for control_flags field in qla_fw.h.
481 struct completion comp;
485 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
486 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
487 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
488 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
489 #define FXDISC_TIMEOUT 20
495 dma_addr_t req_dma_handle;
496 dma_addr_t rsp_dma_handle;
498 __le32 adapter_id_hi;
499 __le16 req_func_type;
501 __le32 req_data_extra;
505 struct completion fxiocb_comp;
513 struct completion comp;
516 #define MAX_IOCB_MB_REG 28
517 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
519 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
520 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
522 dma_addr_t out_dma, in_dma;
523 struct completion comp;
527 struct imm_ntfy_from_isp *ntfy;
531 uint16_t rsp_pyld_len;
535 /* These are only used with ls4 requests */
540 enum nvmefc_fcp_datadir dir;
542 uint32_t timeout_sec;
543 struct list_head entry;
551 struct timer_list timer;
552 void (*timeout)(void *);
555 /* Values for srb_ctx type */
556 #define SRB_LOGIN_CMD 1
557 #define SRB_LOGOUT_CMD 2
558 #define SRB_ELS_CMD_RPT 3
559 #define SRB_ELS_CMD_HST 4
561 #define SRB_ADISC_CMD 6
563 #define SRB_SCSI_CMD 8
564 #define SRB_BIDI_CMD 9
565 #define SRB_FXIOCB_DCMD 10
566 #define SRB_FXIOCB_BCMD 11
567 #define SRB_ABT_CMD 12
568 #define SRB_ELS_DCMD 13
569 #define SRB_MB_IOCB 14
570 #define SRB_CT_PTHRU_CMD 15
571 #define SRB_NACK_PLOGI 16
572 #define SRB_NACK_PRLI 17
573 #define SRB_NACK_LOGO 18
574 #define SRB_NVME_CMD 19
575 #define SRB_NVME_LS 20
576 #define SRB_PRLI_CMD 21
577 #define SRB_CTRL_VP 22
578 #define SRB_PRLO_CMD 23
583 TYPE_TGT_TMCMD, /* task management */
588 * Do not move cmd_type field, it needs to
589 * line up with qla_tgt_cmd->cmd_type
594 struct kref cmd_kref; /* need to migrate ref_count over to this */
596 wait_queue_head_t nvme_ls_waitq;
597 struct fc_port *fcport;
598 struct scsi_qla_host *vha;
599 unsigned int start_timer:1;
605 struct qla_qpair *qpair;
606 struct list_head elem;
607 u32 gen1; /* scratch */
608 u32 gen2; /* scratch */
611 struct completion *comp;
613 struct srb_iocb iocb_cmd;
614 struct bsg_job *bsg_job;
617 void (*done)(void *, int);
618 void (*free)(void *);
619 void (*put_fn)(struct kref *kref);
622 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
623 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
624 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
626 #define GET_CMD_SENSE_LEN(sp) \
627 (sp->u.scmd.request_sense_length)
628 #define SET_CMD_SENSE_LEN(sp, len) \
629 (sp->u.scmd.request_sense_length = len)
630 #define GET_CMD_SENSE_PTR(sp) \
631 (sp->u.scmd.request_sense_ptr)
632 #define SET_CMD_SENSE_PTR(sp, ptr) \
633 (sp->u.scmd.request_sense_ptr = ptr)
634 #define GET_FW_SENSE_LEN(sp) \
635 (sp->u.scmd.fw_sense_length)
636 #define SET_FW_SENSE_LEN(sp, len) \
637 (sp->u.scmd.fw_sense_length = len)
645 uint32_t transfer_size;
646 uint32_t iteration_count;
650 * ISP I/O Register Set structure definitions.
652 struct device_reg_2xxx {
653 uint16_t flash_address; /* Flash BIOS address */
654 uint16_t flash_data; /* Flash BIOS data */
655 uint16_t unused_1[1]; /* Gap */
656 uint16_t ctrl_status; /* Control/Status */
657 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
658 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
659 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
661 uint16_t ictrl; /* Interrupt control */
662 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
663 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
665 uint16_t istatus; /* Interrupt status */
666 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
668 uint16_t semaphore; /* Semaphore */
669 uint16_t nvram; /* NVRAM register. */
670 #define NVR_DESELECT 0
671 #define NVR_BUSY BIT_15
672 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
673 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
674 #define NVR_DATA_IN BIT_3
675 #define NVR_DATA_OUT BIT_2
676 #define NVR_SELECT BIT_1
677 #define NVR_CLOCK BIT_0
679 #define NVR_WAIT_CNT 20000
691 uint16_t unused_2[59]; /* Gap */
692 } __attribute__((packed)) isp2100;
695 uint16_t req_q_in; /* In-Pointer */
696 uint16_t req_q_out; /* Out-Pointer */
698 uint16_t rsp_q_in; /* In-Pointer */
699 uint16_t rsp_q_out; /* Out-Pointer */
701 /* RISC to Host Status */
702 uint32_t host_status;
703 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
704 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
706 /* Host to Host Semaphore */
707 uint16_t host_semaphore;
708 uint16_t unused_3[17]; /* Gap */
742 uint16_t unused_4[10]; /* Gap */
743 } __attribute__((packed)) isp2300;
746 uint16_t fpm_diag_config;
747 uint16_t unused_5[0x4]; /* Gap */
749 uint16_t unused_5_1; /* Gap */
750 uint16_t pcr; /* Processor Control Register. */
751 uint16_t unused_6[0x5]; /* Gap */
752 uint16_t mctr; /* Memory Configuration and Timing. */
753 uint16_t unused_7[0x3]; /* Gap */
754 uint16_t fb_cmd_2100; /* Unused on 23XX */
755 uint16_t unused_8[0x3]; /* Gap */
756 uint16_t hccr; /* Host command & control register. */
757 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
758 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
760 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
761 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
762 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
763 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
764 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
765 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
766 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
767 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
769 uint16_t unused_9[5]; /* Gap */
770 uint16_t gpiod; /* GPIO Data register. */
771 uint16_t gpioe; /* GPIO Enable register. */
772 #define GPIO_LED_MASK 0x00C0
773 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
774 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
775 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
776 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
777 #define GPIO_LED_ALL_OFF 0x0000
778 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
779 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
783 uint16_t unused_10[8]; /* Gap */
799 uint16_t mailbox23; /* Also probe reg. */
800 } __attribute__((packed)) isp2200;
804 struct device_reg_25xxmq {
814 struct device_reg_fx00 {
815 uint32_t mailbox0; /* 00 */
816 uint32_t mailbox1; /* 04 */
817 uint32_t mailbox2; /* 08 */
818 uint32_t mailbox3; /* 0C */
819 uint32_t mailbox4; /* 10 */
820 uint32_t mailbox5; /* 14 */
821 uint32_t mailbox6; /* 18 */
822 uint32_t mailbox7; /* 1C */
823 uint32_t mailbox8; /* 20 */
824 uint32_t mailbox9; /* 24 */
825 uint32_t mailbox10; /* 28 */
847 uint32_t aenmailbox0;
848 uint32_t aenmailbox1;
849 uint32_t aenmailbox2;
850 uint32_t aenmailbox3;
851 uint32_t aenmailbox4;
852 uint32_t aenmailbox5;
853 uint32_t aenmailbox6;
854 uint32_t aenmailbox7;
856 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
857 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
858 /* Response Queue. */
859 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
860 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
861 /* Init values shadowed on FW Up Event */
862 uint32_t initval0; /* B0 */
863 uint32_t initval1; /* B4 */
864 uint32_t initval2; /* B8 */
865 uint32_t initval3; /* BC */
866 uint32_t initval4; /* C0 */
867 uint32_t initval5; /* C4 */
868 uint32_t initval6; /* C8 */
869 uint32_t initval7; /* CC */
870 uint32_t fwheartbeat; /* D0 */
871 uint32_t pseudoaen; /* D4 */
877 struct device_reg_2xxx isp;
878 struct device_reg_24xx isp24;
879 struct device_reg_25xxmq isp25mq;
880 struct device_reg_82xx isp82;
881 struct device_reg_fx00 ispfx00;
882 } __iomem device_reg_t;
884 #define ISP_REQ_Q_IN(ha, reg) \
885 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
886 &(reg)->u.isp2100.mailbox4 : \
887 &(reg)->u.isp2300.req_q_in)
888 #define ISP_REQ_Q_OUT(ha, reg) \
889 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
890 &(reg)->u.isp2100.mailbox4 : \
891 &(reg)->u.isp2300.req_q_out)
892 #define ISP_RSP_Q_IN(ha, reg) \
893 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
894 &(reg)->u.isp2100.mailbox5 : \
895 &(reg)->u.isp2300.rsp_q_in)
896 #define ISP_RSP_Q_OUT(ha, reg) \
897 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
898 &(reg)->u.isp2100.mailbox5 : \
899 &(reg)->u.isp2300.rsp_q_out)
901 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
902 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
904 #define MAILBOX_REG(ha, reg, num) \
905 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
907 &(reg)->u.isp2100.mailbox0 + (num) : \
908 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
909 &(reg)->u.isp2300.mailbox0 + (num))
910 #define RD_MAILBOX_REG(ha, reg, num) \
911 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
912 #define WRT_MAILBOX_REG(ha, reg, num, data) \
913 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
915 #define FB_CMD_REG(ha, reg) \
916 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
917 &(reg)->fb_cmd_2100 : \
918 &(reg)->u.isp2300.fb_cmd)
919 #define RD_FB_CMD_REG(ha, reg) \
920 RD_REG_WORD(FB_CMD_REG(ha, reg))
921 #define WRT_FB_CMD_REG(ha, reg, data) \
922 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
925 uint32_t out_mb; /* outbound from driver */
926 uint32_t in_mb; /* Incoming from RISC */
927 uint16_t mb[MAILBOX_REGISTER_COUNT];
932 #define MBX_DMA_IN BIT_0
933 #define MBX_DMA_OUT BIT_1
934 #define IOCTL_CMD BIT_2
938 uint32_t out_mb; /* outbound from driver */
939 uint32_t in_mb; /* Incoming from RISC */
940 uint32_t mb[MAILBOX_REGISTER_COUNT];
945 #define MBX_DMA_IN BIT_0
946 #define MBX_DMA_OUT BIT_1
947 #define IOCTL_CMD BIT_2
951 #define MBX_TOV_SECONDS 30
954 * ISP product identification definitions in mailboxes after reset.
956 #define PROD_ID_1 0x4953
957 #define PROD_ID_2 0x0000
958 #define PROD_ID_2a 0x5020
959 #define PROD_ID_3 0x2020
962 * ISP mailbox Self-Test status codes
964 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
965 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
966 #define MBS_BUSY 4 /* Busy. */
969 * ISP mailbox command complete status codes
971 #define MBS_COMMAND_COMPLETE 0x4000
972 #define MBS_INVALID_COMMAND 0x4001
973 #define MBS_HOST_INTERFACE_ERROR 0x4002
974 #define MBS_TEST_FAILED 0x4003
975 #define MBS_COMMAND_ERROR 0x4005
976 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
977 #define MBS_PORT_ID_USED 0x4007
978 #define MBS_LOOP_ID_USED 0x4008
979 #define MBS_ALL_IDS_IN_USE 0x4009
980 #define MBS_NOT_LOGGED_IN 0x400A
981 #define MBS_LINK_DOWN_ERROR 0x400B
982 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
985 * ISP mailbox asynchronous event status codes
987 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
988 #define MBA_RESET 0x8001 /* Reset Detected. */
989 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
990 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
991 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
992 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
993 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
995 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
996 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
997 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
998 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
999 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
1000 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
1001 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
1002 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
1003 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
1004 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
1005 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
1006 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
1007 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
1008 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
1009 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
1010 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
1012 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
1013 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
1014 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
1015 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
1016 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
1017 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
1018 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
1019 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
1020 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
1021 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
1022 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
1023 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
1024 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
1025 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
1026 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
1027 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
1028 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
1029 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
1030 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
1031 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
1032 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
1033 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
1034 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
1035 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
1037 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
1038 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
1039 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
1040 /* 83XX FCoE specific */
1041 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
1043 /* Interrupt type codes */
1044 #define INTR_ROM_MB_SUCCESS 0x1
1045 #define INTR_ROM_MB_FAILED 0x2
1046 #define INTR_MB_SUCCESS 0x10
1047 #define INTR_MB_FAILED 0x11
1048 #define INTR_ASYNC_EVENT 0x12
1049 #define INTR_RSP_QUE_UPDATE 0x13
1050 #define INTR_RSP_QUE_UPDATE_83XX 0x14
1051 #define INTR_ATIO_QUE_UPDATE 0x1C
1052 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1053 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1055 /* ISP mailbox loopback echo diagnostic error code */
1056 #define MBS_LB_RESET 0x17
1058 * Firmware options 1, 2, 3.
1060 #define FO1_AE_ON_LIPF8 BIT_0
1061 #define FO1_AE_ALL_LIP_RESET BIT_1
1062 #define FO1_CTIO_RETRY BIT_3
1063 #define FO1_DISABLE_LIP_F7_SW BIT_4
1064 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1065 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1066 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1067 #define FO1_SET_EMPHASIS_SWING BIT_8
1068 #define FO1_AE_AUTO_BYPASS BIT_9
1069 #define FO1_ENABLE_PURE_IOCB BIT_10
1070 #define FO1_AE_PLOGI_RJT BIT_11
1071 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1072 #define FO1_AE_QUEUE_FULL BIT_13
1074 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1075 #define FO2_REV_LOOPBACK BIT_1
1077 #define FO3_ENABLE_EMERG_IOCB BIT_0
1078 #define FO3_AE_RND_ERROR BIT_1
1080 /* 24XX additional firmware options */
1081 #define ADD_FO_COUNT 3
1082 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1083 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1085 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1087 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1090 * ISP mailbox commands
1092 #define MBC_LOAD_RAM 1 /* Load RAM. */
1093 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
1094 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1095 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1096 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1097 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1098 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1099 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
1100 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
1101 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1102 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1103 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1104 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1105 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1106 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1107 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1108 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1109 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1110 #define MBC_RESET 0x18 /* Reset. */
1111 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1112 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1113 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1114 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1115 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1116 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1117 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1118 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1119 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1120 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1121 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1122 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1123 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1124 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1125 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1126 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1127 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1128 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1129 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1130 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1131 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1132 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1133 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1134 #define MBC_DATA_RATE 0x5d /* Data Rate */
1135 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1136 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1137 /* Initialization Procedure */
1138 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1139 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1140 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1141 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1142 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1143 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1144 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1145 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1146 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1147 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1148 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1150 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1151 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1152 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1153 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1154 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1155 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1156 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1157 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1158 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1159 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1160 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1163 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1164 * should be defined with MBC_MR_*
1166 #define MBC_MR_DRV_SHUTDOWN 0x6A
1169 * ISP24xx mailbox commands
1171 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1172 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1173 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1174 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1175 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1176 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1177 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1178 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1179 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1180 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1181 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1182 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1183 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1184 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1185 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1186 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1187 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1188 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1189 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1190 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1191 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1192 #define MBC_PORT_RESET 0x120 /* Port Reset */
1193 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1194 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1197 * ISP81xx mailbox commands
1199 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1202 * ISP8044 mailbox commands
1204 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1205 #define HCS_WRITE_SERDES 0x3
1206 #define HCS_READ_SERDES 0x4
1208 /* Firmware return data sizes */
1209 #define FCAL_MAP_SIZE 128
1211 /* Mailbox bit definitions for out_mb and in_mb */
1212 #define MBX_31 BIT_31
1213 #define MBX_30 BIT_30
1214 #define MBX_29 BIT_29
1215 #define MBX_28 BIT_28
1216 #define MBX_27 BIT_27
1217 #define MBX_26 BIT_26
1218 #define MBX_25 BIT_25
1219 #define MBX_24 BIT_24
1220 #define MBX_23 BIT_23
1221 #define MBX_22 BIT_22
1222 #define MBX_21 BIT_21
1223 #define MBX_20 BIT_20
1224 #define MBX_19 BIT_19
1225 #define MBX_18 BIT_18
1226 #define MBX_17 BIT_17
1227 #define MBX_16 BIT_16
1228 #define MBX_15 BIT_15
1229 #define MBX_14 BIT_14
1230 #define MBX_13 BIT_13
1231 #define MBX_12 BIT_12
1232 #define MBX_11 BIT_11
1233 #define MBX_10 BIT_10
1245 #define RNID_TYPE_PORT_LOGIN 0x7
1246 #define RNID_TYPE_SET_VERSION 0x9
1247 #define RNID_TYPE_ASIC_TEMP 0xC
1250 * Firmware state codes from get firmware state mailbox command
1252 #define FSTATE_CONFIG_WAIT 0
1253 #define FSTATE_WAIT_AL_PA 1
1254 #define FSTATE_WAIT_LOGIN 2
1255 #define FSTATE_READY 3
1256 #define FSTATE_LOSS_OF_SYNC 4
1257 #define FSTATE_ERROR 5
1258 #define FSTATE_REINIT 6
1259 #define FSTATE_NON_PART 7
1261 #define FSTATE_CONFIG_CORRECT 0
1262 #define FSTATE_P2P_RCV_LIP 1
1263 #define FSTATE_P2P_CHOOSE_LOOP 2
1264 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1265 #define FSTATE_FATAL_ERROR 4
1266 #define FSTATE_LOOP_BACK_CONN 5
1268 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1269 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1270 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1271 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1272 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1273 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1274 #define QLA27XX_DEFAULT_IMAGE 0
1275 #define QLA27XX_PRIMARY_IMAGE 1
1276 #define QLA27XX_SECONDARY_IMAGE 2
1279 * Port Database structure definition
1280 * Little endian except where noted.
1282 #define PORT_DATABASE_SIZE 128 /* bytes */
1286 uint8_t master_state;
1287 uint8_t slave_state;
1288 uint8_t reserved[2];
1289 uint8_t hard_address;
1292 uint8_t node_name[WWN_SIZE];
1293 uint8_t port_name[WWN_SIZE];
1294 uint16_t execution_throttle;
1295 uint16_t execution_count;
1296 uint8_t reset_count;
1298 uint16_t resource_allocation;
1299 uint16_t current_allocation;
1300 uint16_t queue_head;
1301 uint16_t queue_tail;
1302 uint16_t transmit_execution_list_next;
1303 uint16_t transmit_execution_list_previous;
1304 uint16_t common_features;
1305 uint16_t total_concurrent_sequences;
1306 uint16_t RO_by_information_category;
1309 uint16_t receive_data_size;
1310 uint16_t concurrent_sequences;
1311 uint16_t open_sequences_per_exchange;
1312 uint16_t lun_abort_flags;
1313 uint16_t lun_stop_flags;
1314 uint16_t stop_queue_head;
1315 uint16_t stop_queue_tail;
1316 uint16_t port_retry_timer;
1317 uint16_t next_sequence_id;
1318 uint16_t frame_count;
1319 uint16_t PRLI_payload_length;
1320 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1321 /* Bits 15-0 of word 0 */
1322 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1323 /* Bits 15-0 of word 3 */
1325 uint16_t extended_lun_info_list_pointer;
1326 uint16_t extended_lun_stop_list_pointer;
1330 * Port database slave/master states
1332 #define PD_STATE_DISCOVERY 0
1333 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1334 #define PD_STATE_PORT_LOGIN 2
1335 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1336 #define PD_STATE_PROCESS_LOGIN 4
1337 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1338 #define PD_STATE_PORT_LOGGED_IN 6
1339 #define PD_STATE_PORT_UNAVAILABLE 7
1340 #define PD_STATE_PROCESS_LOGOUT 8
1341 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1342 #define PD_STATE_PORT_LOGOUT 10
1343 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1346 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1347 #define QLA_ZIO_DISABLED 0
1348 #define QLA_ZIO_DEFAULT_TIMER 2
1351 * ISP Initialization Control Block.
1352 * Little endian except where noted.
1354 #define ICB_VERSION 1
1360 * LSB BIT 0 = Enable Hard Loop Id
1361 * LSB BIT 1 = Enable Fairness
1362 * LSB BIT 2 = Enable Full-Duplex
1363 * LSB BIT 3 = Enable Fast Posting
1364 * LSB BIT 4 = Enable Target Mode
1365 * LSB BIT 5 = Disable Initiator Mode
1366 * LSB BIT 6 = Enable ADISC
1367 * LSB BIT 7 = Enable Target Inquiry Data
1369 * MSB BIT 0 = Enable PDBC Notify
1370 * MSB BIT 1 = Non Participating LIP
1371 * MSB BIT 2 = Descending Loop ID Search
1372 * MSB BIT 3 = Acquire Loop ID in LIPA
1373 * MSB BIT 4 = Stop PortQ on Full Status
1374 * MSB BIT 5 = Full Login after LIP
1375 * MSB BIT 6 = Node Name Option
1376 * MSB BIT 7 = Ext IFWCB enable bit
1378 uint8_t firmware_options[2];
1380 uint16_t frame_payload_size;
1381 uint16_t max_iocb_allocation;
1382 uint16_t execution_throttle;
1383 uint8_t retry_count;
1384 uint8_t retry_delay; /* unused */
1385 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1386 uint16_t hard_address;
1387 uint8_t inquiry_data;
1388 uint8_t login_timeout;
1389 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1391 uint16_t request_q_outpointer;
1392 uint16_t response_q_inpointer;
1393 uint16_t request_q_length;
1394 uint16_t response_q_length;
1395 __le64 request_q_address __packed;
1396 __le64 response_q_address __packed;
1398 uint16_t lun_enables;
1399 uint8_t command_resource_count;
1400 uint8_t immediate_notify_resource_count;
1402 uint8_t reserved_2[2];
1405 * LSB BIT 0 = Timer Operation mode bit 0
1406 * LSB BIT 1 = Timer Operation mode bit 1
1407 * LSB BIT 2 = Timer Operation mode bit 2
1408 * LSB BIT 3 = Timer Operation mode bit 3
1409 * LSB BIT 4 = Init Config Mode bit 0
1410 * LSB BIT 5 = Init Config Mode bit 1
1411 * LSB BIT 6 = Init Config Mode bit 2
1412 * LSB BIT 7 = Enable Non part on LIHA failure
1414 * MSB BIT 0 = Enable class 2
1415 * MSB BIT 1 = Enable ACK0
1418 * MSB BIT 4 = FC Tape Enable
1419 * MSB BIT 5 = Enable FC Confirm
1420 * MSB BIT 6 = Enable command queuing in target mode
1421 * MSB BIT 7 = No Logo On Link Down
1423 uint8_t add_firmware_options[2];
1425 uint8_t response_accumulation_timer;
1426 uint8_t interrupt_delay_timer;
1429 * LSB BIT 0 = Enable Read xfr_rdy
1430 * LSB BIT 1 = Soft ID only
1433 * LSB BIT 4 = FCP RSP Payload [0]
1434 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1435 * LSB BIT 6 = Enable Out-of-Order frame handling
1436 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1438 * MSB BIT 0 = Sbus enable - 2300
1442 * MSB BIT 4 = LED mode
1443 * MSB BIT 5 = enable 50 ohm termination
1444 * MSB BIT 6 = Data Rate (2300 only)
1445 * MSB BIT 7 = Data Rate (2300 only)
1447 uint8_t special_options[2];
1449 uint8_t reserved_3[26];
1453 * Get Link Status mailbox command return buffer.
1455 #define GLSO_SEND_RPS BIT_0
1456 #define GLSO_USE_DID BIT_3
1458 struct link_statistics {
1459 uint32_t link_fail_cnt;
1460 uint32_t loss_sync_cnt;
1461 uint32_t loss_sig_cnt;
1462 uint32_t prim_seq_err_cnt;
1463 uint32_t inval_xmit_word_cnt;
1464 uint32_t inval_crc_cnt;
1466 uint32_t link_up_cnt;
1467 uint32_t link_down_loop_init_tmo;
1468 uint32_t link_down_los;
1469 uint32_t link_down_loss_rcv_clk;
1470 uint32_t reserved0[5];
1471 uint32_t port_cfg_chg;
1472 uint32_t reserved1[11];
1473 uint32_t rsp_q_full;
1474 uint32_t atio_q_full;
1476 uint32_t els_proto_err;
1480 uint32_t discarded_frames;
1481 uint32_t dropped_frames;
1484 uint32_t reserved4[4];
1486 uint32_t rcv_exfail;
1488 uint32_t seq_frm_miss;
1491 uint32_t nport_full;
1494 uint32_t fpm_recv_word_cnt_lo;
1495 uint32_t fpm_recv_word_cnt_hi;
1496 uint32_t fpm_disc_word_cnt_lo;
1497 uint32_t fpm_disc_word_cnt_hi;
1498 uint32_t fpm_xmit_word_cnt_lo;
1499 uint32_t fpm_xmit_word_cnt_hi;
1500 uint32_t reserved6[70];
1504 * NVRAM Command values.
1506 #define NV_START_BIT BIT_2
1507 #define NV_WRITE_OP (BIT_26+BIT_24)
1508 #define NV_READ_OP (BIT_26+BIT_25)
1509 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1510 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1511 #define NV_DELAY_COUNT 10
1514 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1521 uint8_t nvram_version;
1525 * NVRAM RISC parameter block
1527 uint8_t parameter_block_version;
1531 * LSB BIT 0 = Enable Hard Loop Id
1532 * LSB BIT 1 = Enable Fairness
1533 * LSB BIT 2 = Enable Full-Duplex
1534 * LSB BIT 3 = Enable Fast Posting
1535 * LSB BIT 4 = Enable Target Mode
1536 * LSB BIT 5 = Disable Initiator Mode
1537 * LSB BIT 6 = Enable ADISC
1538 * LSB BIT 7 = Enable Target Inquiry Data
1540 * MSB BIT 0 = Enable PDBC Notify
1541 * MSB BIT 1 = Non Participating LIP
1542 * MSB BIT 2 = Descending Loop ID Search
1543 * MSB BIT 3 = Acquire Loop ID in LIPA
1544 * MSB BIT 4 = Stop PortQ on Full Status
1545 * MSB BIT 5 = Full Login after LIP
1546 * MSB BIT 6 = Node Name Option
1547 * MSB BIT 7 = Ext IFWCB enable bit
1549 uint8_t firmware_options[2];
1551 uint16_t frame_payload_size;
1552 uint16_t max_iocb_allocation;
1553 uint16_t execution_throttle;
1554 uint8_t retry_count;
1555 uint8_t retry_delay; /* unused */
1556 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1557 uint16_t hard_address;
1558 uint8_t inquiry_data;
1559 uint8_t login_timeout;
1560 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1563 * LSB BIT 0 = Timer Operation mode bit 0
1564 * LSB BIT 1 = Timer Operation mode bit 1
1565 * LSB BIT 2 = Timer Operation mode bit 2
1566 * LSB BIT 3 = Timer Operation mode bit 3
1567 * LSB BIT 4 = Init Config Mode bit 0
1568 * LSB BIT 5 = Init Config Mode bit 1
1569 * LSB BIT 6 = Init Config Mode bit 2
1570 * LSB BIT 7 = Enable Non part on LIHA failure
1572 * MSB BIT 0 = Enable class 2
1573 * MSB BIT 1 = Enable ACK0
1576 * MSB BIT 4 = FC Tape Enable
1577 * MSB BIT 5 = Enable FC Confirm
1578 * MSB BIT 6 = Enable command queuing in target mode
1579 * MSB BIT 7 = No Logo On Link Down
1581 uint8_t add_firmware_options[2];
1583 uint8_t response_accumulation_timer;
1584 uint8_t interrupt_delay_timer;
1587 * LSB BIT 0 = Enable Read xfr_rdy
1588 * LSB BIT 1 = Soft ID only
1591 * LSB BIT 4 = FCP RSP Payload [0]
1592 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1593 * LSB BIT 6 = Enable Out-of-Order frame handling
1594 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1596 * MSB BIT 0 = Sbus enable - 2300
1600 * MSB BIT 4 = LED mode
1601 * MSB BIT 5 = enable 50 ohm termination
1602 * MSB BIT 6 = Data Rate (2300 only)
1603 * MSB BIT 7 = Data Rate (2300 only)
1605 uint8_t special_options[2];
1607 /* Reserved for expanded RISC parameter block */
1608 uint8_t reserved_2[22];
1611 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1612 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1613 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1614 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1615 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1616 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1617 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1618 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1620 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1621 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1622 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1623 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1624 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1625 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1626 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1627 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1629 * LSB BIT 0 = Output Swing 1G bit 0
1630 * LSB BIT 1 = Output Swing 1G bit 1
1631 * LSB BIT 2 = Output Swing 1G bit 2
1632 * LSB BIT 3 = Output Emphasis 1G bit 0
1633 * LSB BIT 4 = Output Emphasis 1G bit 1
1634 * LSB BIT 5 = Output Swing 2G bit 0
1635 * LSB BIT 6 = Output Swing 2G bit 1
1636 * LSB BIT 7 = Output Swing 2G bit 2
1638 * MSB BIT 0 = Output Emphasis 2G bit 0
1639 * MSB BIT 1 = Output Emphasis 2G bit 1
1640 * MSB BIT 2 = Output Enable
1647 uint8_t seriallink_options[4];
1650 * NVRAM host parameter block
1652 * LSB BIT 0 = Enable spinup delay
1653 * LSB BIT 1 = Disable BIOS
1654 * LSB BIT 2 = Enable Memory Map BIOS
1655 * LSB BIT 3 = Enable Selectable Boot
1656 * LSB BIT 4 = Disable RISC code load
1657 * LSB BIT 5 = Set cache line size 1
1658 * LSB BIT 6 = PCI Parity Disable
1659 * LSB BIT 7 = Enable extended logging
1661 * MSB BIT 0 = Enable 64bit addressing
1662 * MSB BIT 1 = Enable lip reset
1663 * MSB BIT 2 = Enable lip full login
1664 * MSB BIT 3 = Enable target reset
1665 * MSB BIT 4 = Enable database storage
1666 * MSB BIT 5 = Enable cache flush read
1667 * MSB BIT 6 = Enable database load
1668 * MSB BIT 7 = Enable alternate WWN
1672 uint8_t boot_node_name[WWN_SIZE];
1673 uint8_t boot_lun_number;
1674 uint8_t reset_delay;
1675 uint8_t port_down_retry_count;
1676 uint8_t boot_id_number;
1677 uint16_t max_luns_per_target;
1678 uint8_t fcode_boot_port_name[WWN_SIZE];
1679 uint8_t alternate_port_name[WWN_SIZE];
1680 uint8_t alternate_node_name[WWN_SIZE];
1683 * BIT 0 = Selective Login
1684 * BIT 1 = Alt-Boot Enable
1686 * BIT 3 = Boot Order List
1688 * BIT 5 = Selective LUN
1692 uint8_t efi_parameters;
1694 uint8_t link_down_timeout;
1696 uint8_t adapter_id[16];
1698 uint8_t alt1_boot_node_name[WWN_SIZE];
1699 uint16_t alt1_boot_lun_number;
1700 uint8_t alt2_boot_node_name[WWN_SIZE];
1701 uint16_t alt2_boot_lun_number;
1702 uint8_t alt3_boot_node_name[WWN_SIZE];
1703 uint16_t alt3_boot_lun_number;
1704 uint8_t alt4_boot_node_name[WWN_SIZE];
1705 uint16_t alt4_boot_lun_number;
1706 uint8_t alt5_boot_node_name[WWN_SIZE];
1707 uint16_t alt5_boot_lun_number;
1708 uint8_t alt6_boot_node_name[WWN_SIZE];
1709 uint16_t alt6_boot_lun_number;
1710 uint8_t alt7_boot_node_name[WWN_SIZE];
1711 uint16_t alt7_boot_lun_number;
1713 uint8_t reserved_3[2];
1715 /* Offset 200-215 : Model Number */
1716 uint8_t model_number[16];
1718 /* OEM related items */
1719 uint8_t oem_specific[16];
1722 * NVRAM Adapter Features offset 232-239
1724 * LSB BIT 0 = External GBIC
1725 * LSB BIT 1 = Risc RAM parity
1726 * LSB BIT 2 = Buffer Plus Module
1727 * LSB BIT 3 = Multi Chip Adapter
1728 * LSB BIT 4 = Internal connector
1742 uint8_t adapter_features[2];
1744 uint8_t reserved_4[16];
1746 /* Subsystem vendor ID for ISP2200 */
1747 uint16_t subsystem_vendor_id_2200;
1749 /* Subsystem device ID for ISP2200 */
1750 uint16_t subsystem_device_id_2200;
1757 * ISP queue - response queue entry definition.
1760 uint8_t entry_type; /* Entry type. */
1761 uint8_t entry_count; /* Entry count. */
1762 uint8_t sys_define; /* System defined. */
1763 uint8_t entry_status; /* Entry Status. */
1764 uint32_t handle; /* System defined handle */
1767 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1771 * ISP queue - ATIO queue entry definition.
1774 uint8_t entry_type; /* Entry type. */
1775 uint8_t entry_count; /* Entry count. */
1776 __le16 attr_n_length;
1779 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1790 #define SET_TARGET_ID(ha, to, from) \
1792 if (HAS_EXTENDED_IDS(ha)) \
1793 to.extended = cpu_to_le16(from); \
1795 to.id.standard = (uint8_t)from; \
1799 * ISP queue - command entry structure definition.
1801 #define COMMAND_TYPE 0x11 /* Command entry */
1803 uint8_t entry_type; /* Entry type. */
1804 uint8_t entry_count; /* Entry count. */
1805 uint8_t sys_define; /* System defined. */
1806 uint8_t entry_status; /* Entry Status. */
1807 uint32_t handle; /* System handle. */
1808 target_id_t target; /* SCSI ID */
1809 uint16_t lun; /* SCSI LUN */
1810 uint16_t control_flags; /* Control flags. */
1811 #define CF_WRITE BIT_6
1812 #define CF_READ BIT_5
1813 #define CF_SIMPLE_TAG BIT_3
1814 #define CF_ORDERED_TAG BIT_2
1815 #define CF_HEAD_TAG BIT_1
1816 uint16_t reserved_1;
1817 uint16_t timeout; /* Command timeout. */
1818 uint16_t dseg_count; /* Data segment count. */
1819 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1820 uint32_t byte_count; /* Total byte count. */
1822 struct dsd32 dsd32[3];
1823 struct dsd64 dsd64[2];
1828 * ISP queue - 64-Bit addressing, command entry structure definition.
1830 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1832 uint8_t entry_type; /* Entry type. */
1833 uint8_t entry_count; /* Entry count. */
1834 uint8_t sys_define; /* System defined. */
1835 uint8_t entry_status; /* Entry Status. */
1836 uint32_t handle; /* System handle. */
1837 target_id_t target; /* SCSI ID */
1838 uint16_t lun; /* SCSI LUN */
1839 uint16_t control_flags; /* Control flags. */
1840 uint16_t reserved_1;
1841 uint16_t timeout; /* Command timeout. */
1842 uint16_t dseg_count; /* Data segment count. */
1843 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1844 uint32_t byte_count; /* Total byte count. */
1845 struct dsd64 dsd[2];
1846 } cmd_a64_entry_t, request_t;
1849 * ISP queue - continuation entry structure definition.
1851 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1853 uint8_t entry_type; /* Entry type. */
1854 uint8_t entry_count; /* Entry count. */
1855 uint8_t sys_define; /* System defined. */
1856 uint8_t entry_status; /* Entry Status. */
1858 struct dsd32 dsd[7];
1862 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1864 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1866 uint8_t entry_type; /* Entry type. */
1867 uint8_t entry_count; /* Entry count. */
1868 uint8_t sys_define; /* System defined. */
1869 uint8_t entry_status; /* Entry Status. */
1870 struct dsd64 dsd[5];
1873 #define PO_MODE_DIF_INSERT 0
1874 #define PO_MODE_DIF_REMOVE 1
1875 #define PO_MODE_DIF_PASS 2
1876 #define PO_MODE_DIF_REPLACE 3
1877 #define PO_MODE_DIF_TCP_CKSUM 6
1878 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1879 #define PO_DISABLE_GUARD_CHECK BIT_4
1880 #define PO_DISABLE_INCR_REF_TAG BIT_5
1881 #define PO_DIS_HEADER_MODE BIT_7
1882 #define PO_ENABLE_DIF_BUNDLING BIT_8
1883 #define PO_DIS_FRAME_MODE BIT_9
1884 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1885 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1887 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1888 #define PO_DIS_REF_TAG_REPL BIT_13
1889 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1890 #define PO_DIS_REF_TAG_VALD BIT_15
1893 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1895 struct crc_context {
1896 uint32_t handle; /* System handle. */
1899 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1900 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1901 __le16 guard_seed; /* Initial Guard Seed */
1902 __le16 prot_opts; /* Requested Data Protection Mode */
1903 __le16 blk_size; /* Data size in bytes */
1904 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1906 __le32 byte_count; /* Total byte count/ total data
1910 uint32_t reserved_1;
1911 uint16_t reserved_2;
1912 uint16_t reserved_3;
1913 uint32_t reserved_4;
1914 struct dsd64 data_dsd[1];
1915 uint32_t reserved_5[2];
1916 uint32_t reserved_6;
1919 __le32 dif_byte_count; /* Total DIF byte
1921 uint16_t reserved_1;
1922 __le16 dseg_count; /* Data segment count */
1923 uint32_t reserved_2;
1924 struct dsd64 data_dsd[1];
1925 struct dsd64 dif_dsd;
1929 struct fcp_cmnd fcp_cmnd;
1930 dma_addr_t crc_ctx_dma;
1931 /* List of DMA context transfers */
1932 struct list_head dsd_list;
1934 /* List of DIF Bundling context DMA address */
1935 struct list_head ldif_dsd_list;
1938 struct list_head ldif_dma_hndl_list;
1941 /* This structure should not exceed 512 bytes */
1944 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1945 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1948 * ISP queue - status entry structure definition.
1950 #define STATUS_TYPE 0x03 /* Status entry. */
1952 uint8_t entry_type; /* Entry type. */
1953 uint8_t entry_count; /* Entry count. */
1954 uint8_t sys_define; /* System defined. */
1955 uint8_t entry_status; /* Entry Status. */
1956 uint32_t handle; /* System handle. */
1957 uint16_t scsi_status; /* SCSI status. */
1958 uint16_t comp_status; /* Completion status. */
1959 uint16_t state_flags; /* State flags. */
1960 uint16_t status_flags; /* Status flags. */
1961 uint16_t rsp_info_len; /* Response Info Length. */
1962 uint16_t req_sense_length; /* Request sense data length. */
1963 uint32_t residual_length; /* Residual transfer length. */
1964 uint8_t rsp_info[8]; /* FCP response information. */
1965 uint8_t req_sense_data[32]; /* Request sense data. */
1969 * Status entry entry status
1971 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1972 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1973 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1974 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1975 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1976 #define RF_BUSY BIT_1 /* Busy */
1977 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1978 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1979 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1983 * Status entry SCSI status bit definitions.
1985 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1986 #define SS_RESIDUAL_UNDER BIT_11
1987 #define SS_RESIDUAL_OVER BIT_10
1988 #define SS_SENSE_LEN_VALID BIT_9
1989 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1990 #define SS_SCSI_STATUS_BYTE 0xff
1992 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1993 #define SS_BUSY_CONDITION BIT_3
1994 #define SS_CONDITION_MET BIT_2
1995 #define SS_CHECK_CONDITION BIT_1
1998 * Status entry completion status
2000 #define CS_COMPLETE 0x0 /* No errors */
2001 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
2002 #define CS_DMA 0x2 /* A DMA direction error. */
2003 #define CS_TRANSPORT 0x3 /* Transport error. */
2004 #define CS_RESET 0x4 /* SCSI bus reset occurred */
2005 #define CS_ABORTED 0x5 /* System aborted command. */
2006 #define CS_TIMEOUT 0x6 /* Timeout error. */
2007 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
2008 #define CS_DIF_ERROR 0xC /* DIF error detected */
2010 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
2011 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
2012 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
2013 /* (selection timeout) */
2014 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
2015 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
2016 #define CS_PORT_BUSY 0x2B /* Port Busy */
2017 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
2018 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
2020 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
2021 #define CS_UNKNOWN 0x81 /* Driver defined */
2022 #define CS_RETRY 0x82 /* Driver defined */
2023 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
2025 #define CS_BIDIR_RD_OVERRUN 0x700
2026 #define CS_BIDIR_RD_WR_OVERRUN 0x707
2027 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2028 #define CS_BIDIR_RD_UNDERRUN 0x1500
2029 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2030 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2031 #define CS_BIDIR_DMA 0x200
2033 * Status entry status flags
2035 #define SF_ABTS_TERMINATED BIT_10
2036 #define SF_LOGOUT_SENT BIT_13
2039 * ISP queue - status continuation entry structure definition.
2041 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
2043 uint8_t entry_type; /* Entry type. */
2044 uint8_t entry_count; /* Entry count. */
2045 uint8_t sys_define; /* System defined. */
2046 uint8_t entry_status; /* Entry Status. */
2047 uint8_t data[60]; /* data */
2051 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
2052 * structure definition.
2054 #define STATUS_TYPE_21 0x21 /* Status entry. */
2056 uint8_t entry_type; /* Entry type. */
2057 uint8_t entry_count; /* Entry count. */
2058 uint8_t handle_count; /* Handle count. */
2059 uint8_t entry_status; /* Entry Status. */
2060 uint32_t handle[15]; /* System handles. */
2064 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2065 * structure definition.
2067 #define STATUS_TYPE_22 0x22 /* Status entry. */
2069 uint8_t entry_type; /* Entry type. */
2070 uint8_t entry_count; /* Entry count. */
2071 uint8_t handle_count; /* Handle count. */
2072 uint8_t entry_status; /* Entry Status. */
2073 uint16_t handle[30]; /* System handles. */
2077 * ISP queue - marker entry structure definition.
2079 #define MARKER_TYPE 0x04 /* Marker entry. */
2081 uint8_t entry_type; /* Entry type. */
2082 uint8_t entry_count; /* Entry count. */
2083 uint8_t handle_count; /* Handle count. */
2084 uint8_t entry_status; /* Entry Status. */
2085 uint32_t sys_define_2; /* System defined. */
2086 target_id_t target; /* SCSI ID */
2087 uint8_t modifier; /* Modifier (7-0). */
2088 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2089 #define MK_SYNC_ID 1 /* Synchronize ID */
2090 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2091 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2092 /* clear port changed, */
2093 /* use sequence number. */
2095 uint16_t sequence_number; /* Sequence number of event */
2096 uint16_t lun; /* SCSI LUN */
2097 uint8_t reserved_2[48];
2101 * ISP queue - Management Server entry structure definition.
2103 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2105 uint8_t entry_type; /* Entry type. */
2106 uint8_t entry_count; /* Entry count. */
2107 uint8_t handle_count; /* Handle count. */
2108 uint8_t entry_status; /* Entry Status. */
2109 uint32_t handle1; /* System handle. */
2110 target_id_t loop_id;
2112 uint16_t control_flags; /* Control flags. */
2115 uint16_t cmd_dsd_count;
2116 uint16_t total_dsd_count;
2122 uint32_t rsp_bytecount;
2123 uint32_t req_bytecount;
2124 struct dsd64 req_dsd;
2125 struct dsd64 rsp_dsd;
2130 * ISP queue - Mailbox Command entry structure definition.
2132 #define MBX_IOCB_TYPE 0x39
2135 uint8_t entry_count;
2136 uint8_t sys_define1;
2137 /* Use sys_define1 for source type */
2138 #define SOURCE_SCSI 0x00
2139 #define SOURCE_IP 0x01
2140 #define SOURCE_VI 0x02
2141 #define SOURCE_SCTP 0x03
2142 #define SOURCE_MP 0x04
2143 #define SOURCE_MPIOCTL 0x05
2144 #define SOURCE_ASYNC_IOCB 0x07
2146 uint8_t entry_status;
2149 target_id_t loop_id;
2152 uint16_t state_flags;
2153 uint16_t status_flags;
2155 uint32_t sys_define2[2];
2165 uint32_t reserved_2[2];
2166 uint8_t node_name[WWN_SIZE];
2167 uint8_t port_name[WWN_SIZE];
2170 #ifndef IMMED_NOTIFY_TYPE
2171 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2173 * ISP queue - immediate notify entry structure definition.
2174 * This is sent by the ISP to the Target driver.
2175 * This IOCB would have report of events sent by the
2176 * initiator, that needs to be handled by the target
2177 * driver immediately.
2179 struct imm_ntfy_from_isp {
2180 uint8_t entry_type; /* Entry type. */
2181 uint8_t entry_count; /* Entry count. */
2182 uint8_t sys_define; /* System defined. */
2183 uint8_t entry_status; /* Entry Status. */
2186 uint32_t sys_define_2; /* System defined. */
2191 uint16_t status_modifier;
2193 uint16_t task_flags;
2196 uint32_t srr_rel_offs;
2198 #define SRR_IU_DATA_IN 0x1
2199 #define SRR_IU_DATA_OUT 0x5
2200 #define SRR_IU_STATUS 0x7
2202 uint8_t reserved_2[28];
2206 uint16_t nport_handle;
2207 uint16_t reserved_2;
2209 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2210 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2213 uint8_t status_subcode;
2215 uint32_t exchange_address;
2216 uint32_t srr_rel_offs;
2221 uint8_t node_name[8];
2222 } plogi; /* PLOGI/ADISC/PDISC */
2224 /* PRLI word 3 bit 0-15 */
2231 uint16_t nport_handle;
2235 uint8_t port_name[8];
2238 uint32_t reserved_5;
2243 uint16_t reserved_7;
2249 * ISP request and response queue entry sizes
2251 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2252 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2257 * Switch info gathering structure.
2261 uint8_t node_name[WWN_SIZE];
2262 uint8_t port_name[WWN_SIZE];
2263 uint8_t fabric_port_name[WWN_SIZE];
2266 uint8_t fc4f_nvme; /* nvme fc4 feature bits */
2270 #define FC4_TYPE_FCP_SCSI 0x08
2271 #define FC4_TYPE_NVME 0x28
2272 #define FC4_TYPE_OTHER 0x0
2273 #define FC4_TYPE_UNKNOWN 0xff
2275 /* mailbox command 4G & above */
2276 struct mbx_24xx_entry {
2278 uint8_t entry_count;
2279 uint8_t sys_define1;
2280 uint8_t entry_status;
2285 #define IOCB_SIZE 64
2288 * Fibre channel port type.
2297 FCT_NVME_INITIATOR = 0x10,
2298 FCT_NVME_TARGET = 0x20,
2299 FCT_NVME_DISCOVERY = 0x40,
2303 enum qla_sess_deletion {
2304 QLA_SESS_DELETION_NONE = 0,
2305 QLA_SESS_DELETION_IN_PROGRESS,
2309 enum qlt_plogi_link_t {
2310 QLT_PLOGI_LINK_SAME_WWN,
2311 QLT_PLOGI_LINK_CONFLICT,
2315 struct qlt_plogi_ack_t {
2316 struct list_head list;
2317 struct imm_ntfy_from_isp iocb;
2323 struct ct_sns_desc {
2324 struct ct_sns_pkt *ct_sns;
2325 dma_addr_t ct_sns_dma;
2328 enum discovery_state {
2341 enum login_state { /* FW control Target side */
2342 DSC_LS_LLIOCB_SENT = 2,
2347 DSC_LS_PORT_UNAVAIL,
2348 DSC_LS_PRLO_PEND = 9,
2352 enum fcport_mgt_event {
2355 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */
2365 FCME_ELS_PLOGI_DONE,
2368 enum rscn_addr_format {
2376 * Fibre channel port structure.
2378 typedef struct fc_port {
2379 struct list_head list;
2380 struct scsi_qla_host *vha;
2382 uint8_t node_name[WWN_SIZE];
2383 uint8_t port_name[WWN_SIZE];
2386 uint16_t old_loop_id;
2388 unsigned int conf_compl_supported:1;
2389 unsigned int deleted:2;
2390 unsigned int free_pending:1;
2391 unsigned int local:1;
2392 unsigned int logout_on_delete:1;
2393 unsigned int logo_ack_needed:1;
2394 unsigned int keep_nport_handle:1;
2395 unsigned int send_els_logo:1;
2396 unsigned int login_pause:1;
2397 unsigned int login_succ:1;
2398 unsigned int query:1;
2399 unsigned int id_changed:1;
2400 unsigned int scan_needed:1;
2402 struct completion nvme_del_done;
2403 uint32_t nvme_prli_service_param;
2404 #define NVME_PRLI_SP_CONF BIT_7
2405 #define NVME_PRLI_SP_INITIATOR BIT_5
2406 #define NVME_PRLI_SP_TARGET BIT_4
2407 #define NVME_PRLI_SP_DISCOVERY BIT_3
2408 #define NVME_PRLI_SP_FIRST_BURST BIT_0
2410 uint32_t nvme_first_burst_size;
2411 #define NVME_FLAG_REGISTERED 4
2412 #define NVME_FLAG_DELETING 2
2413 #define NVME_FLAG_RESETTING 1
2415 struct fc_port *conflict;
2416 unsigned char logout_completed;
2419 struct se_session *se_sess;
2420 struct kref sess_kref;
2421 struct qla_tgt *tgt;
2422 unsigned long expires;
2423 struct list_head del_list_entry;
2424 struct work_struct free_work;
2425 struct work_struct reg_work;
2426 uint64_t jiffies_at_registration;
2427 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2430 uint16_t old_tgt_id;
2431 uint16_t sec_since_registration;
2435 uint8_t fabric_port_name[WWN_SIZE];
2438 fc_port_type_t port_type;
2445 struct fc_rport *rport, *drport;
2446 u32 supported_classes;
2453 unsigned long last_queue_full;
2454 unsigned long last_ramp_up;
2458 struct nvme_fc_remote_port *nvme_remote_port;
2460 unsigned long retry_delay_timestamp;
2461 struct qla_tgt_sess *tgt_session;
2462 struct ct_sns_desc ct_desc;
2463 enum discovery_state disc_state;
2464 enum discovery_state next_disc_state;
2465 enum login_state fw_login_state;
2466 unsigned long dm_login_expire;
2467 unsigned long plogi_nack_done_deadline;
2469 u32 login_gen, last_login_gen;
2470 u32 rscn_gen, last_rscn_gen;
2472 struct list_head gnl_entry;
2473 struct work_struct del_work;
2475 u8 current_login_state;
2476 u8 last_login_state;
2477 u16 n2n_link_reset_cnt;
2481 #define QLA_FCPORT_SCAN 1
2482 #define QLA_FCPORT_FOUND 2
2485 enum fcport_mgt_event event;
2490 u8 port_name[WWN_SIZE];
2497 * Fibre channel port/lun states.
2499 #define FCS_UNCONFIGURED 1
2500 #define FCS_DEVICE_DEAD 2
2501 #define FCS_DEVICE_LOST 3
2502 #define FCS_ONLINE 4
2504 extern const char *const port_state_str[5];
2509 #define FCF_FABRIC_DEVICE BIT_0
2510 #define FCF_LOGIN_NEEDED BIT_1
2511 #define FCF_FCP2_DEVICE BIT_2
2512 #define FCF_ASYNC_SENT BIT_3
2513 #define FCF_CONF_COMP_SUPPORTED BIT_4
2514 #define FCF_ASYNC_ACTIVE BIT_5
2516 /* No loop ID flag. */
2517 #define FC_NO_LOOP_ID 0x1000
2522 * NOTE: All structures are big-endian in form.
2525 #define CT_REJECT_RESPONSE 0x8001
2526 #define CT_ACCEPT_RESPONSE 0x8002
2527 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2528 #define CT_REASON_CANNOT_PERFORM 0x09
2529 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2530 #define CT_EXPL_ALREADY_REGISTERED 0x10
2531 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2532 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2533 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2534 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2535 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2536 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2537 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2538 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2539 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2540 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2541 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2543 #define NS_N_PORT_TYPE 0x01
2544 #define NS_NL_PORT_TYPE 0x02
2545 #define NS_NX_PORT_TYPE 0x7F
2547 #define GA_NXT_CMD 0x100
2548 #define GA_NXT_REQ_SIZE (16 + 4)
2549 #define GA_NXT_RSP_SIZE (16 + 620)
2551 #define GPN_FT_CMD 0x172
2552 #define GPN_FT_REQ_SIZE (16 + 4)
2553 #define GNN_FT_CMD 0x173
2554 #define GNN_FT_REQ_SIZE (16 + 4)
2556 #define GID_PT_CMD 0x1A1
2557 #define GID_PT_REQ_SIZE (16 + 4)
2559 #define GPN_ID_CMD 0x112
2560 #define GPN_ID_REQ_SIZE (16 + 4)
2561 #define GPN_ID_RSP_SIZE (16 + 8)
2563 #define GNN_ID_CMD 0x113
2564 #define GNN_ID_REQ_SIZE (16 + 4)
2565 #define GNN_ID_RSP_SIZE (16 + 8)
2567 #define GFT_ID_CMD 0x117
2568 #define GFT_ID_REQ_SIZE (16 + 4)
2569 #define GFT_ID_RSP_SIZE (16 + 32)
2571 #define GID_PN_CMD 0x121
2572 #define GID_PN_REQ_SIZE (16 + 8)
2573 #define GID_PN_RSP_SIZE (16 + 4)
2575 #define RFT_ID_CMD 0x217
2576 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2577 #define RFT_ID_RSP_SIZE 16
2579 #define RFF_ID_CMD 0x21F
2580 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2581 #define RFF_ID_RSP_SIZE 16
2583 #define RNN_ID_CMD 0x213
2584 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2585 #define RNN_ID_RSP_SIZE 16
2587 #define RSNN_NN_CMD 0x239
2588 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2589 #define RSNN_NN_RSP_SIZE 16
2591 #define GFPN_ID_CMD 0x11C
2592 #define GFPN_ID_REQ_SIZE (16 + 4)
2593 #define GFPN_ID_RSP_SIZE (16 + 8)
2595 #define GPSC_CMD 0x127
2596 #define GPSC_REQ_SIZE (16 + 8)
2597 #define GPSC_RSP_SIZE (16 + 2 + 2)
2599 #define GFF_ID_CMD 0x011F
2600 #define GFF_ID_REQ_SIZE (16 + 4)
2601 #define GFF_ID_RSP_SIZE (16 + 128)
2604 * HBA attribute types.
2606 #define FDMI_HBA_ATTR_COUNT 9
2607 #define FDMIV2_HBA_ATTR_COUNT 17
2608 #define FDMI_HBA_NODE_NAME 0x1
2609 #define FDMI_HBA_MANUFACTURER 0x2
2610 #define FDMI_HBA_SERIAL_NUMBER 0x3
2611 #define FDMI_HBA_MODEL 0x4
2612 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2613 #define FDMI_HBA_HARDWARE_VERSION 0x6
2614 #define FDMI_HBA_DRIVER_VERSION 0x7
2615 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2616 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2617 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2618 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2619 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2620 #define FDMI_HBA_VENDOR_ID 0xd
2621 #define FDMI_HBA_NUM_PORTS 0xe
2622 #define FDMI_HBA_FABRIC_NAME 0xf
2623 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2624 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2626 struct ct_fdmi_hba_attr {
2630 uint8_t node_name[WWN_SIZE];
2631 uint8_t manufacturer[64];
2632 uint8_t serial_num[32];
2633 uint8_t model[16+1];
2634 uint8_t model_desc[80];
2635 uint8_t hw_version[32];
2636 uint8_t driver_version[32];
2637 uint8_t orom_version[16];
2638 uint8_t fw_version[32];
2639 uint8_t os_version[128];
2640 uint32_t max_ct_len;
2644 struct ct_fdmi_hba_attributes {
2646 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2649 struct ct_fdmiv2_hba_attr {
2653 uint8_t node_name[WWN_SIZE];
2654 uint8_t manufacturer[64];
2655 uint8_t serial_num[32];
2656 uint8_t model[16+1];
2657 uint8_t model_desc[80];
2658 uint8_t hw_version[16];
2659 uint8_t driver_version[32];
2660 uint8_t orom_version[16];
2661 uint8_t fw_version[32];
2662 uint8_t os_version[128];
2663 uint32_t max_ct_len;
2664 uint8_t sym_name[256];
2667 uint8_t fabric_name[WWN_SIZE];
2668 uint8_t bios_name[32];
2669 uint8_t vendor_identifier[8];
2673 struct ct_fdmiv2_hba_attributes {
2675 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2679 * Port attribute types.
2681 #define FDMI_PORT_ATTR_COUNT 6
2682 #define FDMIV2_PORT_ATTR_COUNT 16
2683 #define FDMI_PORT_FC4_TYPES 0x1
2684 #define FDMI_PORT_SUPPORT_SPEED 0x2
2685 #define FDMI_PORT_CURRENT_SPEED 0x3
2686 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2687 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2688 #define FDMI_PORT_HOST_NAME 0x6
2689 #define FDMI_PORT_NODE_NAME 0x7
2690 #define FDMI_PORT_NAME 0x8
2691 #define FDMI_PORT_SYM_NAME 0x9
2692 #define FDMI_PORT_TYPE 0xa
2693 #define FDMI_PORT_SUPP_COS 0xb
2694 #define FDMI_PORT_FABRIC_NAME 0xc
2695 #define FDMI_PORT_FC4_TYPE 0xd
2696 #define FDMI_PORT_STATE 0x101
2697 #define FDMI_PORT_COUNT 0x102
2698 #define FDMI_PORT_ID 0x103
2700 #define FDMI_PORT_SPEED_1GB 0x1
2701 #define FDMI_PORT_SPEED_2GB 0x2
2702 #define FDMI_PORT_SPEED_10GB 0x4
2703 #define FDMI_PORT_SPEED_4GB 0x8
2704 #define FDMI_PORT_SPEED_8GB 0x10
2705 #define FDMI_PORT_SPEED_16GB 0x20
2706 #define FDMI_PORT_SPEED_32GB 0x40
2707 #define FDMI_PORT_SPEED_64GB 0x80
2708 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2710 #define FC_CLASS_2 0x04
2711 #define FC_CLASS_3 0x08
2712 #define FC_CLASS_2_3 0x0C
2714 struct ct_fdmiv2_port_attr {
2718 uint8_t fc4_types[32];
2721 uint32_t max_frame_size;
2722 uint8_t os_dev_name[32];
2723 uint8_t host_name[256];
2724 uint8_t node_name[WWN_SIZE];
2725 uint8_t port_name[WWN_SIZE];
2726 uint8_t port_sym_name[128];
2728 uint32_t port_supported_cos;
2729 uint8_t fabric_name[WWN_SIZE];
2730 uint8_t port_fc4_type[32];
2731 uint32_t port_state;
2738 * Port Attribute Block.
2740 struct ct_fdmiv2_port_attributes {
2742 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2745 struct ct_fdmi_port_attr {
2749 uint8_t fc4_types[32];
2752 uint32_t max_frame_size;
2753 uint8_t os_dev_name[32];
2754 uint8_t host_name[256];
2758 struct ct_fdmi_port_attributes {
2760 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2763 /* FDMI definitions. */
2764 #define GRHL_CMD 0x100
2765 #define GHAT_CMD 0x101
2766 #define GRPL_CMD 0x102
2767 #define GPAT_CMD 0x110
2769 #define RHBA_CMD 0x200
2770 #define RHBA_RSP_SIZE 16
2772 #define RHAT_CMD 0x201
2773 #define RPRT_CMD 0x210
2775 #define RPA_CMD 0x211
2776 #define RPA_RSP_SIZE 16
2778 #define DHBA_CMD 0x300
2779 #define DHBA_REQ_SIZE (16 + 8)
2780 #define DHBA_RSP_SIZE 16
2782 #define DHAT_CMD 0x301
2783 #define DPRT_CMD 0x310
2784 #define DPA_CMD 0x311
2786 /* CT command header -- request/response common fields */
2796 /* CT command request */
2798 struct ct_cmd_hdr header;
2800 uint16_t max_rsp_size;
2801 uint8_t fragment_id;
2802 uint8_t reserved[3];
2805 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2828 uint8_t fc4_types[32];
2835 uint8_t fc4_feature;
2842 uint8_t node_name[8];
2846 uint8_t node_name[8];
2848 uint8_t sym_node_name[255];
2852 uint8_t hba_identifier[8];
2856 uint8_t hba_identifier[8];
2857 uint32_t entry_count;
2858 uint8_t port_name[8];
2859 struct ct_fdmi_hba_attributes attrs;
2863 uint8_t hba_identifier[8];
2864 uint32_t entry_count;
2865 uint8_t port_name[8];
2866 struct ct_fdmiv2_hba_attributes attrs;
2870 uint8_t hba_identifier[8];
2871 struct ct_fdmi_hba_attributes attrs;
2875 uint8_t port_name[8];
2876 struct ct_fdmi_port_attributes attrs;
2880 uint8_t port_name[8];
2881 struct ct_fdmiv2_port_attributes attrs;
2885 uint8_t port_name[8];
2889 uint8_t port_name[8];
2893 uint8_t port_name[8];
2897 uint8_t port_name[8];
2901 uint8_t port_name[8];
2910 uint8_t port_name[8];
2915 /* CT command response header */
2917 struct ct_cmd_hdr header;
2920 uint8_t fragment_id;
2921 uint8_t reason_code;
2922 uint8_t explanation_code;
2923 uint8_t vendor_unique;
2926 struct ct_sns_gid_pt_data {
2927 uint8_t control_byte;
2931 /* It's the same for both GPN_FT and GNN_FT */
2932 struct ct_sns_gpnft_rsp {
2934 struct ct_cmd_hdr header;
2937 uint8_t fragment_id;
2938 uint8_t reason_code;
2939 uint8_t explanation_code;
2940 uint8_t vendor_unique;
2942 /* Assume the largest number of targets for the union */
2943 struct ct_sns_gpn_ft_data {
2951 /* CT command response */
2953 struct ct_rsp_hdr header;
2959 uint8_t port_name[8];
2960 uint8_t sym_port_name_len;
2961 uint8_t sym_port_name[255];
2962 uint8_t node_name[8];
2963 uint8_t sym_node_name_len;
2964 uint8_t sym_node_name[255];
2965 uint8_t init_proc_assoc[8];
2966 uint8_t node_ip_addr[16];
2967 uint8_t class_of_service[4];
2968 uint8_t fc4_types[32];
2969 uint8_t ip_address[16];
2970 uint8_t fabric_port_name[8];
2972 uint8_t hard_address[3];
2976 /* Assume the largest number of targets for the union */
2977 struct ct_sns_gid_pt_data
2978 entries[MAX_FIBRE_DEVICES_MAX];
2982 uint8_t port_name[8];
2986 uint8_t node_name[8];
2990 uint8_t fc4_types[32];
2994 uint32_t entry_count;
2995 uint8_t port_name[8];
2996 struct ct_fdmi_hba_attributes attrs;
3000 uint8_t port_name[8];
3008 #define GFF_FCP_SCSI_OFFSET 7
3009 #define GFF_NVME_OFFSET 23 /* type = 28h */
3011 uint8_t fc4_features[128];
3022 struct ct_sns_req req;
3023 struct ct_sns_rsp rsp;
3027 struct ct_sns_gpnft_pkt {
3029 struct ct_sns_req req;
3030 struct ct_sns_gpnft_rsp rsp;
3035 SF_SCANNING = BIT_0,
3040 FS_FC4TYPE_FCP = BIT_0,
3041 FS_FC4TYPE_NVME = BIT_1,
3044 struct fab_scan_rp {
3046 enum fc4type_t fc4type;
3052 struct fab_scan_rp *l;
3055 #define MAX_SCAN_RETRIES 5
3056 enum scan_flags_t scan_flags;
3057 struct delayed_work scan_work;
3061 * SNS command structures -- for 2200 compatibility.
3063 #define RFT_ID_SNS_SCMD_LEN 22
3064 #define RFT_ID_SNS_CMD_SIZE 60
3065 #define RFT_ID_SNS_DATA_SIZE 16
3067 #define RNN_ID_SNS_SCMD_LEN 10
3068 #define RNN_ID_SNS_CMD_SIZE 36
3069 #define RNN_ID_SNS_DATA_SIZE 16
3071 #define GA_NXT_SNS_SCMD_LEN 6
3072 #define GA_NXT_SNS_CMD_SIZE 28
3073 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3075 #define GID_PT_SNS_SCMD_LEN 6
3076 #define GID_PT_SNS_CMD_SIZE 28
3078 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3081 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3083 #define GPN_ID_SNS_SCMD_LEN 6
3084 #define GPN_ID_SNS_CMD_SIZE 28
3085 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3087 #define GNN_ID_SNS_SCMD_LEN 6
3088 #define GNN_ID_SNS_CMD_SIZE 28
3089 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3091 struct sns_cmd_pkt {
3094 uint16_t buffer_length;
3095 uint16_t reserved_1;
3096 __le64 buffer_address __packed;
3097 uint16_t subcommand_length;
3098 uint16_t reserved_2;
3099 uint16_t subcommand;
3101 uint32_t reserved_3;
3105 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3106 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3107 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3108 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3109 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3110 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3117 const struct firmware *fw;
3120 /* Return data from MBC_GET_ID_LIST call. */
3121 struct gid_list_info {
3125 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3126 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3127 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3131 typedef struct vport_info {
3132 uint8_t port_name[WWN_SIZE];
3133 uint8_t node_name[WWN_SIZE];
3136 unsigned long host_no;
3141 typedef struct vport_params {
3142 uint8_t port_name[WWN_SIZE];
3143 uint8_t node_name[WWN_SIZE];
3145 #define VP_OPTS_RETRY_ENABLE BIT_0
3146 #define VP_OPTS_VP_DISABLE BIT_1
3149 /* NPIV - return codes of VP create and modify */
3150 #define VP_RET_CODE_OK 0
3151 #define VP_RET_CODE_FATAL 1
3152 #define VP_RET_CODE_WRONG_ID 2
3153 #define VP_RET_CODE_WWPN 3
3154 #define VP_RET_CODE_RESOURCES 4
3155 #define VP_RET_CODE_NO_MEM 5
3156 #define VP_RET_CODE_NOT_FOUND 6
3163 struct isp_operations {
3165 int (*pci_config) (struct scsi_qla_host *);
3166 int (*reset_chip)(struct scsi_qla_host *);
3167 int (*chip_diag) (struct scsi_qla_host *);
3168 void (*config_rings) (struct scsi_qla_host *);
3169 int (*reset_adapter)(struct scsi_qla_host *);
3170 int (*nvram_config) (struct scsi_qla_host *);
3171 void (*update_fw_options) (struct scsi_qla_host *);
3172 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3174 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3175 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3177 irq_handler_t intr_handler;
3178 void (*enable_intrs) (struct qla_hw_data *);
3179 void (*disable_intrs) (struct qla_hw_data *);
3181 int (*abort_command) (srb_t *);
3182 int (*target_reset) (struct fc_port *, uint64_t, int);
3183 int (*lun_reset) (struct fc_port *, uint64_t, int);
3184 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3185 uint8_t, uint8_t, uint16_t *, uint8_t);
3186 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3189 uint16_t (*calc_req_entries) (uint16_t);
3190 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3191 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3192 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3195 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3196 uint32_t, uint32_t);
3197 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3200 void (*fw_dump) (struct scsi_qla_host *, int);
3202 int (*beacon_on) (struct scsi_qla_host *);
3203 int (*beacon_off) (struct scsi_qla_host *);
3204 void (*beacon_blink) (struct scsi_qla_host *);
3206 void *(*read_optrom)(struct scsi_qla_host *, void *,
3207 uint32_t, uint32_t);
3208 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3211 int (*get_flash_version) (struct scsi_qla_host *, void *);
3212 int (*start_scsi) (srb_t *);
3213 int (*start_scsi_mq) (srb_t *);
3214 int (*abort_isp) (struct scsi_qla_host *);
3215 int (*iospace_config)(struct qla_hw_data *);
3216 int (*initialize_adapter)(struct scsi_qla_host *);
3219 /* MSI-X Support *************************************************************/
3221 #define QLA_MSIX_CHIP_REV_24XX 3
3222 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3223 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3225 #define QLA_BASE_VECTORS 2 /* default + RSP */
3226 #define QLA_MSIX_RSP_Q 0x01
3227 #define QLA_ATIO_VECTOR 0x02
3228 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3230 #define QLA_MIDX_DEFAULT 0
3231 #define QLA_MIDX_RSP_Q 1
3232 #define QLA_PCI_MSIX_CONTROL 0xa2
3233 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3235 struct scsi_qla_host;
3238 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3240 struct qla_msix_entry {
3250 #define WATCH_INTERVAL 1 /* number of seconds */
3253 enum qla_work_type {
3256 QLA_EVT_ASYNC_LOGIN,
3257 QLA_EVT_ASYNC_LOGOUT,
3258 QLA_EVT_ASYNC_LOGOUT_DONE,
3259 QLA_EVT_ASYNC_ADISC,
3272 QLA_EVT_ASYNC_PRLO_DONE,
3284 struct qla_work_evt {
3285 struct list_head list;
3286 enum qla_work_type type;
3288 #define QLA_EVT_FLAG_FREE 0x1
3292 enum fc_host_event_code code;
3296 #define QLA_IDC_ACK_REGS 7
3297 uint16_t mb[QLA_IDC_ACK_REGS];
3300 struct fc_port *fcport;
3301 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3306 #define QLA_UEVENT_CODE_FW_DUMP 0
3326 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3342 struct qla_chip_state_84xx {
3343 struct list_head list;
3347 spinlock_t access_lock;
3348 struct mutex fw_update_mutex;
3350 uint32_t op_fw_version;
3351 uint32_t op_fw_size;
3352 uint32_t op_fw_seq_size;
3353 uint32_t diag_fw_version;
3354 uint32_t gold_fw_version;
3357 struct qla_dif_statistics {
3358 uint64_t dif_input_bytes;
3359 uint64_t dif_output_bytes;
3360 uint64_t dif_input_requests;
3361 uint64_t dif_output_requests;
3362 uint32_t dif_guard_err;
3363 uint32_t dif_ref_tag_err;
3364 uint32_t dif_app_tag_err;
3367 struct qla_statistics {
3368 uint32_t total_isp_aborts;
3369 uint64_t input_bytes;
3370 uint64_t output_bytes;
3371 uint64_t input_requests;
3372 uint64_t output_requests;
3373 uint32_t control_requests;
3375 uint64_t jiffies_at_last_reset;
3376 uint32_t stat_max_pend_cmds;
3377 uint32_t stat_max_qfull_cmds_alloc;
3378 uint32_t stat_max_qfull_cmds_dropped;
3380 struct qla_dif_statistics qla_dif_stats;
3383 struct bidi_statistics {
3384 unsigned long long io_count;
3385 unsigned long long transfer_bytes;
3388 struct qla_tc_param {
3389 struct scsi_qla_host *vha;
3392 struct scatterlist *sg;
3393 struct scatterlist *prot_sg;
3394 struct crc_context *ctx;
3395 uint8_t *ctx_dsd_alloced;
3398 /* Multi queue support */
3399 #define MBC_INITIALIZE_MULTIQ 0x1f
3400 #define QLA_QUE_PAGE 0X1000
3401 #define QLA_MQ_SIZE 32
3402 #define QLA_MAX_QUEUES 256
3403 #define ISP_QUE_REG(ha, id) \
3404 ((ha->mqenable || IS_QLA83XX(ha) || \
3405 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3406 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3407 ((void __iomem *)ha->iobase))
3408 #define QLA_REQ_QUE_ID(tag) \
3409 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3410 #define QLA_DEFAULT_QUE_QOS 5
3411 #define QLA_PRECONFIG_VPORTS 32
3412 #define QLA_MAX_VPORTS_QLA24XX 128
3413 #define QLA_MAX_VPORTS_QLA25XX 256
3415 struct qla_tgt_counters {
3416 uint64_t qla_core_sbt_cmd;
3417 uint64_t core_qla_que_buf;
3418 uint64_t qla_core_ret_ctio;
3419 uint64_t core_qla_snd_status;
3420 uint64_t qla_core_ret_sta_ctio;
3421 uint64_t core_qla_free_cmd;
3422 uint64_t num_q_full_sent;
3423 uint64_t num_alloc_iocb_failed;
3424 uint64_t num_term_xchg_sent;
3429 /* Response queue data structure */
3433 response_t *ring_ptr;
3434 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
3435 uint32_t __iomem *rsp_q_out;
3436 uint16_t ring_index;
3438 uint16_t *in_ptr; /* queue shadow in index */
3444 struct qla_hw_data *hw;
3445 struct qla_msix_entry *msix;
3446 struct req_que *req;
3447 srb_t *status_srb; /* status continuation entry */
3448 struct qla_qpair *qpair;
3450 dma_addr_t dma_fx00;
3451 response_t *ring_fx00;
3452 uint16_t length_fx00;
3453 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3456 /* Request queue data structure */
3460 request_t *ring_ptr;
3461 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
3462 uint32_t __iomem *req_q_out;
3463 uint16_t ring_index;
3465 uint16_t *out_ptr; /* queue shadow out index */
3473 struct rsp_que *rsp;
3474 srb_t **outstanding_cmds;
3475 uint32_t current_outstanding_cmd;
3476 uint16_t num_outstanding_cmds;
3479 dma_addr_t dma_fx00;
3480 request_t *ring_fx00;
3481 uint16_t length_fx00;
3482 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3485 /*Queue pair data structure */
3491 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3492 * legacy code. For other Qpair(s), it will point at qp_lock.
3494 spinlock_t *qp_lock_ptr;
3495 struct scsi_qla_host *vha;
3498 /* distill these fields down to 'online=0/1'
3499 * ha->flags.eeh_busy
3500 * ha->flags.pci_channel_io_perm_failure
3501 * base_vha->loop_state
3504 /* move vha->flags.difdix_supported here */
3505 uint32_t difdix_supported:1;
3506 uint32_t delete_in_progress:1;
3507 uint32_t fw_started:1;
3508 uint32_t enable_class_2:1;
3509 uint32_t enable_explicit_conf:1;
3510 uint32_t use_shadow_reg:1;
3512 uint16_t id; /* qp number used with FW */
3513 uint16_t vp_idx; /* vport ID */
3514 mempool_t *srb_mempool;
3516 struct pci_dev *pdev;
3517 void (*reqq_start_iocbs)(struct qla_qpair *);
3519 /* to do: New driver: move queues to here instead of pointers */
3520 struct req_que *req;
3521 struct rsp_que *rsp;
3522 struct atio_que *atio;
3523 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3524 struct qla_hw_data *hw;
3525 struct work_struct q_work;
3526 struct list_head qp_list_elem; /* vha->qp_list */
3527 struct list_head hints_list;
3529 uint16_t retry_term_cnt;
3530 uint32_t retry_term_exchg_addr;
3531 uint64_t retry_term_jiff;
3532 struct qla_tgt_counters tgt_counters;
3535 /* Place holder for FW buffer parameters */
3542 struct scsi_qlt_host {
3543 void *target_lport_ptr;
3544 struct mutex tgt_mutex;
3545 struct mutex tgt_host_action_mutex;
3546 struct qla_tgt *qla_tgt;
3549 struct qlt_hw_data {
3550 /* Protected by hw lock */
3551 uint32_t node_name_set:1;
3553 dma_addr_t atio_dma; /* Physical address. */
3554 struct atio *atio_ring; /* Base virtual address */
3555 struct atio *atio_ring_ptr; /* Current address. */
3556 uint16_t atio_ring_index; /* Current index. */
3557 uint16_t atio_q_length;
3558 uint32_t __iomem *atio_q_in;
3559 uint32_t __iomem *atio_q_out;
3561 struct qla_tgt_func_tmpl *tgt_ops;
3562 struct qla_tgt_vp_map *tgt_vp_map;
3565 uint16_t saved_exchange_count;
3566 uint32_t saved_firmware_options_1;
3567 uint32_t saved_firmware_options_2;
3568 uint32_t saved_firmware_options_3;
3569 uint8_t saved_firmware_options[2];
3570 uint8_t saved_add_firmware_options[2];
3572 uint8_t tgt_node_name[WWN_SIZE];
3574 struct dentry *dfs_tgt_sess;
3575 struct dentry *dfs_tgt_port_database;
3576 struct dentry *dfs_naqp;
3578 struct list_head q_full_list;
3579 uint32_t num_pend_cmds;
3580 uint32_t num_qfull_cmds_alloc;
3581 uint32_t num_qfull_cmds_dropped;
3582 spinlock_t q_full_lock;
3583 uint32_t leak_exchg_thresh_hold;
3584 spinlock_t sess_lock;
3586 #define DEFAULT_NAQP 2
3587 spinlock_t atio_lock ____cacheline_aligned;
3588 struct btree_head32 host_map;
3591 #define MAX_QFULL_CMDS_ALLOC 8192
3592 #define Q_FULL_THRESH_HOLD_PERCENT 90
3593 #define Q_FULL_THRESH_HOLD(ha) \
3594 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3596 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3599 * Qlogic host adapter specific data structure.
3601 struct qla_hw_data {
3602 struct pci_dev *pdev;
3604 #define SRB_MIN_REQ 128
3605 mempool_t *srb_mempool;
3608 uint32_t mbox_int :1;
3609 uint32_t mbox_busy :1;
3610 uint32_t disable_risc_code_load :1;
3611 uint32_t enable_64bit_addressing :1;
3612 uint32_t enable_lip_reset :1;
3613 uint32_t enable_target_reset :1;
3614 uint32_t enable_lip_full_login :1;
3615 uint32_t enable_led_scheme :1;
3617 uint32_t msi_enabled :1;
3618 uint32_t msix_enabled :1;
3619 uint32_t disable_serdes :1;
3620 uint32_t gpsc_supported :1;
3621 uint32_t npiv_supported :1;
3622 uint32_t pci_channel_io_perm_failure :1;
3623 uint32_t fce_enabled :1;
3624 uint32_t fac_supported :1;
3626 uint32_t chip_reset_done :1;
3627 uint32_t running_gold_fw :1;
3628 uint32_t eeh_busy :1;
3629 uint32_t disable_msix_handshake :1;
3630 uint32_t fcp_prio_enabled :1;
3631 uint32_t isp82xx_fw_hung:1;
3632 uint32_t nic_core_hung:1;
3634 uint32_t quiesce_owner:1;
3635 uint32_t nic_core_reset_hdlr_active:1;
3636 uint32_t nic_core_reset_owner:1;
3637 uint32_t isp82xx_no_md_cap:1;
3638 uint32_t host_shutting_down:1;
3639 uint32_t idc_compl_status:1;
3640 uint32_t mr_reset_hdlr_active:1;
3641 uint32_t mr_intr_valid:1;
3643 uint32_t dport_enabled:1;
3644 uint32_t fawwpn_enabled:1;
3645 uint32_t exlogins_enabled:1;
3646 uint32_t exchoffld_enabled:1;
3650 uint32_t fw_started:1;
3651 uint32_t fw_init_done:1;
3653 uint32_t detected_lr_sfp:1;
3654 uint32_t using_lr_setting:1;
3655 uint32_t rida_fmt2:1;
3656 uint32_t purge_mbox:1;
3657 uint32_t n2n_bigger:1;
3658 uint32_t secure_adapter:1;
3659 uint32_t secure_fw:1;
3663 uint16_t long_range_distance; /* 32G & above */
3664 #define LR_DISTANCE_5K 1
3665 #define LR_DISTANCE_10K 0
3667 /* This spinlock is used to protect "io transactions", you must
3668 * acquire it before doing any IO to the card, eg with RD_REG*() and
3669 * WRT_REG*() for the duration of your entire commandtransaction.
3671 * This spinlock is of lower priority than the io request lock.
3674 spinlock_t hardware_lock ____cacheline_aligned;
3677 device_reg_t *iobase; /* Base I/O address */
3678 resource_size_t pio_address;
3680 #define MIN_IOBASE_LEN 0x100
3681 dma_addr_t bar0_hdl;
3683 void __iomem *cregbase;
3684 dma_addr_t bar2_hdl;
3685 #define BAR0_LEN_FX00 (1024 * 1024)
3686 #define BAR2_LEN_FX00 (128 * 1024)
3688 uint32_t rqstq_intr_code;
3689 uint32_t mbx_intr_code;
3690 uint32_t req_que_len;
3691 uint32_t rsp_que_len;
3692 uint32_t req_que_off;
3693 uint32_t rsp_que_off;
3695 /* Multi queue data structs */
3696 device_reg_t *mqiobase;
3697 device_reg_t *msixbase;
3698 uint16_t msix_count;
3700 struct req_que **req_q_map;
3701 struct rsp_que **rsp_q_map;
3702 struct qla_qpair **queue_pair_map;
3703 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3704 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3705 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3706 / sizeof(unsigned long)];
3707 uint8_t max_req_queues;
3708 uint8_t max_rsp_queues;
3711 struct qla_qpair *base_qpair;
3712 struct qla_npiv_entry *npiv_info;
3713 uint16_t nvram_npiv_size;
3715 uint16_t switch_cap;
3716 #define FLOGI_SEQ_DEL BIT_8
3717 #define FLOGI_MID_SUPPORT BIT_10
3718 #define FLOGI_VSAN_SUPPORT BIT_12
3719 #define FLOGI_SP_SUPPORT BIT_13
3721 uint8_t port_no; /* Physical port of adapter */
3722 uint8_t exch_starvation;
3724 /* Timeout timers. */
3725 uint8_t loop_down_abort_time; /* port down timer */
3726 atomic_t loop_down_timer; /* loop down timer */
3727 uint8_t link_down_timeout; /* link down timeout */
3728 uint16_t max_loop_id;
3729 uint16_t max_fibre_devices; /* Maximum number of targets */
3732 uint16_t min_external_loopid; /* First external loop Id */
3734 #define PORT_SPEED_UNKNOWN 0xFFFF
3735 #define PORT_SPEED_1GB 0x00
3736 #define PORT_SPEED_2GB 0x01
3737 #define PORT_SPEED_AUTO 0x02
3738 #define PORT_SPEED_4GB 0x03
3739 #define PORT_SPEED_8GB 0x04
3740 #define PORT_SPEED_16GB 0x05
3741 #define PORT_SPEED_32GB 0x06
3742 #define PORT_SPEED_64GB 0x07
3743 #define PORT_SPEED_10GB 0x13
3744 uint16_t link_data_rate; /* F/W operating speed */
3745 uint16_t set_data_rate; /* Set by user */
3747 uint8_t current_topology;
3748 uint8_t prev_topology;
3749 #define ISP_CFG_NL 1
3751 #define ISP_CFG_FL 4
3754 uint8_t operating_mode; /* F/W operating mode */
3759 uint8_t interrupts_on;
3760 uint32_t isp_abort_cnt;
3761 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3762 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3763 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3764 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3765 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3766 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3767 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3768 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3769 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
3770 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
3771 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
3772 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
3773 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
3776 #define DT_ISP2100 BIT_0
3777 #define DT_ISP2200 BIT_1
3778 #define DT_ISP2300 BIT_2
3779 #define DT_ISP2312 BIT_3
3780 #define DT_ISP2322 BIT_4
3781 #define DT_ISP6312 BIT_5
3782 #define DT_ISP6322 BIT_6
3783 #define DT_ISP2422 BIT_7
3784 #define DT_ISP2432 BIT_8
3785 #define DT_ISP5422 BIT_9
3786 #define DT_ISP5432 BIT_10
3787 #define DT_ISP2532 BIT_11
3788 #define DT_ISP8432 BIT_12
3789 #define DT_ISP8001 BIT_13
3790 #define DT_ISP8021 BIT_14
3791 #define DT_ISP2031 BIT_15
3792 #define DT_ISP8031 BIT_16
3793 #define DT_ISPFX00 BIT_17
3794 #define DT_ISP8044 BIT_18
3795 #define DT_ISP2071 BIT_19
3796 #define DT_ISP2271 BIT_20
3797 #define DT_ISP2261 BIT_21
3798 #define DT_ISP2061 BIT_22
3799 #define DT_ISP2081 BIT_23
3800 #define DT_ISP2089 BIT_24
3801 #define DT_ISP2281 BIT_25
3802 #define DT_ISP2289 BIT_26
3803 #define DT_ISP_LAST (DT_ISP2289 << 1)
3805 uint32_t device_type;
3806 #define DT_T10_PI BIT_25
3807 #define DT_IIDMA BIT_26
3808 #define DT_FWI2 BIT_27
3809 #define DT_ZIO_SUPPORTED BIT_28
3810 #define DT_OEM_001 BIT_29
3811 #define DT_ISP2200A BIT_30
3812 #define DT_EXTENDED_IDS BIT_31
3814 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3815 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3816 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3817 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3818 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3819 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3820 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3821 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3822 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3823 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3824 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3825 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3826 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3827 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3828 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3829 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3830 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3831 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3832 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3833 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3834 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3835 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3836 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3837 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3838 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
3839 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
3841 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3842 IS_QLA6312(ha) || IS_QLA6322(ha))
3843 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3844 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3845 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3846 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3847 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3848 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3849 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
3850 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3852 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3853 IS_QLA8031(ha) || IS_QLA8044(ha))
3854 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3855 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3856 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3857 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3858 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
3860 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3861 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3862 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3863 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3864 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3865 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3866 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3867 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3869 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3870 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3871 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3872 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3873 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3874 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3875 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3876 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3877 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3878 #define IS_BIDI_CAPABLE(ha) \
3879 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3880 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3881 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3882 ((ha)->fw_attributes_ext[0] & BIT_0))
3883 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3884 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3885 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3886 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3888 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3889 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3890 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3892 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3893 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
3894 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3896 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
3898 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
3899 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3900 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3901 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3902 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3903 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
3904 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3906 /* HBA serial number */
3911 /* NVRAM configuration data */
3912 #define MAX_NVRAM_SIZE 4096
3913 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
3914 uint16_t nvram_size;
3915 uint16_t nvram_base;
3921 uint16_t loop_reset_delay;
3922 uint8_t retry_count;
3923 uint8_t login_timeout;
3925 int port_down_retry_count;
3927 uint8_t aen_mbx_count;
3928 atomic_t num_pend_mbx_stage1;
3929 atomic_t num_pend_mbx_stage2;
3930 atomic_t num_pend_mbx_stage3;
3931 uint16_t frame_payload_size;
3933 uint32_t login_retry_count;
3934 /* SNS command interfaces. */
3935 ms_iocb_entry_t *ms_iocb;
3936 dma_addr_t ms_iocb_dma;
3937 struct ct_sns_pkt *ct_sns;
3938 dma_addr_t ct_sns_dma;
3939 /* SNS command interfaces for 2200. */
3940 struct sns_cmd_pkt *sns_cmd;
3941 dma_addr_t sns_cmd_dma;
3943 #define SFP_DEV_SIZE 512
3944 #define SFP_BLOCK_SIZE 64
3946 dma_addr_t sfp_data_dma;
3951 #define XGMAC_DATA_SIZE 4096
3953 dma_addr_t xgmac_data_dma;
3955 #define DCBX_TLV_DATA_SIZE 4096
3957 dma_addr_t dcbx_tlv_dma;
3959 struct task_struct *dpc_thread;
3960 uint8_t dpc_active; /* DPC routine is active */
3962 dma_addr_t gid_list_dma;
3963 struct gid_list_info *gid_list;
3964 int gid_list_info_size;
3966 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3967 #define DMA_POOL_SIZE 256
3968 struct dma_pool *s_dma_pool;
3970 dma_addr_t init_cb_dma;
3973 dma_addr_t ex_init_cb_dma;
3974 struct ex_init_cb_81xx *ex_init_cb;
3977 dma_addr_t async_pd_dma;
3979 #define ENABLE_EXTENDED_LOGIN BIT_7
3981 /* Extended Logins */
3983 dma_addr_t exlogin_buf_dma;
3986 #define ENABLE_EXCHANGE_OFFLD BIT_2
3988 /* Exchange Offload */
3989 void *exchoffld_buf;
3990 dma_addr_t exchoffld_buf_dma;
3992 int exchoffld_count;
3995 struct els_plogi_payload plogi_els_payld;
3999 /* These are used by mailbox operations. */
4000 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4001 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4002 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4005 struct mbx_cmd_32 *mcp32;
4007 unsigned long mbx_cmd_flags;
4008 #define MBX_INTERRUPT 1
4009 #define MBX_INTR_WAIT 2
4010 #define MBX_UPDATE_FLASH_ACTIVE 3
4012 struct mutex vport_lock; /* Virtual port synchronization */
4013 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
4014 struct mutex mq_lock; /* multi-queue synchronization */
4015 struct completion mbx_cmd_comp; /* Serialize mbx access */
4016 struct completion mbx_intr_comp; /* Used for completion notification */
4017 struct completion dcbx_comp; /* For set port config notification */
4018 struct completion lb_portup_comp; /* Used to wait for link up during
4020 #define DCBX_COMP_TIMEOUT 20
4021 #define LB_PORTUP_COMP_TIMEOUT 10
4023 int notify_dcbx_comp;
4024 int notify_lb_portup_comp;
4025 struct mutex selflogin_lock;
4027 /* Basic firmware related information. */
4028 uint16_t fw_major_version;
4029 uint16_t fw_minor_version;
4030 uint16_t fw_subminor_version;
4031 uint16_t fw_attributes;
4032 uint16_t fw_attributes_h;
4033 #define FW_ATTR_H_NVME_FBURST BIT_1
4034 #define FW_ATTR_H_NVME BIT_10
4035 #define FW_ATTR_H_NVME_UPDATED BIT_14
4037 uint16_t fw_attributes_ext[2];
4038 uint32_t fw_memory_size;
4039 uint32_t fw_transfer_size;
4040 uint32_t fw_srisc_address;
4041 #define RISC_START_ADDRESS_2100 0x1000
4042 #define RISC_START_ADDRESS_2300 0x800
4043 #define RISC_START_ADDRESS_2400 0x100000
4045 uint16_t orig_fw_tgt_xcb_count;
4046 uint16_t cur_fw_tgt_xcb_count;
4047 uint16_t orig_fw_xcb_count;
4048 uint16_t cur_fw_xcb_count;
4049 uint16_t orig_fw_iocb_count;
4050 uint16_t cur_fw_iocb_count;
4051 uint16_t fw_max_fcf_count;
4053 uint32_t fw_shared_ram_start;
4054 uint32_t fw_shared_ram_end;
4055 uint32_t fw_ddr_ram_start;
4056 uint32_t fw_ddr_ram_end;
4058 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
4059 uint8_t fw_seriallink_options[4];
4060 uint16_t fw_seriallink_options24[4];
4062 uint8_t serdes_version[3];
4063 uint8_t mpi_version[3];
4064 uint32_t mpi_capabilities;
4065 uint8_t phy_version[3];
4066 uint8_t pep_version[3];
4068 /* Firmware dump template */
4074 struct qla2xxx_fw_dump *fw_dump;
4075 uint32_t fw_dump_len;
4076 u32 fw_dump_alloc_len;
4079 unsigned long fw_dump_cap_flags;
4080 #define RISC_PAUSE_CMPL 0
4081 #define DMA_SHUTDOWN_CMPL 1
4082 #define ISP_RESET_CMPL 2
4083 #define RISC_RDY_AFT_RESET 3
4084 #define RISC_SRAM_DUMP_CMPL 4
4085 #define RISC_EXT_MEM_DUMP_CMPL 5
4086 #define ISP_MBX_RDY 6
4087 #define ISP_SOFT_RESET_CMPL 7
4088 int fw_dump_reading;
4089 int prev_minidump_failed;
4092 /* Current size of mctp dump is 0x086064 bytes */
4093 #define MCTP_DUMP_SIZE 0x086064
4094 dma_addr_t mctp_dump_dma;
4097 int mctp_dump_reading;
4098 uint32_t chain_offset;
4099 struct dentry *dfs_dir;
4100 struct dentry *dfs_fce;
4101 struct dentry *dfs_tgt_counters;
4102 struct dentry *dfs_fw_resource_cnt;
4108 uint64_t fce_wr, fce_rd;
4109 struct mutex fce_mutex;
4112 uint16_t chip_revision;
4114 uint16_t product_id[4];
4116 uint8_t model_number[16+1];
4117 char model_desc[80];
4118 uint8_t adapter_id[16+1];
4120 /* Option ROM information. */
4121 char *optrom_buffer;
4122 uint32_t optrom_size;
4124 #define QLA_SWAITING 0
4125 #define QLA_SREADING 1
4126 #define QLA_SWRITING 2
4127 uint32_t optrom_region_start;
4128 uint32_t optrom_region_size;
4129 struct mutex optrom_mutex;
4131 /* PCI expansion ROM image information. */
4132 #define ROM_CODE_TYPE_BIOS 0
4133 #define ROM_CODE_TYPE_FCODE 1
4134 #define ROM_CODE_TYPE_EFI 3
4135 uint8_t bios_revision[2];
4136 uint8_t efi_revision[2];
4137 uint8_t fcode_revision[16];
4138 uint32_t fw_revision[4];
4140 uint32_t gold_fw_version[4];
4142 /* Offsets for flash/nvram access (set to ~0 if not used). */
4143 uint32_t flash_conf_off;
4144 uint32_t flash_data_off;
4145 uint32_t nvram_conf_off;
4146 uint32_t nvram_data_off;
4148 uint32_t fdt_wrt_disable;
4149 uint32_t fdt_wrt_enable;
4150 uint32_t fdt_erase_cmd;
4151 uint32_t fdt_block_size;
4152 uint32_t fdt_unprotect_sec_cmd;
4153 uint32_t fdt_protect_sec_cmd;
4154 uint32_t fdt_wrt_sts_reg_cmd;
4157 uint32_t flt_region_flt;
4158 uint32_t flt_region_fdt;
4159 uint32_t flt_region_boot;
4160 uint32_t flt_region_boot_sec;
4161 uint32_t flt_region_fw;
4162 uint32_t flt_region_fw_sec;
4163 uint32_t flt_region_vpd_nvram;
4164 uint32_t flt_region_vpd_nvram_sec;
4165 uint32_t flt_region_vpd;
4166 uint32_t flt_region_vpd_sec;
4167 uint32_t flt_region_nvram;
4168 uint32_t flt_region_nvram_sec;
4169 uint32_t flt_region_npiv_conf;
4170 uint32_t flt_region_gold_fw;
4171 uint32_t flt_region_fcp_prio;
4172 uint32_t flt_region_bootload;
4173 uint32_t flt_region_img_status_pri;
4174 uint32_t flt_region_img_status_sec;
4175 uint32_t flt_region_aux_img_status_pri;
4176 uint32_t flt_region_aux_img_status_sec;
4178 uint8_t active_image;
4180 /* Needed for BEACON */
4181 uint16_t beacon_blink_led;
4182 uint8_t beacon_color_state;
4183 #define QLA_LED_GRN_ON 0x01
4184 #define QLA_LED_YLW_ON 0x02
4185 #define QLA_LED_ABR_ON 0x04
4186 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4187 /* ISP2322: red, green, amber. */
4191 struct qla_msix_entry *msix_entries;
4193 struct list_head vp_list; /* list of VP */
4194 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4195 sizeof(unsigned long)];
4196 uint16_t num_vhosts; /* number of vports created */
4197 uint16_t num_vsans; /* number of vsan created */
4198 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4199 int cur_vport_count;
4201 struct qla_chip_state_84xx *cs84xx;
4202 struct isp_operations *isp_ops;
4203 struct workqueue_struct *wq;
4204 struct qlfc_fw fw_buf;
4206 /* FCP_CMND priority support */
4207 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4209 struct dma_pool *dl_dma_pool;
4210 #define DSD_LIST_DMA_POOL_SIZE 512
4212 struct dma_pool *fcp_cmnd_dma_pool;
4213 mempool_t *ctx_mempool;
4214 #define FCP_CMND_DMA_POOL_SIZE 512
4216 void __iomem *nx_pcibase; /* Base I/O address */
4217 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4218 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
4221 uint32_t curr_window;
4222 uint32_t ddr_mn_window;
4223 unsigned long mn_win_crb;
4224 unsigned long ms_win_crb;
4226 uint32_t fcoe_dev_init_timeout;
4227 uint32_t fcoe_reset_timeout;
4229 uint16_t portnum; /* port number */
4231 struct fw_blob *hablob;
4232 struct qla82xx_legacy_intr_set nx_legacy_intr;
4234 uint16_t gbl_dsd_inuse;
4235 uint16_t gbl_dsd_avail;
4236 struct list_head gbl_dsd_list;
4237 #define NUM_DSD_CHAIN 4096
4240 __le32 file_prd_off; /* File firmware product offset */
4242 uint32_t md_template_size;
4244 dma_addr_t md_tmplt_hdr_dma;
4246 uint32_t md_dump_size;
4250 /* QLA83XX IDC specific fields */
4251 uint32_t idc_audit_ts;
4252 uint32_t idc_extend_tmo;
4254 /* DPC low-priority workqueue */
4255 struct workqueue_struct *dpc_lp_wq;
4256 struct work_struct idc_aen;
4257 /* DPC high-priority workqueue */
4258 struct workqueue_struct *dpc_hp_wq;
4259 struct work_struct nic_core_reset;
4260 struct work_struct idc_state_handler;
4261 struct work_struct nic_core_unrecoverable;
4262 struct work_struct board_disable;
4264 struct mr_data_fx00 mr;
4265 uint32_t chip_reset;
4267 struct qlt_hw_data tgt;
4268 int allow_cna_fw_dump;
4269 uint32_t fw_ability_mask;
4270 uint16_t min_supported_speed;
4271 uint16_t max_supported_speed;
4273 /* DMA pool for the DIF bundling buffers */
4274 struct dma_pool *dif_bundl_pool;
4275 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4278 struct list_head head;
4282 struct list_head head;
4287 unsigned long long dif_bundle_crossed_pages;
4288 unsigned long long dif_bundle_reads;
4289 unsigned long long dif_bundle_writes;
4290 unsigned long long dif_bundle_kallocs;
4291 unsigned long long dif_bundle_dma_allocs;
4293 atomic_t nvme_active_aen_cnt;
4294 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4296 atomic_t zio_threshold;
4297 uint16_t last_zio_threshold;
4299 #define DEFAULT_ZIO_THRESHOLD 5
4302 struct active_regions {
4305 uint8_t board_config;
4307 uint8_t npiv_config_0_1;
4308 uint8_t npiv_config_2_3;
4312 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4313 #define FW_ABILITY_MAX_SPEED_16G 0x0
4314 #define FW_ABILITY_MAX_SPEED_32G 0x1
4315 #define FW_ABILITY_MAX_SPEED(ha) \
4316 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4318 #define QLA_GET_DATA_RATE 0
4319 #define QLA_SET_DATA_RATE_NOLR 1
4320 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
4323 * Qlogic scsi host structure
4325 typedef struct scsi_qla_host {
4326 struct list_head list;
4327 struct list_head vp_fcports; /* list of fcports */
4328 struct list_head work_list;
4329 spinlock_t work_lock;
4330 struct work_struct iocb_work;
4332 /* Commonly used flags and state information. */
4333 struct Scsi_Host *host;
4334 unsigned long host_no;
4335 uint8_t host_str[16];
4338 uint32_t init_done :1;
4340 uint32_t reset_active :1;
4342 uint32_t management_server_logged_in :1;
4343 uint32_t process_response_queue :1;
4344 uint32_t difdix_supported:1;
4345 uint32_t delete_progress:1;
4347 uint32_t fw_tgt_reported:1;
4348 uint32_t bbcr_enable:1;
4349 uint32_t qpairs_available:1;
4350 uint32_t qpairs_req_created:1;
4351 uint32_t qpairs_rsp_created:1;
4352 uint32_t nvme_enabled:1;
4353 uint32_t nvme_first_burst:1;
4356 atomic_t loop_state;
4357 #define LOOP_TIMEOUT 1
4360 #define LOOP_UPDATE 4
4361 #define LOOP_READY 5
4364 unsigned long relogin_jif;
4365 unsigned long dpc_flags;
4366 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4367 #define RESET_ACTIVE 1
4368 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4369 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4370 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4371 #define LOOP_RESYNC_ACTIVE 5
4372 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4373 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4374 #define RELOGIN_NEEDED 8
4375 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4376 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4377 #define BEACON_BLINK_NEEDED 11
4378 #define REGISTER_FDMI_NEEDED 12
4379 #define FCPORT_UPDATE_NEEDED 13
4380 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4381 #define UNLOADING 15
4382 #define NPIV_CONFIG_NEEDED 16
4383 #define ISP_UNRECOVERABLE 17
4384 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4385 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4386 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4387 #define N2N_LINK_RESET 21
4388 #define PORT_UPDATE_NEEDED 22
4389 #define FX00_RESET_RECOVERY 23
4390 #define FX00_TARGET_SCAN 24
4391 #define FX00_CRITEMP_RECOVERY 25
4392 #define FX00_HOST_INFO_RESEND 26
4393 #define QPAIR_ONLINE_CHECK_NEEDED 27
4394 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28
4395 #define DETECT_SFP_CHANGE 29
4396 #define N2N_LOGIN_NEEDED 30
4397 #define IOCB_WORK_ACTIVE 31
4398 #define SET_ZIO_THRESHOLD_NEEDED 32
4399 #define ISP_ABORT_TO_ROM 33
4401 unsigned long pci_flags;
4402 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4403 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4404 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4406 uint32_t device_flags;
4407 #define SWITCH_FOUND BIT_0
4408 #define DFLG_NO_CABLE BIT_1
4409 #define DFLG_DEV_FAILED BIT_5
4411 /* ISP configuration data. */
4412 uint16_t loop_id; /* Host adapter loop id */
4413 uint16_t self_login_loop_id; /* host adapter loop id
4414 * get it on self login
4416 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4417 * no need of allocating it for
4421 port_id_t d_id; /* Host adapter port id */
4422 uint8_t marker_needed;
4423 uint16_t mgmt_svr_loop_id;
4427 /* Timeout timers. */
4428 uint8_t loop_down_abort_time; /* port down timer */
4429 atomic_t loop_down_timer; /* loop down timer */
4430 uint8_t link_down_timeout; /* link down timeout */
4432 uint32_t timer_active;
4433 struct timer_list timer;
4435 uint8_t node_name[WWN_SIZE];
4436 uint8_t port_name[WWN_SIZE];
4437 uint8_t fabric_node_name[WWN_SIZE];
4439 struct nvme_fc_local_port *nvme_local_port;
4440 struct completion nvme_del_done;
4442 uint16_t fcoe_vlan_id;
4443 uint16_t fcoe_fcf_idx;
4444 uint8_t fcoe_vn_port_mac[6];
4446 /* list of commands waiting on workqueue */
4447 struct list_head qla_cmd_list;
4448 struct list_head qla_sess_op_cmd_list;
4449 struct list_head unknown_atio_list;
4450 spinlock_t cmd_list_lock;
4451 struct delayed_work unknown_atio_work;
4453 /* Counter to detect races between ELS and RSCN events */
4454 atomic_t generation_tick;
4455 /* Time when global fcport update has been scheduled */
4456 int total_fcport_update_gen;
4457 /* List of pending LOGOs, protected by tgt_mutex */
4458 struct list_head logo_list;
4459 /* List of pending PLOGI acks, protected by hw lock */
4460 struct list_head plogi_ack_list;
4462 struct list_head qp_list;
4464 uint32_t vp_abort_cnt;
4466 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4467 uint16_t vp_idx; /* vport ID */
4468 struct qla_qpair *qpair; /* base qpair */
4470 unsigned long vp_flags;
4471 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4472 #define VP_CREATE_NEEDED 1
4473 #define VP_BIND_NEEDED 2
4474 #define VP_DELETE_NEEDED 3
4475 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4476 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4478 #define VP_OFFLINE 0
4481 // #define VP_DISABLE 3
4482 uint16_t vp_err_state;
4483 uint16_t vp_prev_err_state;
4484 #define VP_ERR_UNKWN 0
4485 #define VP_ERR_PORTDWN 1
4486 #define VP_ERR_FAB_UNSUPPORTED 2
4487 #define VP_ERR_FAB_NORESOURCES 3
4488 #define VP_ERR_FAB_LOGOUT 4
4489 #define VP_ERR_ADAP_NORESOURCES 5
4490 struct qla_hw_data *hw;
4491 struct scsi_qlt_host vha_tgt;
4492 struct req_que *req;
4493 int fw_heartbeat_counter;
4494 int seconds_since_last_heartbeat;
4495 struct fc_host_statistics fc_host_stat;
4496 struct qla_statistics qla_stats;
4497 struct bidi_statistics bidi_stats;
4498 atomic_t vref_count;
4499 struct qla8044_reset_template reset_tmplt;
4502 uint16_t u_ql2xexchoffld;
4503 uint16_t u_ql2xiniexchg;
4504 uint16_t qlini_mode;
4505 uint16_t ql2xexchoffld;
4506 uint16_t ql2xiniexchg;
4508 struct name_list_extended gnl;
4509 /* Count of active session/fcport */
4511 wait_queue_head_t fcport_waitQ;
4512 wait_queue_head_t vref_waitq;
4513 uint8_t min_supported_speed;
4514 uint8_t n2n_node_name[WWN_SIZE];
4515 uint8_t n2n_port_name[WWN_SIZE];
4517 struct list_head gpnid_list;
4518 struct fab_scan scan;
4520 unsigned int irq_offset;
4523 struct qla27xx_image_status {
4524 uint8_t image_status_mask;
4525 uint16_t generation;
4528 uint8_t bitmap; /* 28xx only */
4529 uint8_t reserved[2];
4534 /* 28xx aux image status bimap values */
4535 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
4536 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
4537 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
4538 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4540 #define SET_VP_IDX 1
4542 #define RESET_VP_IDX 3
4543 #define RESET_AL_PA 4
4544 struct qla_tgt_vp_map {
4546 scsi_qla_host_t *vha;
4550 dma_addr_t dma_addr; /* OUT */
4551 uint32_t dma_len; /* OUT */
4553 uint32_t tot_bytes; /* IN */
4554 struct scatterlist *cur_sg; /* IN */
4556 /* for book keeping, bzero on initial invocation */
4557 uint32_t bytes_consumed;
4559 uint32_t tot_partial;
4566 #define QLA_FW_STARTED(_ha) { \
4568 _ha->flags.fw_started = 1; \
4569 _ha->base_qpair->fw_started = 1; \
4570 for (i = 0; i < _ha->max_qpairs; i++) { \
4571 if (_ha->queue_pair_map[i]) \
4572 _ha->queue_pair_map[i]->fw_started = 1; \
4576 #define QLA_FW_STOPPED(_ha) { \
4578 _ha->flags.fw_started = 0; \
4579 _ha->base_qpair->fw_started = 0; \
4580 for (i = 0; i < _ha->max_qpairs; i++) { \
4581 if (_ha->queue_pair_map[i]) \
4582 _ha->queue_pair_map[i]->fw_started = 0; \
4587 #define SFUB_CHECKSUM_SIZE 4
4589 struct secure_flash_update_block {
4590 uint32_t block_info;
4591 uint32_t signature_lo;
4592 uint32_t signature_hi;
4593 uint32_t signature_upper[0x3e];
4596 struct secure_flash_update_block_pk {
4597 uint32_t block_info;
4598 uint32_t signature_lo;
4599 uint32_t signature_hi;
4600 uint32_t signature_upper[0x3e];
4601 uint32_t public_key[0x41];
4605 * Macros to help code, maintain, etc.
4607 #define LOOP_TRANSITION(ha) \
4608 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4609 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4610 atomic_read(&ha->loop_state) == LOOP_DOWN)
4612 #define STATE_TRANSITION(ha) \
4613 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4614 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4616 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4617 atomic_inc(&__vha->vref_count); \
4619 if (__vha->flags.delete_progress) { \
4620 atomic_dec(&__vha->vref_count); \
4621 wake_up(&__vha->vref_waitq); \
4628 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4629 atomic_dec(&__vha->vref_count); \
4630 wake_up(&__vha->vref_waitq); \
4633 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4634 atomic_inc(&__qpair->ref_count); \
4636 if (__qpair->delete_in_progress) { \
4637 atomic_dec(&__qpair->ref_count); \
4644 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4645 atomic_dec(&__qpair->ref_count); \
4648 #define QLA_ENA_CONF(_ha) {\
4650 _ha->base_qpair->enable_explicit_conf = 1; \
4651 for (i = 0; i < _ha->max_qpairs; i++) { \
4652 if (_ha->queue_pair_map[i]) \
4653 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4657 #define QLA_DIS_CONF(_ha) {\
4659 _ha->base_qpair->enable_explicit_conf = 0; \
4660 for (i = 0; i < _ha->max_qpairs; i++) { \
4661 if (_ha->queue_pair_map[i]) \
4662 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4667 * qla2x00 local function return status codes
4669 #define MBS_MASK 0x3fff
4671 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4672 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4673 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4674 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4675 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4676 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4677 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4678 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4679 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4680 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4682 #define QLA_FUNCTION_TIMEOUT 0x100
4683 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4684 #define QLA_FUNCTION_FAILED 0x102
4685 #define QLA_MEMORY_ALLOC_FAILED 0x103
4686 #define QLA_LOCK_TIMEOUT 0x104
4687 #define QLA_ABORTED 0x105
4688 #define QLA_SUSPENDED 0x106
4689 #define QLA_BUSY 0x107
4690 #define QLA_ALREADY_REGISTERED 0x109
4691 #define QLA_OS_TIMER_EXPIRED 0x10a
4693 #define NVRAM_DELAY() udelay(10)
4696 * Flash support definitions
4698 #define OPTROM_SIZE_2300 0x20000
4699 #define OPTROM_SIZE_2322 0x100000
4700 #define OPTROM_SIZE_24XX 0x100000
4701 #define OPTROM_SIZE_25XX 0x200000
4702 #define OPTROM_SIZE_81XX 0x400000
4703 #define OPTROM_SIZE_82XX 0x800000
4704 #define OPTROM_SIZE_83XX 0x1000000
4705 #define OPTROM_SIZE_28XX 0x2000000
4707 #define OPTROM_BURST_SIZE 0x1000
4708 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4710 #define QLA_DSDS_PER_IOCB 37
4712 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4714 #define QLA_SG_ALL 1024
4716 enum nexus_wait_type {
4722 /* Refer to SNIA SFF 8247 */
4723 struct sff_8247_a0 {
4724 u8 txid; /* transceiver id */
4727 /* compliance code */
4728 u8 eth_infi_cc3; /* ethernet, inifiband */
4732 #define FC_LL_VL BIT_7 /* very long */
4733 #define FC_LL_S BIT_6 /* Short */
4734 #define FC_LL_I BIT_5 /* Intermidiate*/
4735 #define FC_LL_L BIT_4 /* Long */
4736 #define FC_LL_M BIT_3 /* Medium */
4737 #define FC_LL_SA BIT_2 /* ShortWave laser */
4738 #define FC_LL_LC BIT_1 /* LongWave laser */
4739 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
4742 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
4743 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
4744 #define FC_TEC_SL BIT_5 /* short wave with OFC */
4745 #define FC_TEC_LL BIT_4 /* Longwave Laser */
4746 #define FC_TEC_ACT BIT_3 /* Active cable */
4747 #define FC_TEC_PAS BIT_2 /* Passive cable */
4749 /* Transmission Media */
4750 #define FC_MED_TW BIT_7 /* Twin Ax */
4751 #define FC_MED_TP BIT_6 /* Twited Pair */
4752 #define FC_MED_MI BIT_5 /* Min Coax */
4753 #define FC_MED_TV BIT_4 /* Video Coax */
4754 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
4755 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
4756 #define FC_MED_SM BIT_0 /* Single Mode */
4758 /* speed FC_SP_12: 12*100M = 1200 MB/s */
4759 #define FC_SP_12 BIT_7
4760 #define FC_SP_8 BIT_6
4761 #define FC_SP_16 BIT_5
4762 #define FC_SP_4 BIT_4
4763 #define FC_SP_32 BIT_3
4764 #define FC_SP_2 BIT_2
4765 #define FC_SP_1 BIT_0
4770 u8 length_km; /* offset 14/eh */
4776 #define SFF_VEN_NAME_LEN 16
4777 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
4780 #define SFF_PART_NAME_LEN 16
4781 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
4786 u8 options[2]; /* offset 64 */
4795 u8 vendor_specific[32];
4799 #define AUTO_DETECT_SFP_SUPPORT(_vha)\
4800 (ql2xautodetectsfp && !_vha->vp_idx && \
4801 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
4802 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw) || \
4803 IS_QLA28XX(_vha->hw)))
4805 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
4807 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4808 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
4810 #define SAVE_TOPO(_ha) { \
4811 if (_ha->current_topology) \
4812 _ha->prev_topology = _ha->current_topology; \
4815 #define N2N_TOPO(ha) \
4816 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
4817 ha->current_topology == ISP_CFG_N || \
4818 !ha->current_topology)
4820 #include "qla_target.h"
4821 #include "qla_gbl.h"
4822 #include "qla_dbg.h"
4823 #include "qla_inline.h"