drivers/pinctrl/sh-pfc/pfc-r8a77965.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A77965 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
   6  * Copyright (C) 2016 Renesas Electronics Corp.
   7  *
   8  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
   9  *
  10  * R-Car Gen3 processor support - PFC hardware block.
  11  *
  12  * Copyright (C) 2015  Renesas Electronics Corporation
  13  */
  14
  15 #include <linux/errno.h>
  16 #include <linux/kernel.h>
  17
  18 #include "core.h"
  19 #include "sh_pfc.h"
  20
  21 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  22                    SH_PFC_PIN_CFG_PULL_UP | \
  23                    SH_PFC_PIN_CFG_PULL_DOWN)
  24
  25 #define CPU_ALL_PORT(fn, sfx)                                           \
  26         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  27         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  30         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  31         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  34         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  35         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  36         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  37         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  38 /*
  39  * F_() : just information
  40  * FM() : macro for FN_xxx / xxx_MARK
  41  */
  42
  43 /* GPSR0 */
  44 #define GPSR0_15        F_(D15,                 IP7_11_8)
  45 #define GPSR0_14        F_(D14,                 IP7_7_4)
  46 #define GPSR0_13        F_(D13,                 IP7_3_0)
  47 #define GPSR0_12        F_(D12,                 IP6_31_28)
  48 #define GPSR0_11        F_(D11,                 IP6_27_24)
  49 #define GPSR0_10        F_(D10,                 IP6_23_20)
  50 #define GPSR0_9         F_(D9,                  IP6_19_16)
  51 #define GPSR0_8         F_(D8,                  IP6_15_12)
  52 #define GPSR0_7         F_(D7,                  IP6_11_8)
  53 #define GPSR0_6         F_(D6,                  IP6_7_4)
  54 #define GPSR0_5         F_(D5,                  IP6_3_0)
  55 #define GPSR0_4         F_(D4,                  IP5_31_28)
  56 #define GPSR0_3         F_(D3,                  IP5_27_24)
  57 #define GPSR0_2         F_(D2,                  IP5_23_20)
  58 #define GPSR0_1         F_(D1,                  IP5_19_16)
  59 #define GPSR0_0         F_(D0,                  IP5_15_12)
  60
  61 /* GPSR1 */
  62 #define GPSR1_28        FM(CLKOUT)
  63 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  64 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  65 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  66 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  67 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  68 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  69 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  70 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  71 #define GPSR1_19        F_(A19,                 IP4_11_8)
  72 #define GPSR1_18        F_(A18,                 IP4_7_4)
  73 #define GPSR1_17        F_(A17,                 IP4_3_0)
  74 #define GPSR1_16        F_(A16,                 IP3_31_28)
  75 #define GPSR1_15        F_(A15,                 IP3_27_24)
  76 #define GPSR1_14        F_(A14,                 IP3_23_20)
  77 #define GPSR1_13        F_(A13,                 IP3_19_16)
  78 #define GPSR1_12        F_(A12,                 IP3_15_12)
  79 #define GPSR1_11        F_(A11,                 IP3_11_8)
  80 #define GPSR1_10        F_(A10,                 IP3_7_4)
  81 #define GPSR1_9         F_(A9,                  IP3_3_0)
  82 #define GPSR1_8         F_(A8,                  IP2_31_28)
  83 #define GPSR1_7         F_(A7,                  IP2_27_24)
  84 #define GPSR1_6         F_(A6,                  IP2_23_20)
  85 #define GPSR1_5         F_(A5,                  IP2_19_16)
  86 #define GPSR1_4         F_(A4,                  IP2_15_12)
  87 #define GPSR1_3         F_(A3,                  IP2_11_8)
  88 #define GPSR1_2         F_(A2,                  IP2_7_4)
  89 #define GPSR1_1         F_(A1,                  IP2_3_0)
  90 #define GPSR1_0         F_(A0,                  IP1_31_28)
  91
  92 /* GPSR2 */
  93 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  94 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  95 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  96 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  97 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  98 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  99 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
 100 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 101 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 102 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 103 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 104 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 105 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 106 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 107 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 108
 109 /* GPSR3 */
 110 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 111 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 112 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 113 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 114 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 115 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 116 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 117 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 118 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 119 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 120 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 121 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 122 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 123 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 124 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 125 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 126
 127 /* GPSR4 */
 128 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 129 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 130 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 131 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 132 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 133 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 134 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 135 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 136 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 137 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 138 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 139 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 140 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 141 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 142 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 143 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 144 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 145 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 146
 147 /* GPSR5 */
 148 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 149 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 150 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 151 #define GPSR5_22        FM(MSIOF0_RXD)
 152 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 153 #define GPSR5_20        FM(MSIOF0_TXD)
 154 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 155 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 156 #define GPSR5_17        FM(MSIOF0_SCK)
 157 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 158 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 159 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 160 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 161 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 162 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 163 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 164 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 165 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 166 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 167 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 168 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 169 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 170 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 171 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 172 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 173 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 174
 175 /* GPSR6 */
 176 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 177 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 178 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 179 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 180 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 181 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 182 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 183 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 184 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 185 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 186 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 187 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 188 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 189 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 190 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 191 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 192 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 193 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 194 #define GPSR6_13        FM(SSI_SDATA5)
 195 #define GPSR6_12        FM(SSI_WS5)
 196 #define GPSR6_11        FM(SSI_SCK5)
 197 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 198 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 199 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 200 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 201 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 202 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 203 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 204 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 205 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 206 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 207 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 208
 209 /* GPSR7 */
 210 #define GPSR7_3         FM(GP7_03)
 211 #define GPSR7_2         FM(GP7_02)
 212 #define GPSR7_1         FM(AVS2)
 213 #define GPSR7_0         FM(AVS1)
 214
 215
 216 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 217 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        FM(FSCLKST2_N_A) F_(0, 0)               F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)               FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244
 245 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 246 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275
 276 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 277 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311
 312 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 313 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 334 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341
 342 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 343 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 363 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 364 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 365 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 366 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 367 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 368 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 369 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 370
 371 #define PINMUX_GPSR     \
 372 \
 373                                                                                                 GPSR6_31 \
 374                                                                                                 GPSR6_30 \
 375                                                                                                 GPSR6_29 \
 376                 GPSR1_28                                                                        GPSR6_28 \
 377                 GPSR1_27                                                                        GPSR6_27 \
 378                 GPSR1_26                                                                        GPSR6_26 \
 379                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 380                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 381                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 382                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 383                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 384                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 385                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 386                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 387                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 388                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 389 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 390 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 391 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 392 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 393 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 394 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 395 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 396 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 397 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 398 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 399 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 400 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 401 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 402 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 403 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 404 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 405
 406 #define PINMUX_IPSR                             \
 407 \
 408 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 409 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 410 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 411 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 412 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 413 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 414 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 415 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 416 \
 417 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 418 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 419 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 420 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 421 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 422 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 423 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 424 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 425 \
 426 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 427 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 428 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 429 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 430 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 431 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 432 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 433 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 434 \
 435 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 436 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 437 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 438 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 439 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 440 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 441 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 442 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 443 \
 444 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 445 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 446 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 447 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 448 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 449 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 450 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 451 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 452
 453 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 454 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 455 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 456 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 457 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 458 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 459 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 460 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 461 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 462 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 463 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 464 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 465 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 466 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 467 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 468 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 469 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 470 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 471 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 472
 473 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 474 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 475 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 476 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 477 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 478 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 479 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 480 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 481 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 482 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 483 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 484 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 485 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 486 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 487 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 488 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 489 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 490 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 491 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 492 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 493 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 494 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 495 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 496
 497 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 498 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 499 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 500 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 501 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 502 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 503 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 504 #define MOD_SEL2_22             FM(SEL_NDFC_0)          FM(SEL_NDFC_1)
 505 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 506 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 507 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 508 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 509 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 510 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 511
 512 #define PINMUX_MOD_SELS \
 513 \
 514 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 515                                                 MOD_SEL2_30 \
 516                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 517 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 518 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 519                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 520 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 521 MOD_SEL0_22                                     MOD_SEL2_22 \
 522 MOD_SEL0_21                                     MOD_SEL2_21 \
 523 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 524 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 525 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 526                                                 MOD_SEL2_17 \
 527 MOD_SEL0_16             MOD_SEL1_16 \
 528                         MOD_SEL1_15_14 \
 529 MOD_SEL0_14_13 \
 530                         MOD_SEL1_13 \
 531 MOD_SEL0_12             MOD_SEL1_12 \
 532 MOD_SEL0_11             MOD_SEL1_11 \
 533 MOD_SEL0_10             MOD_SEL1_10 \
 534 MOD_SEL0_9_8            MOD_SEL1_9 \
 535 MOD_SEL0_7_6 \
 536                         MOD_SEL1_6 \
 537 MOD_SEL0_5              MOD_SEL1_5 \
 538 MOD_SEL0_4_3            MOD_SEL1_4 \
 539                         MOD_SEL1_3 \
 540                         MOD_SEL1_2 \
 541                         MOD_SEL1_1 \
 542                         MOD_SEL1_0              MOD_SEL2_0
 543
 544 /*
 545  * These pins are not able to be muxed but have other properties
 546  * that can be set, such as drive-strength or pull-up/pull-down enable.
 547  */
 548 #define PINMUX_STATIC \
 549         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 550         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 551         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 552         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 553         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 554         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 555         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 556         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 557         FM(PRESETOUT) \
 558         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
 559         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 560
 561 enum {
 562         PINMUX_RESERVED = 0,
 563
 564         PINMUX_DATA_BEGIN,
 565         GP_ALL(DATA),
 566         PINMUX_DATA_END,
 567
 568 #define F_(x, y)
 569 #define FM(x)   FN_##x,
 570         PINMUX_FUNCTION_BEGIN,
 571         GP_ALL(FN),
 572         PINMUX_GPSR
 573         PINMUX_IPSR
 574         PINMUX_MOD_SELS
 575         PINMUX_FUNCTION_END,
 576 #undef F_
 577 #undef FM
 578
 579 #define F_(x, y)
 580 #define FM(x)   x##_MARK,
 581         PINMUX_MARK_BEGIN,
 582         PINMUX_GPSR
 583         PINMUX_IPSR
 584         PINMUX_MOD_SELS
 585         PINMUX_STATIC
 586         PINMUX_MARK_END,
 587 #undef F_
 588 #undef FM
 589 };
 590
 591 static const u16 pinmux_data[] = {
 592         PINMUX_DATA_GP_ALL(),
 593
 594         PINMUX_SINGLE(AVS1),
 595         PINMUX_SINGLE(AVS2),
 596         PINMUX_SINGLE(CLKOUT),
 597         PINMUX_SINGLE(GP7_03),
 598         PINMUX_SINGLE(GP7_02),
 599         PINMUX_SINGLE(MSIOF0_RXD),
 600         PINMUX_SINGLE(MSIOF0_SCK),
 601         PINMUX_SINGLE(MSIOF0_TXD),
 602         PINMUX_SINGLE(SSI_SCK5),
 603         PINMUX_SINGLE(SSI_SDATA5),
 604         PINMUX_SINGLE(SSI_WS5),
 605
 606         /* IPSR0 */
 607         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 608         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 609
 610         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 611         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 612         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 613
 614         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 615         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 616         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 617
 618         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 619         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 620         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 621         PINMUX_IPSR_GPSR(IP0_19_16,     FSCLKST2_N_A),
 622
 623         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 624         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 625         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 626
 627         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 628         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 629         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_A,               SEL_SCIF4_0),
 630
 631         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 632         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 633         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 634         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 635         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 636         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 637         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 638
 639         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 640         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 641         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 642         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 643         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 644         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 645         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 646
 647         /* IPSR1 */
 648         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 649         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 650         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 651         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 652         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 653         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 654
 655         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 656         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 657         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 658         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 659         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 660         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 661
 662         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 663         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 664         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 665         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 666         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 667         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 668
 669         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 670         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 671         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 672         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 673         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 674         PINMUX_IPSR_GPSR(IP1_15_12,     FSCLKST2_N_B),
 675         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 676
 677         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 678         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 679         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 680         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 681
 682         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 683         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 684         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 685         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 686
 687         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 688         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 689         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 690
 691         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 692         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 693         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 694         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 695         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 696         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 697
 698         /* IPSR2 */
 699         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 700         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 701         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 702         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 703         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 704         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 705
 706         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 707         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 708         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 709         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 710         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 711         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 712
 713         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 714         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 715         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 716         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 717         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 718         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 719
 720         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 721         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 722         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 723         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 724         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 725         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 726
 727         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 728         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 729         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 730         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 731         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 732         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 733         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 734
 735         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 736         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 737         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 738         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 739         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 740         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 741         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 742
 743         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 744         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 745         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 746         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 747         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 748         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 749         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 750
 751         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 752         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 753         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 754         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 755         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 756         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 757         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 758
 759         /* IPSR3 */
 760         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 761         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 762         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 763         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 764
 765         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 766         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 767         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 768         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 769
 770         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 771         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 772         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 773         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 774         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 775         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 776         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 777         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 778         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 779
 780         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 781         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 782         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 783         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 784         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 785         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 786
 787         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 788         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 789         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 790         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 791         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 792         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 793
 794         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 795         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 796         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 797         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 798         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 799         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 800
 801         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 802         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 803         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 804         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 805         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 806         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 807
 808         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 809         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 810         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 811         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 812
 813         /* IPSR4 */
 814         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 815         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 816         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 817         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 818
 819         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 820         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 821         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 822         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 823
 824         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 825         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 826         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 827         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 828
 829         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 830         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 831
 832         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 833         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 834         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 835
 836         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 837         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 838         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 839         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 840         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 841         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 842         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 843         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 844
 845         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 846         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 847         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 848         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 849         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 850         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 851
 852         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 853         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 854         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 855         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 856         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 857         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 858
 859         /* IPSR5 */
 860         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 861         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 862         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 863         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 864         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 865         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 866         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 867
 868         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 869         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 870         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 871         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 872         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 873         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 874         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 875         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 876
 877         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 878         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 879         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 880         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 881
 882         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 883         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 884         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 885         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 886         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 887
 888         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 889         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 890         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 891         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 892         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 893
 894         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 895         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 896         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 897         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 898
 899         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 900         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 901         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 902         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 903
 904         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 905         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 906         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 907         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 908
 909         /* IPSR6 */
 910         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 911         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 912         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 913         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 914
 915         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 916         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 917         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 918         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 919
 920         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 921         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 922         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 923         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 924
 925         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 926         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 927         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 928         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 929         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 930         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 931
 932         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 933         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 934         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 935         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 936         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 937
 938         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 939         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 940         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 941         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 942         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 943         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 944         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 945
 946         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 947         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 948         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 949         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 950         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 951         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 952         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 953
 954         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 955         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 956         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 957         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 958         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 959         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 960
 961         /* IPSR7 */
 962         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 963         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 964         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 965         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 966         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 967         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 968
 969         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 970         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 971         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 972         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 973         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 974         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 975         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 976
 977         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 978         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 979         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 980         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 981         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 982         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 983         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 984
 985         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 986         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 987         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 988
 989         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 990         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 991         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 992
 993         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 994         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 995         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 996         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 997
 998         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 999         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
1000         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1001         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1002
1003         /* IPSR8 */
1004         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1005         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1006         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1007         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1008
1009         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1010         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1011         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1012         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1013
1014         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1015         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1016         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1017
1018         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1019         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1020         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDFC_1),
1021         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1022         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1023
1024         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1025         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1026         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1027         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDFC_1),
1028         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1029         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1030
1031         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1032         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1033         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1034         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDFC_1),
1035         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1036         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1037
1038         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1039         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1040         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1041         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDFC_1),
1042         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1043         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1044
1045         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1046         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1047         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1048         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDFC_1),
1049         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1050         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1051
1052         /* IPSR9 */
1053         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1054         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1055
1056         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1057         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1058
1059         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1060         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1061
1062         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1063         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1064
1065         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1066         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1067
1068         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1069         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1070
1071         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1072         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1073         PINMUX_IPSR_GPSR(IP9_27_24,     SATA_DEVSLP_B),
1074
1075         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1076         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1077
1078         /* IPSR10 */
1079         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1080         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1081
1082         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1083         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1084
1085         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1086         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1087
1088         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1089         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1090
1091         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1092         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1093
1094         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1095         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1096         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1097
1098         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1099         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1100         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1101
1102         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1103         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1104         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1105
1106         /* IPSR11 */
1107         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1108         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1109         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1110
1111         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1112         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1113
1114         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1115         PINMUX_IPSR_MSEL(IP11_11_8,     NFDATA14_A,             SEL_NDFC_0),
1116         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1117         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1118
1119         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1120         PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,             SEL_NDFC_0),
1121         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1122
1123         PINMUX_IPSR_GPSR(IP11_19_16,    SD1_CD),
1124         PINMUX_IPSR_MSEL(IP11_19_16,    NFRB_N_A,               SEL_NDFC_0),
1125         PINMUX_IPSR_MSEL(IP11_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1126
1127         PINMUX_IPSR_GPSR(IP11_23_20,    SD1_WP),
1128         PINMUX_IPSR_MSEL(IP11_23_20,    NFCE_N_A,               SEL_NDFC_0),
1129         PINMUX_IPSR_MSEL(IP11_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1130
1131         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1132         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1133         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1134         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1135         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1136         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1137         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1138         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1139         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1140         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1141
1142         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1143         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1144         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1145         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1146         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1147
1148         /* IPSR12 */
1149         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1150         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1151         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1152         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1153         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1154
1155         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1156         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1157         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1158         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1159         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1160         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1161         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1162         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1163
1164         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1165         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1166         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1167         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1168         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1169         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1170         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1171         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1172
1173         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1174         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1175         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1176         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1177         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1178
1179         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1180         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1181         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1182         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1183         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1184
1185         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1186         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1187         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1188         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1189         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1190         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1191         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1192
1193         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1194         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1195         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1196         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1197         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1198         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1199         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1200
1201         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1202         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1203         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1204         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1205         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1206         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1207         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1208
1209         /* IPSR13 */
1210         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1211         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1212         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1213         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1214         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1215         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1216
1217         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1218         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1219         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1220         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1221         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1222         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1223
1224         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1225         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1226         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1227         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1228         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1229         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1230         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1231         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1232
1233         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1234         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1235         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1237         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1238         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1239
1240         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1241         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1242         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1243         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1244         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1245         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1246
1247         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1248         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1249         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1250         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1251         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1252         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1253         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1254         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1255
1256         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1257         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1258         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1259         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1260         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1261         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1262         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1263
1264         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1265         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1266         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1267         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1268
1269         /* IPSR14 */
1270         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1271         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1272         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDFC_0),
1273         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1274         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1275         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1276         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1277         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1278
1279         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1280         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1281         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1282         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1283         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1284         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1285         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1286         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1287
1288         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1289         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1290         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1291
1292         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1293         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1294         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1295         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1296
1297         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1298         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1299         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1300
1301         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1302         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1303
1304         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1305         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1306
1307         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1308         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1309
1310         /* IPSR15 */
1311         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1312
1313         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1314         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1315
1316         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1317         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1318         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1319
1320         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1321         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1322         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1323         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1324
1325         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1328         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1329         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1330         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1331         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1332
1333         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1337         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1338         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1339         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1340
1341         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1342         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1345         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1346         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1347         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1348
1349         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1350         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1351         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1353         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1354         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1355         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1356
1357         /* IPSR16 */
1358         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1359         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1360
1361         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1362         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1363
1364         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1365         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1366         PINMUX_IPSR_GPSR(IP16_11_8,     SATA_DEVSLP_A),
1367
1368         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1369         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1370         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1371         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1372         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1373         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1374         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1375
1376         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1377         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1378         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1382         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1383
1384         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1385         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1386         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1387         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1391         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1392
1393         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1394         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1395         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1396         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1399         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1400
1401         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1402         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1403         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1404         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1405         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1406         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1408         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1409
1410         /* IPSR17 */
1411         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1412
1413         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1414         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1415         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1416         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1417         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1418
1419         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1420         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1421         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1422         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1423         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1424         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1425         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1426
1427         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1428         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1429         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1430         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1431         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1432         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1433
1434         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1435         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1436         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1437         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1438         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1439         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1440         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1441         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1442         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1443
1444         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1445         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1446         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1447         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1448         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1449         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1450         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1451         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1452         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1453
1454         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1455         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1456         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1457         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1458         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1459         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1460         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1461         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1462         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1463         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1464         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1465
1466         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1467         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1468         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1469         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1470         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1471         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1472         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1473         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1474         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1475
1476         /* IPSR18 */
1477         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1478         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1479         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1480         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1481         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1482         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1483         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1484         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1485         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1486
1487         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1488         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1489         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1490         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1491         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1492         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1493         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1494         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1495         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1496
1497         /* I2C */
1498         PINMUX_IPSR_NOGP(0,             I2C_SEL_0_1),
1499         PINMUX_IPSR_NOGP(0,             I2C_SEL_3_1),
1500         PINMUX_IPSR_NOGP(0,             I2C_SEL_5_1),
1501
1502 /*
1503  * Static pins can not be muxed between different functions but
1504  * still need mark entries in the pinmux list. Add each static
1505  * pin to the list without an associated function. The sh-pfc
1506  * core will do the right thing and skip trying to mux the pin
1507  * while still applying configuration to it.
1508  */
1509 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1510         PINMUX_STATIC
1511 #undef FM
1512 };
1513
1514 /*
1515  * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516  * Physical layout rows: A - AW, cols: 1 - 39.
1517  */
1518 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521 #define PIN_NONE U16_MAX
1522
1523 static const struct sh_pfc_pin pinmux_pins[] = {
1524         PINMUX_GPIO_GP_ALL(),
1525
1526         /*
1527          * Pins not associated with a GPIO port.
1528          *
1529          * The pin positions are different between different r8a77965
1530          * packages, all that is needed for the pfc driver is a unique
1531          * number for each pin. To this end use the pin layout from
1532          * R-Car M3SiP to calculate a unique number for each pin.
1533          */
1534         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1535         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1536         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576 };
1577
1578 /* - AUDIO CLOCK ------------------------------------------------------------ */
1579 static const unsigned int audio_clk_a_a_pins[] = {
1580         /* CLK A */
1581         RCAR_GP_PIN(6, 22),
1582 };
1583 static const unsigned int audio_clk_a_a_mux[] = {
1584         AUDIO_CLKA_A_MARK,
1585 };
1586 static const unsigned int audio_clk_a_b_pins[] = {
1587         /* CLK A */
1588         RCAR_GP_PIN(5, 4),
1589 };
1590 static const unsigned int audio_clk_a_b_mux[] = {
1591         AUDIO_CLKA_B_MARK,
1592 };
1593 static const unsigned int audio_clk_a_c_pins[] = {
1594         /* CLK A */
1595         RCAR_GP_PIN(5, 19),
1596 };
1597 static const unsigned int audio_clk_a_c_mux[] = {
1598         AUDIO_CLKA_C_MARK,
1599 };
1600 static const unsigned int audio_clk_b_a_pins[] = {
1601         /* CLK B */
1602         RCAR_GP_PIN(5, 12),
1603 };
1604 static const unsigned int audio_clk_b_a_mux[] = {
1605         AUDIO_CLKB_A_MARK,
1606 };
1607 static const unsigned int audio_clk_b_b_pins[] = {
1608         /* CLK B */
1609         RCAR_GP_PIN(6, 23),
1610 };
1611 static const unsigned int audio_clk_b_b_mux[] = {
1612         AUDIO_CLKB_B_MARK,
1613 };
1614 static const unsigned int audio_clk_c_a_pins[] = {
1615         /* CLK C */
1616         RCAR_GP_PIN(5, 21),
1617 };
1618 static const unsigned int audio_clk_c_a_mux[] = {
1619         AUDIO_CLKC_A_MARK,
1620 };
1621 static const unsigned int audio_clk_c_b_pins[] = {
1622         /* CLK C */
1623         RCAR_GP_PIN(5, 0),
1624 };
1625 static const unsigned int audio_clk_c_b_mux[] = {
1626         AUDIO_CLKC_B_MARK,
1627 };
1628 static const unsigned int audio_clkout_a_pins[] = {
1629         /* CLKOUT */
1630         RCAR_GP_PIN(5, 18),
1631 };
1632 static const unsigned int audio_clkout_a_mux[] = {
1633         AUDIO_CLKOUT_A_MARK,
1634 };
1635 static const unsigned int audio_clkout_b_pins[] = {
1636         /* CLKOUT */
1637         RCAR_GP_PIN(6, 28),
1638 };
1639 static const unsigned int audio_clkout_b_mux[] = {
1640         AUDIO_CLKOUT_B_MARK,
1641 };
1642 static const unsigned int audio_clkout_c_pins[] = {
1643         /* CLKOUT */
1644         RCAR_GP_PIN(5, 3),
1645 };
1646 static const unsigned int audio_clkout_c_mux[] = {
1647         AUDIO_CLKOUT_C_MARK,
1648 };
1649 static const unsigned int audio_clkout_d_pins[] = {
1650         /* CLKOUT */
1651         RCAR_GP_PIN(5, 21),
1652 };
1653 static const unsigned int audio_clkout_d_mux[] = {
1654         AUDIO_CLKOUT_D_MARK,
1655 };
1656 static const unsigned int audio_clkout1_a_pins[] = {
1657         /* CLKOUT1 */
1658         RCAR_GP_PIN(5, 15),
1659 };
1660 static const unsigned int audio_clkout1_a_mux[] = {
1661         AUDIO_CLKOUT1_A_MARK,
1662 };
1663 static const unsigned int audio_clkout1_b_pins[] = {
1664         /* CLKOUT1 */
1665         RCAR_GP_PIN(6, 29),
1666 };
1667 static const unsigned int audio_clkout1_b_mux[] = {
1668         AUDIO_CLKOUT1_B_MARK,
1669 };
1670 static const unsigned int audio_clkout2_a_pins[] = {
1671         /* CLKOUT2 */
1672         RCAR_GP_PIN(5, 16),
1673 };
1674 static const unsigned int audio_clkout2_a_mux[] = {
1675         AUDIO_CLKOUT2_A_MARK,
1676 };
1677 static const unsigned int audio_clkout2_b_pins[] = {
1678         /* CLKOUT2 */
1679         RCAR_GP_PIN(6, 30),
1680 };
1681 static const unsigned int audio_clkout2_b_mux[] = {
1682         AUDIO_CLKOUT2_B_MARK,
1683 };
1684
1685 static const unsigned int audio_clkout3_a_pins[] = {
1686         /* CLKOUT3 */
1687         RCAR_GP_PIN(5, 19),
1688 };
1689 static const unsigned int audio_clkout3_a_mux[] = {
1690         AUDIO_CLKOUT3_A_MARK,
1691 };
1692 static const unsigned int audio_clkout3_b_pins[] = {
1693         /* CLKOUT3 */
1694         RCAR_GP_PIN(6, 31),
1695 };
1696 static const unsigned int audio_clkout3_b_mux[] = {
1697         AUDIO_CLKOUT3_B_MARK,
1698 };
1699
1700 /* - EtherAVB --------------------------------------------------------------- */
1701 static const unsigned int avb_link_pins[] = {
1702         /* AVB_LINK */
1703         RCAR_GP_PIN(2, 12),
1704 };
1705 static const unsigned int avb_link_mux[] = {
1706         AVB_LINK_MARK,
1707 };
1708 static const unsigned int avb_magic_pins[] = {
1709         /* AVB_MAGIC_ */
1710         RCAR_GP_PIN(2, 10),
1711 };
1712 static const unsigned int avb_magic_mux[] = {
1713         AVB_MAGIC_MARK,
1714 };
1715 static const unsigned int avb_phy_int_pins[] = {
1716         /* AVB_PHY_INT */
1717         RCAR_GP_PIN(2, 11),
1718 };
1719 static const unsigned int avb_phy_int_mux[] = {
1720         AVB_PHY_INT_MARK,
1721 };
1722 static const unsigned int avb_mdio_pins[] = {
1723         /* AVB_MDC, AVB_MDIO */
1724         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1725 };
1726 static const unsigned int avb_mdio_mux[] = {
1727         AVB_MDC_MARK, AVB_MDIO_MARK,
1728 };
1729 static const unsigned int avb_mii_pins[] = {
1730         /*
1731          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1732          * AVB_TD1, AVB_TD2, AVB_TD3,
1733          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1734          * AVB_RD1, AVB_RD2, AVB_RD3,
1735          * AVB_TXCREFCLK
1736          */
1737         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1738         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1739         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1740         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1741         PIN_NUMBER('A', 12),
1742
1743 };
1744 static const unsigned int avb_mii_mux[] = {
1745         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1746         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1747         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1748         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1749         AVB_TXCREFCLK_MARK,
1750 };
1751 static const unsigned int avb_avtp_pps_pins[] = {
1752         /* AVB_AVTP_PPS */
1753         RCAR_GP_PIN(2, 6),
1754 };
1755 static const unsigned int avb_avtp_pps_mux[] = {
1756         AVB_AVTP_PPS_MARK,
1757 };
1758 static const unsigned int avb_avtp_match_a_pins[] = {
1759         /* AVB_AVTP_MATCH_A */
1760         RCAR_GP_PIN(2, 13),
1761 };
1762 static const unsigned int avb_avtp_match_a_mux[] = {
1763         AVB_AVTP_MATCH_A_MARK,
1764 };
1765 static const unsigned int avb_avtp_capture_a_pins[] = {
1766         /* AVB_AVTP_CAPTURE_A */
1767         RCAR_GP_PIN(2, 14),
1768 };
1769 static const unsigned int avb_avtp_capture_a_mux[] = {
1770         AVB_AVTP_CAPTURE_A_MARK,
1771 };
1772 static const unsigned int avb_avtp_match_b_pins[] = {
1773         /*  AVB_AVTP_MATCH_B */
1774         RCAR_GP_PIN(1, 8),
1775 };
1776 static const unsigned int avb_avtp_match_b_mux[] = {
1777         AVB_AVTP_MATCH_B_MARK,
1778 };
1779 static const unsigned int avb_avtp_capture_b_pins[] = {
1780         /* AVB_AVTP_CAPTURE_B */
1781         RCAR_GP_PIN(1, 11),
1782 };
1783 static const unsigned int avb_avtp_capture_b_mux[] = {
1784         AVB_AVTP_CAPTURE_B_MARK,
1785 };
1786
1787 /* - CAN ------------------------------------------------------------------ */
1788 static const unsigned int can0_data_a_pins[] = {
1789         /* TX, RX */
1790         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1791 };
1792
1793 static const unsigned int can0_data_a_mux[] = {
1794         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1795 };
1796
1797 static const unsigned int can0_data_b_pins[] = {
1798         /* TX, RX */
1799         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1800 };
1801
1802 static const unsigned int can0_data_b_mux[] = {
1803         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1804 };
1805
1806 static const unsigned int can1_data_pins[] = {
1807         /* TX, RX */
1808         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1809 };
1810
1811 static const unsigned int can1_data_mux[] = {
1812         CAN1_TX_MARK,           CAN1_RX_MARK,
1813 };
1814
1815 /* - CAN Clock -------------------------------------------------------------- */
1816 static const unsigned int can_clk_pins[] = {
1817         /* CLK */
1818         RCAR_GP_PIN(1, 25),
1819 };
1820
1821 static const unsigned int can_clk_mux[] = {
1822         CAN_CLK_MARK,
1823 };
1824
1825 /* - CAN FD --------------------------------------------------------------- */
1826 static const unsigned int canfd0_data_a_pins[] = {
1827         /* TX, RX */
1828         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1829 };
1830
1831 static const unsigned int canfd0_data_a_mux[] = {
1832         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1833 };
1834
1835 static const unsigned int canfd0_data_b_pins[] = {
1836         /* TX, RX */
1837         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1838 };
1839
1840 static const unsigned int canfd0_data_b_mux[] = {
1841         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1842 };
1843
1844 static const unsigned int canfd1_data_pins[] = {
1845         /* TX, RX */
1846         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1847 };
1848
1849 static const unsigned int canfd1_data_mux[] = {
1850         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1851 };
1852
1853 /* - DRIF0 --------------------------------------------------------------- */
1854 static const unsigned int drif0_ctrl_a_pins[] = {
1855         /* CLK, SYNC */
1856         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1857 };
1858
1859 static const unsigned int drif0_ctrl_a_mux[] = {
1860         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1861 };
1862
1863 static const unsigned int drif0_data0_a_pins[] = {
1864         /* D0 */
1865         RCAR_GP_PIN(6, 10),
1866 };
1867
1868 static const unsigned int drif0_data0_a_mux[] = {
1869         RIF0_D0_A_MARK,
1870 };
1871
1872 static const unsigned int drif0_data1_a_pins[] = {
1873         /* D1 */
1874         RCAR_GP_PIN(6, 7),
1875 };
1876
1877 static const unsigned int drif0_data1_a_mux[] = {
1878         RIF0_D1_A_MARK,
1879 };
1880
1881 static const unsigned int drif0_ctrl_b_pins[] = {
1882         /* CLK, SYNC */
1883         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1884 };
1885
1886 static const unsigned int drif0_ctrl_b_mux[] = {
1887         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1888 };
1889
1890 static const unsigned int drif0_data0_b_pins[] = {
1891         /* D0 */
1892         RCAR_GP_PIN(5, 1),
1893 };
1894
1895 static const unsigned int drif0_data0_b_mux[] = {
1896         RIF0_D0_B_MARK,
1897 };
1898
1899 static const unsigned int drif0_data1_b_pins[] = {
1900         /* D1 */
1901         RCAR_GP_PIN(5, 2),
1902 };
1903
1904 static const unsigned int drif0_data1_b_mux[] = {
1905         RIF0_D1_B_MARK,
1906 };
1907
1908 static const unsigned int drif0_ctrl_c_pins[] = {
1909         /* CLK, SYNC */
1910         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1911 };
1912
1913 static const unsigned int drif0_ctrl_c_mux[] = {
1914         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1915 };
1916
1917 static const unsigned int drif0_data0_c_pins[] = {
1918         /* D0 */
1919         RCAR_GP_PIN(5, 13),
1920 };
1921
1922 static const unsigned int drif0_data0_c_mux[] = {
1923         RIF0_D0_C_MARK,
1924 };
1925
1926 static const unsigned int drif0_data1_c_pins[] = {
1927         /* D1 */
1928         RCAR_GP_PIN(5, 14),
1929 };
1930
1931 static const unsigned int drif0_data1_c_mux[] = {
1932         RIF0_D1_C_MARK,
1933 };
1934
1935 /* - DRIF1 --------------------------------------------------------------- */
1936 static const unsigned int drif1_ctrl_a_pins[] = {
1937         /* CLK, SYNC */
1938         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1939 };
1940
1941 static const unsigned int drif1_ctrl_a_mux[] = {
1942         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1943 };
1944
1945 static const unsigned int drif1_data0_a_pins[] = {
1946         /* D0 */
1947         RCAR_GP_PIN(6, 19),
1948 };
1949
1950 static const unsigned int drif1_data0_a_mux[] = {
1951         RIF1_D0_A_MARK,
1952 };
1953
1954 static const unsigned int drif1_data1_a_pins[] = {
1955         /* D1 */
1956         RCAR_GP_PIN(6, 20),
1957 };
1958
1959 static const unsigned int drif1_data1_a_mux[] = {
1960         RIF1_D1_A_MARK,
1961 };
1962
1963 static const unsigned int drif1_ctrl_b_pins[] = {
1964         /* CLK, SYNC */
1965         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1966 };
1967
1968 static const unsigned int drif1_ctrl_b_mux[] = {
1969         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1970 };
1971
1972 static const unsigned int drif1_data0_b_pins[] = {
1973         /* D0 */
1974         RCAR_GP_PIN(5, 7),
1975 };
1976
1977 static const unsigned int drif1_data0_b_mux[] = {
1978         RIF1_D0_B_MARK,
1979 };
1980
1981 static const unsigned int drif1_data1_b_pins[] = {
1982         /* D1 */
1983         RCAR_GP_PIN(5, 8),
1984 };
1985
1986 static const unsigned int drif1_data1_b_mux[] = {
1987         RIF1_D1_B_MARK,
1988 };
1989
1990 static const unsigned int drif1_ctrl_c_pins[] = {
1991         /* CLK, SYNC */
1992         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1993 };
1994
1995 static const unsigned int drif1_ctrl_c_mux[] = {
1996         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1997 };
1998
1999 static const unsigned int drif1_data0_c_pins[] = {
2000         /* D0 */
2001         RCAR_GP_PIN(5, 6),
2002 };
2003
2004 static const unsigned int drif1_data0_c_mux[] = {
2005         RIF1_D0_C_MARK,
2006 };
2007
2008 static const unsigned int drif1_data1_c_pins[] = {
2009         /* D1 */
2010         RCAR_GP_PIN(5, 10),
2011 };
2012
2013 static const unsigned int drif1_data1_c_mux[] = {
2014         RIF1_D1_C_MARK,
2015 };
2016
2017 /* - DRIF2 --------------------------------------------------------------- */
2018 static const unsigned int drif2_ctrl_a_pins[] = {
2019         /* CLK, SYNC */
2020         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2021 };
2022
2023 static const unsigned int drif2_ctrl_a_mux[] = {
2024         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2025 };
2026
2027 static const unsigned int drif2_data0_a_pins[] = {
2028         /* D0 */
2029         RCAR_GP_PIN(6, 7),
2030 };
2031
2032 static const unsigned int drif2_data0_a_mux[] = {
2033         RIF2_D0_A_MARK,
2034 };
2035
2036 static const unsigned int drif2_data1_a_pins[] = {
2037         /* D1 */
2038         RCAR_GP_PIN(6, 10),
2039 };
2040
2041 static const unsigned int drif2_data1_a_mux[] = {
2042         RIF2_D1_A_MARK,
2043 };
2044
2045 static const unsigned int drif2_ctrl_b_pins[] = {
2046         /* CLK, SYNC */
2047         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2048 };
2049
2050 static const unsigned int drif2_ctrl_b_mux[] = {
2051         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2052 };
2053
2054 static const unsigned int drif2_data0_b_pins[] = {
2055         /* D0 */
2056         RCAR_GP_PIN(6, 30),
2057 };
2058
2059 static const unsigned int drif2_data0_b_mux[] = {
2060         RIF2_D0_B_MARK,
2061 };
2062
2063 static const unsigned int drif2_data1_b_pins[] = {
2064         /* D1 */
2065         RCAR_GP_PIN(6, 31),
2066 };
2067
2068 static const unsigned int drif2_data1_b_mux[] = {
2069         RIF2_D1_B_MARK,
2070 };
2071
2072 /* - DRIF3 --------------------------------------------------------------- */
2073 static const unsigned int drif3_ctrl_a_pins[] = {
2074         /* CLK, SYNC */
2075         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2076 };
2077
2078 static const unsigned int drif3_ctrl_a_mux[] = {
2079         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2080 };
2081
2082 static const unsigned int drif3_data0_a_pins[] = {
2083         /* D0 */
2084         RCAR_GP_PIN(6, 19),
2085 };
2086
2087 static const unsigned int drif3_data0_a_mux[] = {
2088         RIF3_D0_A_MARK,
2089 };
2090
2091 static const unsigned int drif3_data1_a_pins[] = {
2092         /* D1 */
2093         RCAR_GP_PIN(6, 20),
2094 };
2095
2096 static const unsigned int drif3_data1_a_mux[] = {
2097         RIF3_D1_A_MARK,
2098 };
2099
2100 static const unsigned int drif3_ctrl_b_pins[] = {
2101         /* CLK, SYNC */
2102         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2103 };
2104
2105 static const unsigned int drif3_ctrl_b_mux[] = {
2106         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2107 };
2108
2109 static const unsigned int drif3_data0_b_pins[] = {
2110         /* D0 */
2111         RCAR_GP_PIN(6, 28),
2112 };
2113
2114 static const unsigned int drif3_data0_b_mux[] = {
2115         RIF3_D0_B_MARK,
2116 };
2117
2118 static const unsigned int drif3_data1_b_pins[] = {
2119         /* D1 */
2120         RCAR_GP_PIN(6, 29),
2121 };
2122
2123 static const unsigned int drif3_data1_b_mux[] = {
2124         RIF3_D1_B_MARK,
2125 };
2126
2127 /* - DU --------------------------------------------------------------------- */
2128 static const unsigned int du_rgb666_pins[] = {
2129         /* R[7:2], G[7:2], B[7:2] */
2130         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2131         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2132         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2133         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2134         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2135         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2136 };
2137
2138 static const unsigned int du_rgb666_mux[] = {
2139         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2140         DU_DR3_MARK, DU_DR2_MARK,
2141         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2142         DU_DG3_MARK, DU_DG2_MARK,
2143         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2144         DU_DB3_MARK, DU_DB2_MARK,
2145 };
2146
2147 static const unsigned int du_rgb888_pins[] = {
2148         /* R[7:0], G[7:0], B[7:0] */
2149         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2150         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2151         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2152         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2153         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2154         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2155         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2156         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2157         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2158 };
2159
2160 static const unsigned int du_rgb888_mux[] = {
2161         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2162         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2163         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2164         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2165         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2166         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2167 };
2168
2169 static const unsigned int du_clk_out_0_pins[] = {
2170         /* CLKOUT */
2171         RCAR_GP_PIN(1, 27),
2172 };
2173
2174 static const unsigned int du_clk_out_0_mux[] = {
2175         DU_DOTCLKOUT0_MARK
2176 };
2177
2178 static const unsigned int du_clk_out_1_pins[] = {
2179         /* CLKOUT */
2180         RCAR_GP_PIN(2, 3),
2181 };
2182
2183 static const unsigned int du_clk_out_1_mux[] = {
2184         DU_DOTCLKOUT1_MARK
2185 };
2186
2187 static const unsigned int du_sync_pins[] = {
2188         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2189         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2190 };
2191
2192 static const unsigned int du_sync_mux[] = {
2193         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2194 };
2195
2196 static const unsigned int du_oddf_pins[] = {
2197         /* EXDISP/EXODDF/EXCDE */
2198         RCAR_GP_PIN(2, 2),
2199 };
2200
2201 static const unsigned int du_oddf_mux[] = {
2202         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2203 };
2204
2205 static const unsigned int du_cde_pins[] = {
2206         /* CDE */
2207         RCAR_GP_PIN(2, 0),
2208 };
2209
2210 static const unsigned int du_cde_mux[] = {
2211         DU_CDE_MARK,
2212 };
2213
2214 static const unsigned int du_disp_pins[] = {
2215         /* DISP */
2216         RCAR_GP_PIN(2, 1),
2217 };
2218
2219 static const unsigned int du_disp_mux[] = {
2220         DU_DISP_MARK,
2221 };
2222
2223 /* - HSCIF0 ----------------------------------------------------------------- */
2224 static const unsigned int hscif0_data_pins[] = {
2225         /* RX, TX */
2226         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2227 };
2228
2229 static const unsigned int hscif0_data_mux[] = {
2230         HRX0_MARK, HTX0_MARK,
2231 };
2232
2233 static const unsigned int hscif0_clk_pins[] = {
2234         /* SCK */
2235         RCAR_GP_PIN(5, 12),
2236 };
2237
2238 static const unsigned int hscif0_clk_mux[] = {
2239         HSCK0_MARK,
2240 };
2241
2242 static const unsigned int hscif0_ctrl_pins[] = {
2243         /* RTS, CTS */
2244         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2245 };
2246
2247 static const unsigned int hscif0_ctrl_mux[] = {
2248         HRTS0_N_MARK, HCTS0_N_MARK,
2249 };
2250
2251 /* - HSCIF1 ----------------------------------------------------------------- */
2252 static const unsigned int hscif1_data_a_pins[] = {
2253         /* RX, TX */
2254         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2255 };
2256
2257 static const unsigned int hscif1_data_a_mux[] = {
2258         HRX1_A_MARK, HTX1_A_MARK,
2259 };
2260
2261 static const unsigned int hscif1_clk_a_pins[] = {
2262         /* SCK */
2263         RCAR_GP_PIN(6, 21),
2264 };
2265
2266 static const unsigned int hscif1_clk_a_mux[] = {
2267         HSCK1_A_MARK,
2268 };
2269
2270 static const unsigned int hscif1_ctrl_a_pins[] = {
2271         /* RTS, CTS */
2272         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2273 };
2274
2275 static const unsigned int hscif1_ctrl_a_mux[] = {
2276         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2277 };
2278
2279 static const unsigned int hscif1_data_b_pins[] = {
2280         /* RX, TX */
2281         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2282 };
2283
2284 static const unsigned int hscif1_data_b_mux[] = {
2285         HRX1_B_MARK, HTX1_B_MARK,
2286 };
2287
2288 static const unsigned int hscif1_clk_b_pins[] = {
2289         /* SCK */
2290         RCAR_GP_PIN(5, 0),
2291 };
2292
2293 static const unsigned int hscif1_clk_b_mux[] = {
2294         HSCK1_B_MARK,
2295 };
2296
2297 static const unsigned int hscif1_ctrl_b_pins[] = {
2298         /* RTS, CTS */
2299         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2300 };
2301
2302 static const unsigned int hscif1_ctrl_b_mux[] = {
2303         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2304 };
2305
2306 /* - HSCIF2 ----------------------------------------------------------------- */
2307 static const unsigned int hscif2_data_a_pins[] = {
2308         /* RX, TX */
2309         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2310 };
2311
2312 static const unsigned int hscif2_data_a_mux[] = {
2313         HRX2_A_MARK, HTX2_A_MARK,
2314 };
2315
2316 static const unsigned int hscif2_clk_a_pins[] = {
2317         /* SCK */
2318         RCAR_GP_PIN(6, 10),
2319 };
2320
2321 static const unsigned int hscif2_clk_a_mux[] = {
2322         HSCK2_A_MARK,
2323 };
2324
2325 static const unsigned int hscif2_ctrl_a_pins[] = {
2326         /* RTS, CTS */
2327         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2328 };
2329
2330 static const unsigned int hscif2_ctrl_a_mux[] = {
2331         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2332 };
2333
2334 static const unsigned int hscif2_data_b_pins[] = {
2335         /* RX, TX */
2336         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2337 };
2338
2339 static const unsigned int hscif2_data_b_mux[] = {
2340         HRX2_B_MARK, HTX2_B_MARK,
2341 };
2342
2343 static const unsigned int hscif2_clk_b_pins[] = {
2344         /* SCK */
2345         RCAR_GP_PIN(6, 21),
2346 };
2347
2348 static const unsigned int hscif2_clk_b_mux[] = {
2349         HSCK2_B_MARK,
2350 };
2351
2352 static const unsigned int hscif2_ctrl_b_pins[] = {
2353         /* RTS, CTS */
2354         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2355 };
2356
2357 static const unsigned int hscif2_ctrl_b_mux[] = {
2358         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2359 };
2360
2361 static const unsigned int hscif2_data_c_pins[] = {
2362         /* RX, TX */
2363         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2364 };
2365
2366 static const unsigned int hscif2_data_c_mux[] = {
2367         HRX2_C_MARK, HTX2_C_MARK,
2368 };
2369
2370 static const unsigned int hscif2_clk_c_pins[] = {
2371         /* SCK */
2372         RCAR_GP_PIN(6, 24),
2373 };
2374
2375 static const unsigned int hscif2_clk_c_mux[] = {
2376         HSCK2_C_MARK,
2377 };
2378
2379 static const unsigned int hscif2_ctrl_c_pins[] = {
2380         /* RTS, CTS */
2381         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2382 };
2383
2384 static const unsigned int hscif2_ctrl_c_mux[] = {
2385         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2386 };
2387
2388 /* - HSCIF3 ----------------------------------------------------------------- */
2389 static const unsigned int hscif3_data_a_pins[] = {
2390         /* RX, TX */
2391         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2392 };
2393
2394 static const unsigned int hscif3_data_a_mux[] = {
2395         HRX3_A_MARK, HTX3_A_MARK,
2396 };
2397
2398 static const unsigned int hscif3_clk_pins[] = {
2399         /* SCK */
2400         RCAR_GP_PIN(1, 22),
2401 };
2402
2403 static const unsigned int hscif3_clk_mux[] = {
2404         HSCK3_MARK,
2405 };
2406
2407 static const unsigned int hscif3_ctrl_pins[] = {
2408         /* RTS, CTS */
2409         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2410 };
2411
2412 static const unsigned int hscif3_ctrl_mux[] = {
2413         HRTS3_N_MARK, HCTS3_N_MARK,
2414 };
2415
2416 static const unsigned int hscif3_data_b_pins[] = {
2417         /* RX, TX */
2418         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2419 };
2420
2421 static const unsigned int hscif3_data_b_mux[] = {
2422         HRX3_B_MARK, HTX3_B_MARK,
2423 };
2424
2425 static const unsigned int hscif3_data_c_pins[] = {
2426         /* RX, TX */
2427         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2428 };
2429
2430 static const unsigned int hscif3_data_c_mux[] = {
2431         HRX3_C_MARK, HTX3_C_MARK,
2432 };
2433
2434 static const unsigned int hscif3_data_d_pins[] = {
2435         /* RX, TX */
2436         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2437 };
2438
2439 static const unsigned int hscif3_data_d_mux[] = {
2440         HRX3_D_MARK, HTX3_D_MARK,
2441 };
2442
2443 /* - HSCIF4 ----------------------------------------------------------------- */
2444 static const unsigned int hscif4_data_a_pins[] = {
2445         /* RX, TX */
2446         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2447 };
2448
2449 static const unsigned int hscif4_data_a_mux[] = {
2450         HRX4_A_MARK, HTX4_A_MARK,
2451 };
2452
2453 static const unsigned int hscif4_clk_pins[] = {
2454         /* SCK */
2455         RCAR_GP_PIN(1, 11),
2456 };
2457
2458 static const unsigned int hscif4_clk_mux[] = {
2459         HSCK4_MARK,
2460 };
2461
2462 static const unsigned int hscif4_ctrl_pins[] = {
2463         /* RTS, CTS */
2464         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2465 };
2466
2467 static const unsigned int hscif4_ctrl_mux[] = {
2468         HRTS4_N_MARK, HCTS4_N_MARK,
2469 };
2470
2471 static const unsigned int hscif4_data_b_pins[] = {
2472         /* RX, TX */
2473         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2474 };
2475
2476 static const unsigned int hscif4_data_b_mux[] = {
2477         HRX4_B_MARK, HTX4_B_MARK,
2478 };
2479
2480 /* - I2C -------------------------------------------------------------------- */
2481 static const unsigned int i2c1_a_pins[] = {
2482         /* SDA, SCL */
2483         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2484 };
2485 static const unsigned int i2c1_a_mux[] = {
2486         SDA1_A_MARK, SCL1_A_MARK,
2487 };
2488 static const unsigned int i2c1_b_pins[] = {
2489         /* SDA, SCL */
2490         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2491 };
2492 static const unsigned int i2c1_b_mux[] = {
2493         SDA1_B_MARK, SCL1_B_MARK,
2494 };
2495 static const unsigned int i2c2_a_pins[] = {
2496         /* SDA, SCL */
2497         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2498 };
2499 static const unsigned int i2c2_a_mux[] = {
2500         SDA2_A_MARK, SCL2_A_MARK,
2501 };
2502 static const unsigned int i2c2_b_pins[] = {
2503         /* SDA, SCL */
2504         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2505 };
2506 static const unsigned int i2c2_b_mux[] = {
2507         SDA2_B_MARK, SCL2_B_MARK,
2508 };
2509 static const unsigned int i2c6_a_pins[] = {
2510         /* SDA, SCL */
2511         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2512 };
2513 static const unsigned int i2c6_a_mux[] = {
2514         SDA6_A_MARK, SCL6_A_MARK,
2515 };
2516 static const unsigned int i2c6_b_pins[] = {
2517         /* SDA, SCL */
2518         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2519 };
2520 static const unsigned int i2c6_b_mux[] = {
2521         SDA6_B_MARK, SCL6_B_MARK,
2522 };
2523 static const unsigned int i2c6_c_pins[] = {
2524         /* SDA, SCL */
2525         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2526 };
2527 static const unsigned int i2c6_c_mux[] = {
2528         SDA6_C_MARK, SCL6_C_MARK,
2529 };
2530
2531 /* - INTC-EX ---------------------------------------------------------------- */
2532 static const unsigned int intc_ex_irq0_pins[] = {
2533         /* IRQ0 */
2534         RCAR_GP_PIN(2, 0),
2535 };
2536 static const unsigned int intc_ex_irq0_mux[] = {
2537         IRQ0_MARK,
2538 };
2539 static const unsigned int intc_ex_irq1_pins[] = {
2540         /* IRQ1 */
2541         RCAR_GP_PIN(2, 1),
2542 };
2543 static const unsigned int intc_ex_irq1_mux[] = {
2544         IRQ1_MARK,
2545 };
2546 static const unsigned int intc_ex_irq2_pins[] = {
2547         /* IRQ2 */
2548         RCAR_GP_PIN(2, 2),
2549 };
2550 static const unsigned int intc_ex_irq2_mux[] = {
2551         IRQ2_MARK,
2552 };
2553 static const unsigned int intc_ex_irq3_pins[] = {
2554         /* IRQ3 */
2555         RCAR_GP_PIN(2, 3),
2556 };
2557 static const unsigned int intc_ex_irq3_mux[] = {
2558         IRQ3_MARK,
2559 };
2560 static const unsigned int intc_ex_irq4_pins[] = {
2561         /* IRQ4 */
2562         RCAR_GP_PIN(2, 4),
2563 };
2564 static const unsigned int intc_ex_irq4_mux[] = {
2565         IRQ4_MARK,
2566 };
2567 static const unsigned int intc_ex_irq5_pins[] = {
2568         /* IRQ5 */
2569         RCAR_GP_PIN(2, 5),
2570 };
2571 static const unsigned int intc_ex_irq5_mux[] = {
2572         IRQ5_MARK,
2573 };
2574
2575 /* - MSIOF0 ----------------------------------------------------------------- */
2576 static const unsigned int msiof0_clk_pins[] = {
2577         /* SCK */
2578         RCAR_GP_PIN(5, 17),
2579 };
2580 static const unsigned int msiof0_clk_mux[] = {
2581         MSIOF0_SCK_MARK,
2582 };
2583 static const unsigned int msiof0_sync_pins[] = {
2584         /* SYNC */
2585         RCAR_GP_PIN(5, 18),
2586 };
2587 static const unsigned int msiof0_sync_mux[] = {
2588         MSIOF0_SYNC_MARK,
2589 };
2590 static const unsigned int msiof0_ss1_pins[] = {
2591         /* SS1 */
2592         RCAR_GP_PIN(5, 19),
2593 };
2594 static const unsigned int msiof0_ss1_mux[] = {
2595         MSIOF0_SS1_MARK,
2596 };
2597 static const unsigned int msiof0_ss2_pins[] = {
2598         /* SS2 */
2599         RCAR_GP_PIN(5, 21),
2600 };
2601 static const unsigned int msiof0_ss2_mux[] = {
2602         MSIOF0_SS2_MARK,
2603 };
2604 static const unsigned int msiof0_txd_pins[] = {
2605         /* TXD */
2606         RCAR_GP_PIN(5, 20),
2607 };
2608 static const unsigned int msiof0_txd_mux[] = {
2609         MSIOF0_TXD_MARK,
2610 };
2611 static const unsigned int msiof0_rxd_pins[] = {
2612         /* RXD */
2613         RCAR_GP_PIN(5, 22),
2614 };
2615 static const unsigned int msiof0_rxd_mux[] = {
2616         MSIOF0_RXD_MARK,
2617 };
2618 /* - MSIOF1 ----------------------------------------------------------------- */
2619 static const unsigned int msiof1_clk_a_pins[] = {
2620         /* SCK */
2621         RCAR_GP_PIN(6, 8),
2622 };
2623 static const unsigned int msiof1_clk_a_mux[] = {
2624         MSIOF1_SCK_A_MARK,
2625 };
2626 static const unsigned int msiof1_sync_a_pins[] = {
2627         /* SYNC */
2628         RCAR_GP_PIN(6, 9),
2629 };
2630 static const unsigned int msiof1_sync_a_mux[] = {
2631         MSIOF1_SYNC_A_MARK,
2632 };
2633 static const unsigned int msiof1_ss1_a_pins[] = {
2634         /* SS1 */
2635         RCAR_GP_PIN(6, 5),
2636 };
2637 static const unsigned int msiof1_ss1_a_mux[] = {
2638         MSIOF1_SS1_A_MARK,
2639 };
2640 static const unsigned int msiof1_ss2_a_pins[] = {
2641         /* SS2 */
2642         RCAR_GP_PIN(6, 6),
2643 };
2644 static const unsigned int msiof1_ss2_a_mux[] = {
2645         MSIOF1_SS2_A_MARK,
2646 };
2647 static const unsigned int msiof1_txd_a_pins[] = {
2648         /* TXD */
2649         RCAR_GP_PIN(6, 7),
2650 };
2651 static const unsigned int msiof1_txd_a_mux[] = {
2652         MSIOF1_TXD_A_MARK,
2653 };
2654 static const unsigned int msiof1_rxd_a_pins[] = {
2655         /* RXD */
2656         RCAR_GP_PIN(6, 10),
2657 };
2658 static const unsigned int msiof1_rxd_a_mux[] = {
2659         MSIOF1_RXD_A_MARK,
2660 };
2661 static const unsigned int msiof1_clk_b_pins[] = {
2662         /* SCK */
2663         RCAR_GP_PIN(5, 9),
2664 };
2665 static const unsigned int msiof1_clk_b_mux[] = {
2666         MSIOF1_SCK_B_MARK,
2667 };
2668 static const unsigned int msiof1_sync_b_pins[] = {
2669         /* SYNC */
2670         RCAR_GP_PIN(5, 3),
2671 };
2672 static const unsigned int msiof1_sync_b_mux[] = {
2673         MSIOF1_SYNC_B_MARK,
2674 };
2675 static const unsigned int msiof1_ss1_b_pins[] = {
2676         /* SS1 */
2677         RCAR_GP_PIN(5, 4),
2678 };
2679 static const unsigned int msiof1_ss1_b_mux[] = {
2680         MSIOF1_SS1_B_MARK,
2681 };
2682 static const unsigned int msiof1_ss2_b_pins[] = {
2683         /* SS2 */
2684         RCAR_GP_PIN(5, 0),
2685 };
2686 static const unsigned int msiof1_ss2_b_mux[] = {
2687         MSIOF1_SS2_B_MARK,
2688 };
2689 static const unsigned int msiof1_txd_b_pins[] = {
2690         /* TXD */
2691         RCAR_GP_PIN(5, 8),
2692 };
2693 static const unsigned int msiof1_txd_b_mux[] = {
2694         MSIOF1_TXD_B_MARK,
2695 };
2696 static const unsigned int msiof1_rxd_b_pins[] = {
2697         /* RXD */
2698         RCAR_GP_PIN(5, 7),
2699 };
2700 static const unsigned int msiof1_rxd_b_mux[] = {
2701         MSIOF1_RXD_B_MARK,
2702 };
2703 static const unsigned int msiof1_clk_c_pins[] = {
2704         /* SCK */
2705         RCAR_GP_PIN(6, 17),
2706 };
2707 static const unsigned int msiof1_clk_c_mux[] = {
2708         MSIOF1_SCK_C_MARK,
2709 };
2710 static const unsigned int msiof1_sync_c_pins[] = {
2711         /* SYNC */
2712         RCAR_GP_PIN(6, 18),
2713 };
2714 static const unsigned int msiof1_sync_c_mux[] = {
2715         MSIOF1_SYNC_C_MARK,
2716 };
2717 static const unsigned int msiof1_ss1_c_pins[] = {
2718         /* SS1 */
2719         RCAR_GP_PIN(6, 21),
2720 };
2721 static const unsigned int msiof1_ss1_c_mux[] = {
2722         MSIOF1_SS1_C_MARK,
2723 };
2724 static const unsigned int msiof1_ss2_c_pins[] = {
2725         /* SS2 */
2726         RCAR_GP_PIN(6, 27),
2727 };
2728 static const unsigned int msiof1_ss2_c_mux[] = {
2729         MSIOF1_SS2_C_MARK,
2730 };
2731 static const unsigned int msiof1_txd_c_pins[] = {
2732         /* TXD */
2733         RCAR_GP_PIN(6, 20),
2734 };
2735 static const unsigned int msiof1_txd_c_mux[] = {
2736         MSIOF1_TXD_C_MARK,
2737 };
2738 static const unsigned int msiof1_rxd_c_pins[] = {
2739         /* RXD */
2740         RCAR_GP_PIN(6, 19),
2741 };
2742 static const unsigned int msiof1_rxd_c_mux[] = {
2743         MSIOF1_RXD_C_MARK,
2744 };
2745 static const unsigned int msiof1_clk_d_pins[] = {
2746         /* SCK */
2747         RCAR_GP_PIN(5, 12),
2748 };
2749 static const unsigned int msiof1_clk_d_mux[] = {
2750         MSIOF1_SCK_D_MARK,
2751 };
2752 static const unsigned int msiof1_sync_d_pins[] = {
2753         /* SYNC */
2754         RCAR_GP_PIN(5, 15),
2755 };
2756 static const unsigned int msiof1_sync_d_mux[] = {
2757         MSIOF1_SYNC_D_MARK,
2758 };
2759 static const unsigned int msiof1_ss1_d_pins[] = {
2760         /* SS1 */
2761         RCAR_GP_PIN(5, 16),
2762 };
2763 static const unsigned int msiof1_ss1_d_mux[] = {
2764         MSIOF1_SS1_D_MARK,
2765 };
2766 static const unsigned int msiof1_ss2_d_pins[] = {
2767         /* SS2 */
2768         RCAR_GP_PIN(5, 21),
2769 };
2770 static const unsigned int msiof1_ss2_d_mux[] = {
2771         MSIOF1_SS2_D_MARK,
2772 };
2773 static const unsigned int msiof1_txd_d_pins[] = {
2774         /* TXD */
2775         RCAR_GP_PIN(5, 14),
2776 };
2777 static const unsigned int msiof1_txd_d_mux[] = {
2778         MSIOF1_TXD_D_MARK,
2779 };
2780 static const unsigned int msiof1_rxd_d_pins[] = {
2781         /* RXD */
2782         RCAR_GP_PIN(5, 13),
2783 };
2784 static const unsigned int msiof1_rxd_d_mux[] = {
2785         MSIOF1_RXD_D_MARK,
2786 };
2787 static const unsigned int msiof1_clk_e_pins[] = {
2788         /* SCK */
2789         RCAR_GP_PIN(3, 0),
2790 };
2791 static const unsigned int msiof1_clk_e_mux[] = {
2792         MSIOF1_SCK_E_MARK,
2793 };
2794 static const unsigned int msiof1_sync_e_pins[] = {
2795         /* SYNC */
2796         RCAR_GP_PIN(3, 1),
2797 };
2798 static const unsigned int msiof1_sync_e_mux[] = {
2799         MSIOF1_SYNC_E_MARK,
2800 };
2801 static const unsigned int msiof1_ss1_e_pins[] = {
2802         /* SS1 */
2803         RCAR_GP_PIN(3, 4),
2804 };
2805 static const unsigned int msiof1_ss1_e_mux[] = {
2806         MSIOF1_SS1_E_MARK,
2807 };
2808 static const unsigned int msiof1_ss2_e_pins[] = {
2809         /* SS2 */
2810         RCAR_GP_PIN(3, 5),
2811 };
2812 static const unsigned int msiof1_ss2_e_mux[] = {
2813         MSIOF1_SS2_E_MARK,
2814 };
2815 static const unsigned int msiof1_txd_e_pins[] = {
2816         /* TXD */
2817         RCAR_GP_PIN(3, 3),
2818 };
2819 static const unsigned int msiof1_txd_e_mux[] = {
2820         MSIOF1_TXD_E_MARK,
2821 };
2822 static const unsigned int msiof1_rxd_e_pins[] = {
2823         /* RXD */
2824         RCAR_GP_PIN(3, 2),
2825 };
2826 static const unsigned int msiof1_rxd_e_mux[] = {
2827         MSIOF1_RXD_E_MARK,
2828 };
2829 static const unsigned int msiof1_clk_f_pins[] = {
2830         /* SCK */
2831         RCAR_GP_PIN(5, 23),
2832 };
2833 static const unsigned int msiof1_clk_f_mux[] = {
2834         MSIOF1_SCK_F_MARK,
2835 };
2836 static const unsigned int msiof1_sync_f_pins[] = {
2837         /* SYNC */
2838         RCAR_GP_PIN(5, 24),
2839 };
2840 static const unsigned int msiof1_sync_f_mux[] = {
2841         MSIOF1_SYNC_F_MARK,
2842 };
2843 static const unsigned int msiof1_ss1_f_pins[] = {
2844         /* SS1 */
2845         RCAR_GP_PIN(6, 1),
2846 };
2847 static const unsigned int msiof1_ss1_f_mux[] = {
2848         MSIOF1_SS1_F_MARK,
2849 };
2850 static const unsigned int msiof1_ss2_f_pins[] = {
2851         /* SS2 */
2852         RCAR_GP_PIN(6, 2),
2853 };
2854 static const unsigned int msiof1_ss2_f_mux[] = {
2855         MSIOF1_SS2_F_MARK,
2856 };
2857 static const unsigned int msiof1_txd_f_pins[] = {
2858         /* TXD */
2859         RCAR_GP_PIN(6, 0),
2860 };
2861 static const unsigned int msiof1_txd_f_mux[] = {
2862         MSIOF1_TXD_F_MARK,
2863 };
2864 static const unsigned int msiof1_rxd_f_pins[] = {
2865         /* RXD */
2866         RCAR_GP_PIN(5, 25),
2867 };
2868 static const unsigned int msiof1_rxd_f_mux[] = {
2869         MSIOF1_RXD_F_MARK,
2870 };
2871 static const unsigned int msiof1_clk_g_pins[] = {
2872         /* SCK */
2873         RCAR_GP_PIN(3, 6),
2874 };
2875 static const unsigned int msiof1_clk_g_mux[] = {
2876         MSIOF1_SCK_G_MARK,
2877 };
2878 static const unsigned int msiof1_sync_g_pins[] = {
2879         /* SYNC */
2880         RCAR_GP_PIN(3, 7),
2881 };
2882 static const unsigned int msiof1_sync_g_mux[] = {
2883         MSIOF1_SYNC_G_MARK,
2884 };
2885 static const unsigned int msiof1_ss1_g_pins[] = {
2886         /* SS1 */
2887         RCAR_GP_PIN(3, 10),
2888 };
2889 static const unsigned int msiof1_ss1_g_mux[] = {
2890         MSIOF1_SS1_G_MARK,
2891 };
2892 static const unsigned int msiof1_ss2_g_pins[] = {
2893         /* SS2 */
2894         RCAR_GP_PIN(3, 11),
2895 };
2896 static const unsigned int msiof1_ss2_g_mux[] = {
2897         MSIOF1_SS2_G_MARK,
2898 };
2899 static const unsigned int msiof1_txd_g_pins[] = {
2900         /* TXD */
2901         RCAR_GP_PIN(3, 9),
2902 };
2903 static const unsigned int msiof1_txd_g_mux[] = {
2904         MSIOF1_TXD_G_MARK,
2905 };
2906 static const unsigned int msiof1_rxd_g_pins[] = {
2907         /* RXD */
2908         RCAR_GP_PIN(3, 8),
2909 };
2910 static const unsigned int msiof1_rxd_g_mux[] = {
2911         MSIOF1_RXD_G_MARK,
2912 };
2913 /* - MSIOF2 ----------------------------------------------------------------- */
2914 static const unsigned int msiof2_clk_a_pins[] = {
2915         /* SCK */
2916         RCAR_GP_PIN(1, 9),
2917 };
2918 static const unsigned int msiof2_clk_a_mux[] = {
2919         MSIOF2_SCK_A_MARK,
2920 };
2921 static const unsigned int msiof2_sync_a_pins[] = {
2922         /* SYNC */
2923         RCAR_GP_PIN(1, 8),
2924 };
2925 static const unsigned int msiof2_sync_a_mux[] = {
2926         MSIOF2_SYNC_A_MARK,
2927 };
2928 static const unsigned int msiof2_ss1_a_pins[] = {
2929         /* SS1 */
2930         RCAR_GP_PIN(1, 6),
2931 };
2932 static const unsigned int msiof2_ss1_a_mux[] = {
2933         MSIOF2_SS1_A_MARK,
2934 };
2935 static const unsigned int msiof2_ss2_a_pins[] = {
2936         /* SS2 */
2937         RCAR_GP_PIN(1, 7),
2938 };
2939 static const unsigned int msiof2_ss2_a_mux[] = {
2940         MSIOF2_SS2_A_MARK,
2941 };
2942 static const unsigned int msiof2_txd_a_pins[] = {
2943         /* TXD */
2944         RCAR_GP_PIN(1, 11),
2945 };
2946 static const unsigned int msiof2_txd_a_mux[] = {
2947         MSIOF2_TXD_A_MARK,
2948 };
2949 static const unsigned int msiof2_rxd_a_pins[] = {
2950         /* RXD */
2951         RCAR_GP_PIN(1, 10),
2952 };
2953 static const unsigned int msiof2_rxd_a_mux[] = {
2954         MSIOF2_RXD_A_MARK,
2955 };
2956 static const unsigned int msiof2_clk_b_pins[] = {
2957         /* SCK */
2958         RCAR_GP_PIN(0, 4),
2959 };
2960 static const unsigned int msiof2_clk_b_mux[] = {
2961         MSIOF2_SCK_B_MARK,
2962 };
2963 static const unsigned int msiof2_sync_b_pins[] = {
2964         /* SYNC */
2965         RCAR_GP_PIN(0, 5),
2966 };
2967 static const unsigned int msiof2_sync_b_mux[] = {
2968         MSIOF2_SYNC_B_MARK,
2969 };
2970 static const unsigned int msiof2_ss1_b_pins[] = {
2971         /* SS1 */
2972         RCAR_GP_PIN(0, 0),
2973 };
2974 static const unsigned int msiof2_ss1_b_mux[] = {
2975         MSIOF2_SS1_B_MARK,
2976 };
2977 static const unsigned int msiof2_ss2_b_pins[] = {
2978         /* SS2 */
2979         RCAR_GP_PIN(0, 1),
2980 };
2981 static const unsigned int msiof2_ss2_b_mux[] = {
2982         MSIOF2_SS2_B_MARK,
2983 };
2984 static const unsigned int msiof2_txd_b_pins[] = {
2985         /* TXD */
2986         RCAR_GP_PIN(0, 7),
2987 };
2988 static const unsigned int msiof2_txd_b_mux[] = {
2989         MSIOF2_TXD_B_MARK,
2990 };
2991 static const unsigned int msiof2_rxd_b_pins[] = {
2992         /* RXD */
2993         RCAR_GP_PIN(0, 6),
2994 };
2995 static const unsigned int msiof2_rxd_b_mux[] = {
2996         MSIOF2_RXD_B_MARK,
2997 };
2998 static const unsigned int msiof2_clk_c_pins[] = {
2999         /* SCK */
3000         RCAR_GP_PIN(2, 12),
3001 };
3002 static const unsigned int msiof2_clk_c_mux[] = {
3003         MSIOF2_SCK_C_MARK,
3004 };
3005 static const unsigned int msiof2_sync_c_pins[] = {
3006         /* SYNC */
3007         RCAR_GP_PIN(2, 11),
3008 };
3009 static const unsigned int msiof2_sync_c_mux[] = {
3010         MSIOF2_SYNC_C_MARK,
3011 };
3012 static const unsigned int msiof2_ss1_c_pins[] = {
3013         /* SS1 */
3014         RCAR_GP_PIN(2, 10),
3015 };
3016 static const unsigned int msiof2_ss1_c_mux[] = {
3017         MSIOF2_SS1_C_MARK,
3018 };
3019 static const unsigned int msiof2_ss2_c_pins[] = {
3020         /* SS2 */
3021         RCAR_GP_PIN(2, 9),
3022 };
3023 static const unsigned int msiof2_ss2_c_mux[] = {
3024         MSIOF2_SS2_C_MARK,
3025 };
3026 static const unsigned int msiof2_txd_c_pins[] = {
3027         /* TXD */
3028         RCAR_GP_PIN(2, 14),
3029 };
3030 static const unsigned int msiof2_txd_c_mux[] = {
3031         MSIOF2_TXD_C_MARK,
3032 };
3033 static const unsigned int msiof2_rxd_c_pins[] = {
3034         /* RXD */
3035         RCAR_GP_PIN(2, 13),
3036 };
3037 static const unsigned int msiof2_rxd_c_mux[] = {
3038         MSIOF2_RXD_C_MARK,
3039 };
3040 static const unsigned int msiof2_clk_d_pins[] = {
3041         /* SCK */
3042         RCAR_GP_PIN(0, 8),
3043 };
3044 static const unsigned int msiof2_clk_d_mux[] = {
3045         MSIOF2_SCK_D_MARK,
3046 };
3047 static const unsigned int msiof2_sync_d_pins[] = {
3048         /* SYNC */
3049         RCAR_GP_PIN(0, 9),
3050 };
3051 static const unsigned int msiof2_sync_d_mux[] = {
3052         MSIOF2_SYNC_D_MARK,
3053 };
3054 static const unsigned int msiof2_ss1_d_pins[] = {
3055         /* SS1 */
3056         RCAR_GP_PIN(0, 12),
3057 };
3058 static const unsigned int msiof2_ss1_d_mux[] = {
3059         MSIOF2_SS1_D_MARK,
3060 };
3061 static const unsigned int msiof2_ss2_d_pins[] = {
3062         /* SS2 */
3063         RCAR_GP_PIN(0, 13),
3064 };
3065 static const unsigned int msiof2_ss2_d_mux[] = {
3066         MSIOF2_SS2_D_MARK,
3067 };
3068 static const unsigned int msiof2_txd_d_pins[] = {
3069         /* TXD */
3070         RCAR_GP_PIN(0, 11),
3071 };
3072 static const unsigned int msiof2_txd_d_mux[] = {
3073         MSIOF2_TXD_D_MARK,
3074 };
3075 static const unsigned int msiof2_rxd_d_pins[] = {
3076         /* RXD */
3077         RCAR_GP_PIN(0, 10),
3078 };
3079 static const unsigned int msiof2_rxd_d_mux[] = {
3080         MSIOF2_RXD_D_MARK,
3081 };
3082 /* - MSIOF3 ----------------------------------------------------------------- */
3083 static const unsigned int msiof3_clk_a_pins[] = {
3084         /* SCK */
3085         RCAR_GP_PIN(0, 0),
3086 };
3087 static const unsigned int msiof3_clk_a_mux[] = {
3088         MSIOF3_SCK_A_MARK,
3089 };
3090 static const unsigned int msiof3_sync_a_pins[] = {
3091         /* SYNC */
3092         RCAR_GP_PIN(0, 1),
3093 };
3094 static const unsigned int msiof3_sync_a_mux[] = {
3095         MSIOF3_SYNC_A_MARK,
3096 };
3097 static const unsigned int msiof3_ss1_a_pins[] = {
3098         /* SS1 */
3099         RCAR_GP_PIN(0, 14),
3100 };
3101 static const unsigned int msiof3_ss1_a_mux[] = {
3102         MSIOF3_SS1_A_MARK,
3103 };
3104 static const unsigned int msiof3_ss2_a_pins[] = {
3105         /* SS2 */
3106         RCAR_GP_PIN(0, 15),
3107 };
3108 static const unsigned int msiof3_ss2_a_mux[] = {
3109         MSIOF3_SS2_A_MARK,
3110 };
3111 static const unsigned int msiof3_txd_a_pins[] = {
3112         /* TXD */
3113         RCAR_GP_PIN(0, 3),
3114 };
3115 static const unsigned int msiof3_txd_a_mux[] = {
3116         MSIOF3_TXD_A_MARK,
3117 };
3118 static const unsigned int msiof3_rxd_a_pins[] = {
3119         /* RXD */
3120         RCAR_GP_PIN(0, 2),
3121 };
3122 static const unsigned int msiof3_rxd_a_mux[] = {
3123         MSIOF3_RXD_A_MARK,
3124 };
3125 static const unsigned int msiof3_clk_b_pins[] = {
3126         /* SCK */
3127         RCAR_GP_PIN(1, 2),
3128 };
3129 static const unsigned int msiof3_clk_b_mux[] = {
3130         MSIOF3_SCK_B_MARK,
3131 };
3132 static const unsigned int msiof3_sync_b_pins[] = {
3133         /* SYNC */
3134         RCAR_GP_PIN(1, 0),
3135 };
3136 static const unsigned int msiof3_sync_b_mux[] = {
3137         MSIOF3_SYNC_B_MARK,
3138 };
3139 static const unsigned int msiof3_ss1_b_pins[] = {
3140         /* SS1 */
3141         RCAR_GP_PIN(1, 4),
3142 };
3143 static const unsigned int msiof3_ss1_b_mux[] = {
3144         MSIOF3_SS1_B_MARK,
3145 };
3146 static const unsigned int msiof3_ss2_b_pins[] = {
3147         /* SS2 */
3148         RCAR_GP_PIN(1, 5),
3149 };
3150 static const unsigned int msiof3_ss2_b_mux[] = {
3151         MSIOF3_SS2_B_MARK,
3152 };
3153 static const unsigned int msiof3_txd_b_pins[] = {
3154         /* TXD */
3155         RCAR_GP_PIN(1, 1),
3156 };
3157 static const unsigned int msiof3_txd_b_mux[] = {
3158         MSIOF3_TXD_B_MARK,
3159 };
3160 static const unsigned int msiof3_rxd_b_pins[] = {
3161         /* RXD */
3162         RCAR_GP_PIN(1, 3),
3163 };
3164 static const unsigned int msiof3_rxd_b_mux[] = {
3165         MSIOF3_RXD_B_MARK,
3166 };
3167 static const unsigned int msiof3_clk_c_pins[] = {
3168         /* SCK */
3169         RCAR_GP_PIN(1, 12),
3170 };
3171 static const unsigned int msiof3_clk_c_mux[] = {
3172         MSIOF3_SCK_C_MARK,
3173 };
3174 static const unsigned int msiof3_sync_c_pins[] = {
3175         /* SYNC */
3176         RCAR_GP_PIN(1, 13),
3177 };
3178 static const unsigned int msiof3_sync_c_mux[] = {
3179         MSIOF3_SYNC_C_MARK,
3180 };
3181 static const unsigned int msiof3_txd_c_pins[] = {
3182         /* TXD */
3183         RCAR_GP_PIN(1, 15),
3184 };
3185 static const unsigned int msiof3_txd_c_mux[] = {
3186         MSIOF3_TXD_C_MARK,
3187 };
3188 static const unsigned int msiof3_rxd_c_pins[] = {
3189         /* RXD */
3190         RCAR_GP_PIN(1, 14),
3191 };
3192 static const unsigned int msiof3_rxd_c_mux[] = {
3193         MSIOF3_RXD_C_MARK,
3194 };
3195 static const unsigned int msiof3_clk_d_pins[] = {
3196         /* SCK */
3197         RCAR_GP_PIN(1, 22),
3198 };
3199 static const unsigned int msiof3_clk_d_mux[] = {
3200         MSIOF3_SCK_D_MARK,
3201 };
3202 static const unsigned int msiof3_sync_d_pins[] = {
3203         /* SYNC */
3204         RCAR_GP_PIN(1, 23),
3205 };
3206 static const unsigned int msiof3_sync_d_mux[] = {
3207         MSIOF3_SYNC_D_MARK,
3208 };
3209 static const unsigned int msiof3_ss1_d_pins[] = {
3210         /* SS1 */
3211         RCAR_GP_PIN(1, 26),
3212 };
3213 static const unsigned int msiof3_ss1_d_mux[] = {
3214         MSIOF3_SS1_D_MARK,
3215 };
3216 static const unsigned int msiof3_txd_d_pins[] = {
3217         /* TXD */
3218         RCAR_GP_PIN(1, 25),
3219 };
3220 static const unsigned int msiof3_txd_d_mux[] = {
3221         MSIOF3_TXD_D_MARK,
3222 };
3223 static const unsigned int msiof3_rxd_d_pins[] = {
3224         /* RXD */
3225         RCAR_GP_PIN(1, 24),
3226 };
3227 static const unsigned int msiof3_rxd_d_mux[] = {
3228         MSIOF3_RXD_D_MARK,
3229 };
3230 static const unsigned int msiof3_clk_e_pins[] = {
3231         /* SCK */
3232         RCAR_GP_PIN(2, 3),
3233 };
3234 static const unsigned int msiof3_clk_e_mux[] = {
3235         MSIOF3_SCK_E_MARK,
3236 };
3237 static const unsigned int msiof3_sync_e_pins[] = {
3238         /* SYNC */
3239         RCAR_GP_PIN(2, 2),
3240 };
3241 static const unsigned int msiof3_sync_e_mux[] = {
3242         MSIOF3_SYNC_E_MARK,
3243 };
3244 static const unsigned int msiof3_ss1_e_pins[] = {
3245         /* SS1 */
3246         RCAR_GP_PIN(2, 1),
3247 };
3248 static const unsigned int msiof3_ss1_e_mux[] = {
3249         MSIOF3_SS1_E_MARK,
3250 };
3251 static const unsigned int msiof3_ss2_e_pins[] = {
3252         /* SS2 */
3253         RCAR_GP_PIN(2, 0),
3254 };
3255 static const unsigned int msiof3_ss2_e_mux[] = {
3256         MSIOF3_SS2_E_MARK,
3257 };
3258 static const unsigned int msiof3_txd_e_pins[] = {
3259         /* TXD */
3260         RCAR_GP_PIN(2, 5),
3261 };
3262 static const unsigned int msiof3_txd_e_mux[] = {
3263         MSIOF3_TXD_E_MARK,
3264 };
3265 static const unsigned int msiof3_rxd_e_pins[] = {
3266         /* RXD */
3267         RCAR_GP_PIN(2, 4),
3268 };
3269 static const unsigned int msiof3_rxd_e_mux[] = {
3270         MSIOF3_RXD_E_MARK,
3271 };
3272
3273 /* - PWM0 --------------------------------------------------------------------*/
3274 static const unsigned int pwm0_pins[] = {
3275         /* PWM */
3276         RCAR_GP_PIN(2, 6),
3277 };
3278 static const unsigned int pwm0_mux[] = {
3279         PWM0_MARK,
3280 };
3281 /* - PWM1 --------------------------------------------------------------------*/
3282 static const unsigned int pwm1_a_pins[] = {
3283         /* PWM */
3284         RCAR_GP_PIN(2, 7),
3285 };
3286 static const unsigned int pwm1_a_mux[] = {
3287         PWM1_A_MARK,
3288 };
3289 static const unsigned int pwm1_b_pins[] = {
3290         /* PWM */
3291         RCAR_GP_PIN(1, 8),
3292 };
3293 static const unsigned int pwm1_b_mux[] = {
3294         PWM1_B_MARK,
3295 };
3296 /* - PWM2 --------------------------------------------------------------------*/
3297 static const unsigned int pwm2_a_pins[] = {
3298         /* PWM */
3299         RCAR_GP_PIN(2, 8),
3300 };
3301 static const unsigned int pwm2_a_mux[] = {
3302         PWM2_A_MARK,
3303 };
3304 static const unsigned int pwm2_b_pins[] = {
3305         /* PWM */
3306         RCAR_GP_PIN(1, 11),
3307 };
3308 static const unsigned int pwm2_b_mux[] = {
3309         PWM2_B_MARK,
3310 };
3311 /* - PWM3 --------------------------------------------------------------------*/
3312 static const unsigned int pwm3_a_pins[] = {
3313         /* PWM */
3314         RCAR_GP_PIN(1, 0),
3315 };
3316 static const unsigned int pwm3_a_mux[] = {
3317         PWM3_A_MARK,
3318 };
3319 static const unsigned int pwm3_b_pins[] = {
3320         /* PWM */
3321         RCAR_GP_PIN(2, 2),
3322 };
3323 static const unsigned int pwm3_b_mux[] = {
3324         PWM3_B_MARK,
3325 };
3326 /* - PWM4 --------------------------------------------------------------------*/
3327 static const unsigned int pwm4_a_pins[] = {
3328         /* PWM */
3329         RCAR_GP_PIN(1, 1),
3330 };
3331 static const unsigned int pwm4_a_mux[] = {
3332         PWM4_A_MARK,
3333 };
3334 static const unsigned int pwm4_b_pins[] = {
3335         /* PWM */
3336         RCAR_GP_PIN(2, 3),
3337 };
3338 static const unsigned int pwm4_b_mux[] = {
3339         PWM4_B_MARK,
3340 };
3341 /* - PWM5 --------------------------------------------------------------------*/
3342 static const unsigned int pwm5_a_pins[] = {
3343         /* PWM */
3344         RCAR_GP_PIN(1, 2),
3345 };
3346 static const unsigned int pwm5_a_mux[] = {
3347         PWM5_A_MARK,
3348 };
3349 static const unsigned int pwm5_b_pins[] = {
3350         /* PWM */
3351         RCAR_GP_PIN(2, 4),
3352 };
3353 static const unsigned int pwm5_b_mux[] = {
3354         PWM5_B_MARK,
3355 };
3356 /* - PWM6 --------------------------------------------------------------------*/
3357 static const unsigned int pwm6_a_pins[] = {
3358         /* PWM */
3359         RCAR_GP_PIN(1, 3),
3360 };
3361 static const unsigned int pwm6_a_mux[] = {
3362         PWM6_A_MARK,
3363 };
3364 static const unsigned int pwm6_b_pins[] = {
3365         /* PWM */
3366         RCAR_GP_PIN(2, 5),
3367 };
3368 static const unsigned int pwm6_b_mux[] = {
3369         PWM6_B_MARK,
3370 };
3371
3372 /* - SATA --------------------------------------------------------------------*/
3373 static const unsigned int sata0_devslp_a_pins[] = {
3374         /* DEVSLP */
3375         RCAR_GP_PIN(6, 16),
3376 };
3377
3378 static const unsigned int sata0_devslp_a_mux[] = {
3379         SATA_DEVSLP_A_MARK,
3380 };
3381
3382 static const unsigned int sata0_devslp_b_pins[] = {
3383         /* DEVSLP */
3384         RCAR_GP_PIN(4, 6),
3385 };
3386
3387 static const unsigned int sata0_devslp_b_mux[] = {
3388         SATA_DEVSLP_B_MARK,
3389 };
3390
3391 /* - SCIF0 ------------------------------------------------------------------ */
3392 static const unsigned int scif0_data_pins[] = {
3393         /* RX, TX */
3394         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3395 };
3396 static const unsigned int scif0_data_mux[] = {
3397         RX0_MARK, TX0_MARK,
3398 };
3399 static const unsigned int scif0_clk_pins[] = {
3400         /* SCK */
3401         RCAR_GP_PIN(5, 0),
3402 };
3403 static const unsigned int scif0_clk_mux[] = {
3404         SCK0_MARK,
3405 };
3406 static const unsigned int scif0_ctrl_pins[] = {
3407         /* RTS, CTS */
3408         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3409 };
3410 static const unsigned int scif0_ctrl_mux[] = {
3411         RTS0_N_MARK, CTS0_N_MARK,
3412 };
3413 /* - SCIF1 ------------------------------------------------------------------ */
3414 static const unsigned int scif1_data_a_pins[] = {
3415         /* RX, TX */
3416         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3417 };
3418 static const unsigned int scif1_data_a_mux[] = {
3419         RX1_A_MARK, TX1_A_MARK,
3420 };
3421 static const unsigned int scif1_clk_pins[] = {
3422         /* SCK */
3423         RCAR_GP_PIN(6, 21),
3424 };
3425 static const unsigned int scif1_clk_mux[] = {
3426         SCK1_MARK,
3427 };
3428 static const unsigned int scif1_ctrl_pins[] = {
3429         /* RTS, CTS */
3430         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3431 };
3432 static const unsigned int scif1_ctrl_mux[] = {
3433         RTS1_N_MARK, CTS1_N_MARK,
3434 };
3435 static const unsigned int scif1_data_b_pins[] = {
3436         /* RX, TX */
3437         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3438 };
3439 static const unsigned int scif1_data_b_mux[] = {
3440         RX1_B_MARK, TX1_B_MARK,
3441 };
3442 /* - SCIF2 ------------------------------------------------------------------ */
3443 static const unsigned int scif2_data_a_pins[] = {
3444         /* RX, TX */
3445         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3446 };
3447 static const unsigned int scif2_data_a_mux[] = {
3448         RX2_A_MARK, TX2_A_MARK,
3449 };
3450 static const unsigned int scif2_clk_pins[] = {
3451         /* SCK */
3452         RCAR_GP_PIN(5, 9),
3453 };
3454 static const unsigned int scif2_clk_mux[] = {
3455         SCK2_MARK,
3456 };
3457 static const unsigned int scif2_data_b_pins[] = {
3458         /* RX, TX */
3459         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3460 };
3461 static const unsigned int scif2_data_b_mux[] = {
3462         RX2_B_MARK, TX2_B_MARK,
3463 };
3464 /* - SCIF3 ------------------------------------------------------------------ */
3465 static const unsigned int scif3_data_a_pins[] = {
3466         /* RX, TX */
3467         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3468 };
3469 static const unsigned int scif3_data_a_mux[] = {
3470         RX3_A_MARK, TX3_A_MARK,
3471 };
3472 static const unsigned int scif3_clk_pins[] = {
3473         /* SCK */
3474         RCAR_GP_PIN(1, 22),
3475 };
3476 static const unsigned int scif3_clk_mux[] = {
3477         SCK3_MARK,
3478 };
3479 static const unsigned int scif3_ctrl_pins[] = {
3480         /* RTS, CTS */
3481         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3482 };
3483 static const unsigned int scif3_ctrl_mux[] = {
3484         RTS3_N_MARK, CTS3_N_MARK,
3485 };
3486 static const unsigned int scif3_data_b_pins[] = {
3487         /* RX, TX */
3488         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3489 };
3490 static const unsigned int scif3_data_b_mux[] = {
3491         RX3_B_MARK, TX3_B_MARK,
3492 };
3493 /* - SCIF4 ------------------------------------------------------------------ */
3494 static const unsigned int scif4_data_a_pins[] = {
3495         /* RX, TX */
3496         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3497 };
3498 static const unsigned int scif4_data_a_mux[] = {
3499         RX4_A_MARK, TX4_A_MARK,
3500 };
3501 static const unsigned int scif4_clk_a_pins[] = {
3502         /* SCK */
3503         RCAR_GP_PIN(2, 10),
3504 };
3505 static const unsigned int scif4_clk_a_mux[] = {
3506         SCK4_A_MARK,
3507 };
3508 static const unsigned int scif4_ctrl_a_pins[] = {
3509         /* RTS, CTS */
3510         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3511 };
3512 static const unsigned int scif4_ctrl_a_mux[] = {
3513         RTS4_N_A_MARK, CTS4_N_A_MARK,
3514 };
3515 static const unsigned int scif4_data_b_pins[] = {
3516         /* RX, TX */
3517         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3518 };
3519 static const unsigned int scif4_data_b_mux[] = {
3520         RX4_B_MARK, TX4_B_MARK,
3521 };
3522 static const unsigned int scif4_clk_b_pins[] = {
3523         /* SCK */
3524         RCAR_GP_PIN(1, 5),
3525 };
3526 static const unsigned int scif4_clk_b_mux[] = {
3527         SCK4_B_MARK,
3528 };
3529 static const unsigned int scif4_ctrl_b_pins[] = {
3530         /* RTS, CTS */
3531         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3532 };
3533 static const unsigned int scif4_ctrl_b_mux[] = {
3534         RTS4_N_B_MARK, CTS4_N_B_MARK,
3535 };
3536 static const unsigned int scif4_data_c_pins[] = {
3537         /* RX, TX */
3538         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3539 };
3540 static const unsigned int scif4_data_c_mux[] = {
3541         RX4_C_MARK, TX4_C_MARK,
3542 };
3543 static const unsigned int scif4_clk_c_pins[] = {
3544         /* SCK */
3545         RCAR_GP_PIN(0, 8),
3546 };
3547 static const unsigned int scif4_clk_c_mux[] = {
3548         SCK4_C_MARK,
3549 };
3550 static const unsigned int scif4_ctrl_c_pins[] = {
3551         /* RTS, CTS */
3552         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3553 };
3554 static const unsigned int scif4_ctrl_c_mux[] = {
3555         RTS4_N_C_MARK, CTS4_N_C_MARK,
3556 };
3557 /* - SCIF5 ------------------------------------------------------------------ */
3558 static const unsigned int scif5_data_a_pins[] = {
3559         /* RX, TX */
3560         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3561 };
3562 static const unsigned int scif5_data_a_mux[] = {
3563         RX5_A_MARK, TX5_A_MARK,
3564 };
3565 static const unsigned int scif5_clk_a_pins[] = {
3566         /* SCK */
3567         RCAR_GP_PIN(6, 21),
3568 };
3569 static const unsigned int scif5_clk_a_mux[] = {
3570         SCK5_A_MARK,
3571 };
3572 static const unsigned int scif5_data_b_pins[] = {
3573         /* RX, TX */
3574         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3575 };
3576 static const unsigned int scif5_data_b_mux[] = {
3577         RX5_B_MARK, TX5_B_MARK,
3578 };
3579 static const unsigned int scif5_clk_b_pins[] = {
3580         /* SCK */
3581         RCAR_GP_PIN(5, 0),
3582 };
3583 static const unsigned int scif5_clk_b_mux[] = {
3584         SCK5_B_MARK,
3585 };
3586 /* - SCIF Clock ------------------------------------------------------------- */
3587 static const unsigned int scif_clk_a_pins[] = {
3588         /* SCIF_CLK */
3589         RCAR_GP_PIN(6, 23),
3590 };
3591 static const unsigned int scif_clk_a_mux[] = {
3592         SCIF_CLK_A_MARK,
3593 };
3594 static const unsigned int scif_clk_b_pins[] = {
3595         /* SCIF_CLK */
3596         RCAR_GP_PIN(5, 9),
3597 };
3598 static const unsigned int scif_clk_b_mux[] = {
3599         SCIF_CLK_B_MARK,
3600 };
3601
3602 /* - SDHI0 ------------------------------------------------------------------ */
3603 static const unsigned int sdhi0_data1_pins[] = {
3604         /* D0 */
3605         RCAR_GP_PIN(3, 2),
3606 };
3607
3608 static const unsigned int sdhi0_data1_mux[] = {
3609         SD0_DAT0_MARK,
3610 };
3611
3612 static const unsigned int sdhi0_data4_pins[] = {
3613         /* D[0:3] */
3614         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3615         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3616 };
3617
3618 static const unsigned int sdhi0_data4_mux[] = {
3619         SD0_DAT0_MARK, SD0_DAT1_MARK,
3620         SD0_DAT2_MARK, SD0_DAT3_MARK,
3621 };
3622
3623 static const unsigned int sdhi0_ctrl_pins[] = {
3624         /* CLK, CMD */
3625         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3626 };
3627
3628 static const unsigned int sdhi0_ctrl_mux[] = {
3629         SD0_CLK_MARK, SD0_CMD_MARK,
3630 };
3631
3632 static const unsigned int sdhi0_cd_pins[] = {
3633         /* CD */
3634         RCAR_GP_PIN(3, 12),
3635 };
3636
3637 static const unsigned int sdhi0_cd_mux[] = {
3638         SD0_CD_MARK,
3639 };
3640
3641 static const unsigned int sdhi0_wp_pins[] = {
3642         /* WP */
3643         RCAR_GP_PIN(3, 13),
3644 };
3645
3646 static const unsigned int sdhi0_wp_mux[] = {
3647         SD0_WP_MARK,
3648 };
3649
3650 /* - SDHI1 ------------------------------------------------------------------ */
3651 static const unsigned int sdhi1_data1_pins[] = {
3652         /* D0 */
3653         RCAR_GP_PIN(3, 8),
3654 };
3655
3656 static const unsigned int sdhi1_data1_mux[] = {
3657         SD1_DAT0_MARK,
3658 };
3659
3660 static const unsigned int sdhi1_data4_pins[] = {
3661         /* D[0:3] */
3662         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3663         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3664 };
3665
3666 static const unsigned int sdhi1_data4_mux[] = {
3667         SD1_DAT0_MARK, SD1_DAT1_MARK,
3668         SD1_DAT2_MARK, SD1_DAT3_MARK,
3669 };
3670
3671 static const unsigned int sdhi1_ctrl_pins[] = {
3672         /* CLK, CMD */
3673         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3674 };
3675
3676 static const unsigned int sdhi1_ctrl_mux[] = {
3677         SD1_CLK_MARK, SD1_CMD_MARK,
3678 };
3679
3680 static const unsigned int sdhi1_cd_pins[] = {
3681         /* CD */
3682         RCAR_GP_PIN(3, 14),
3683 };
3684
3685 static const unsigned int sdhi1_cd_mux[] = {
3686         SD1_CD_MARK,
3687 };
3688
3689 static const unsigned int sdhi1_wp_pins[] = {
3690         /* WP */
3691         RCAR_GP_PIN(3, 15),
3692 };
3693
3694 static const unsigned int sdhi1_wp_mux[] = {
3695         SD1_WP_MARK,
3696 };
3697
3698 /* - SDHI2 ------------------------------------------------------------------ */
3699 static const unsigned int sdhi2_data1_pins[] = {
3700         /* D0 */
3701         RCAR_GP_PIN(4, 2),
3702 };
3703
3704 static const unsigned int sdhi2_data1_mux[] = {
3705         SD2_DAT0_MARK,
3706 };
3707
3708 static const unsigned int sdhi2_data4_pins[] = {
3709         /* D[0:3] */
3710         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3711         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3712 };
3713
3714 static const unsigned int sdhi2_data4_mux[] = {
3715         SD2_DAT0_MARK, SD2_DAT1_MARK,
3716         SD2_DAT2_MARK, SD2_DAT3_MARK,
3717 };
3718
3719 static const unsigned int sdhi2_data8_pins[] = {
3720         /* D[0:7] */
3721         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3722         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3723         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3724         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3725 };
3726
3727 static const unsigned int sdhi2_data8_mux[] = {
3728         SD2_DAT0_MARK, SD2_DAT1_MARK,
3729         SD2_DAT2_MARK, SD2_DAT3_MARK,
3730         SD2_DAT4_MARK, SD2_DAT5_MARK,
3731         SD2_DAT6_MARK, SD2_DAT7_MARK,
3732 };
3733
3734 static const unsigned int sdhi2_ctrl_pins[] = {
3735         /* CLK, CMD */
3736         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3737 };
3738
3739 static const unsigned int sdhi2_ctrl_mux[] = {
3740         SD2_CLK_MARK, SD2_CMD_MARK,
3741 };
3742
3743 static const unsigned int sdhi2_cd_a_pins[] = {
3744         /* CD */
3745         RCAR_GP_PIN(4, 13),
3746 };
3747
3748 static const unsigned int sdhi2_cd_a_mux[] = {
3749         SD2_CD_A_MARK,
3750 };
3751
3752 static const unsigned int sdhi2_cd_b_pins[] = {
3753         /* CD */
3754         RCAR_GP_PIN(5, 10),
3755 };
3756
3757 static const unsigned int sdhi2_cd_b_mux[] = {
3758         SD2_CD_B_MARK,
3759 };
3760
3761 static const unsigned int sdhi2_wp_a_pins[] = {
3762         /* WP */
3763         RCAR_GP_PIN(4, 14),
3764 };
3765
3766 static const unsigned int sdhi2_wp_a_mux[] = {
3767         SD2_WP_A_MARK,
3768 };
3769
3770 static const unsigned int sdhi2_wp_b_pins[] = {
3771         /* WP */
3772         RCAR_GP_PIN(5, 11),
3773 };
3774
3775 static const unsigned int sdhi2_wp_b_mux[] = {
3776         SD2_WP_B_MARK,
3777 };
3778
3779 static const unsigned int sdhi2_ds_pins[] = {
3780         /* DS */
3781         RCAR_GP_PIN(4, 6),
3782 };
3783
3784 static const unsigned int sdhi2_ds_mux[] = {
3785         SD2_DS_MARK,
3786 };
3787
3788 /* - SDHI3 ------------------------------------------------------------------ */
3789 static const unsigned int sdhi3_data1_pins[] = {
3790         /* D0 */
3791         RCAR_GP_PIN(4, 9),
3792 };
3793
3794 static const unsigned int sdhi3_data1_mux[] = {
3795         SD3_DAT0_MARK,
3796 };
3797
3798 static const unsigned int sdhi3_data4_pins[] = {
3799         /* D[0:3] */
3800         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3801         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3802 };
3803
3804 static const unsigned int sdhi3_data4_mux[] = {
3805         SD3_DAT0_MARK, SD3_DAT1_MARK,
3806         SD3_DAT2_MARK, SD3_DAT3_MARK,
3807 };
3808
3809 static const unsigned int sdhi3_data8_pins[] = {
3810         /* D[0:7] */
3811         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3812         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3813         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3814         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3815 };
3816
3817 static const unsigned int sdhi3_data8_mux[] = {
3818         SD3_DAT0_MARK, SD3_DAT1_MARK,
3819         SD3_DAT2_MARK, SD3_DAT3_MARK,
3820         SD3_DAT4_MARK, SD3_DAT5_MARK,
3821         SD3_DAT6_MARK, SD3_DAT7_MARK,
3822 };
3823
3824 static const unsigned int sdhi3_ctrl_pins[] = {
3825         /* CLK, CMD */
3826         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3827 };
3828
3829 static const unsigned int sdhi3_ctrl_mux[] = {
3830         SD3_CLK_MARK, SD3_CMD_MARK,
3831 };
3832
3833 static const unsigned int sdhi3_cd_pins[] = {
3834         /* CD */
3835         RCAR_GP_PIN(4, 15),
3836 };
3837
3838 static const unsigned int sdhi3_cd_mux[] = {
3839         SD3_CD_MARK,
3840 };
3841
3842 static const unsigned int sdhi3_wp_pins[] = {
3843         /* WP */
3844         RCAR_GP_PIN(4, 16),
3845 };
3846
3847 static const unsigned int sdhi3_wp_mux[] = {
3848         SD3_WP_MARK,
3849 };
3850
3851 static const unsigned int sdhi3_ds_pins[] = {
3852         /* DS */
3853         RCAR_GP_PIN(4, 17),
3854 };
3855
3856 static const unsigned int sdhi3_ds_mux[] = {
3857         SD3_DS_MARK,
3858 };
3859
3860 /* - SSI -------------------------------------------------------------------- */
3861 static const unsigned int ssi0_data_pins[] = {
3862         /* SDATA */
3863         RCAR_GP_PIN(6, 2),
3864 };
3865 static const unsigned int ssi0_data_mux[] = {
3866         SSI_SDATA0_MARK,
3867 };
3868 static const unsigned int ssi01239_ctrl_pins[] = {
3869         /* SCK, WS */
3870         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3871 };
3872 static const unsigned int ssi01239_ctrl_mux[] = {
3873         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3874 };
3875 static const unsigned int ssi1_data_a_pins[] = {
3876         /* SDATA */
3877         RCAR_GP_PIN(6, 3),
3878 };
3879 static const unsigned int ssi1_data_a_mux[] = {
3880         SSI_SDATA1_A_MARK,
3881 };
3882 static const unsigned int ssi1_data_b_pins[] = {
3883         /* SDATA */
3884         RCAR_GP_PIN(5, 12),
3885 };
3886 static const unsigned int ssi1_data_b_mux[] = {
3887         SSI_SDATA1_B_MARK,
3888 };
3889 static const unsigned int ssi1_ctrl_a_pins[] = {
3890         /* SCK, WS */
3891         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3892 };
3893 static const unsigned int ssi1_ctrl_a_mux[] = {
3894         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3895 };
3896 static const unsigned int ssi1_ctrl_b_pins[] = {
3897         /* SCK, WS */
3898         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3899 };
3900 static const unsigned int ssi1_ctrl_b_mux[] = {
3901         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3902 };
3903 static const unsigned int ssi2_data_a_pins[] = {
3904         /* SDATA */
3905         RCAR_GP_PIN(6, 4),
3906 };
3907 static const unsigned int ssi2_data_a_mux[] = {
3908         SSI_SDATA2_A_MARK,
3909 };
3910 static const unsigned int ssi2_data_b_pins[] = {
3911         /* SDATA */
3912         RCAR_GP_PIN(5, 13),
3913 };
3914 static const unsigned int ssi2_data_b_mux[] = {
3915         SSI_SDATA2_B_MARK,
3916 };
3917 static const unsigned int ssi2_ctrl_a_pins[] = {
3918         /* SCK, WS */
3919         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3920 };
3921 static const unsigned int ssi2_ctrl_a_mux[] = {
3922         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3923 };
3924 static const unsigned int ssi2_ctrl_b_pins[] = {
3925         /* SCK, WS */
3926         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3927 };
3928 static const unsigned int ssi2_ctrl_b_mux[] = {
3929         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3930 };
3931 static const unsigned int ssi3_data_pins[] = {
3932         /* SDATA */
3933         RCAR_GP_PIN(6, 7),
3934 };
3935 static const unsigned int ssi3_data_mux[] = {
3936         SSI_SDATA3_MARK,
3937 };
3938 static const unsigned int ssi349_ctrl_pins[] = {
3939         /* SCK, WS */
3940         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3941 };
3942 static const unsigned int ssi349_ctrl_mux[] = {
3943         SSI_SCK349_MARK, SSI_WS349_MARK,
3944 };
3945 static const unsigned int ssi4_data_pins[] = {
3946         /* SDATA */
3947         RCAR_GP_PIN(6, 10),
3948 };
3949 static const unsigned int ssi4_data_mux[] = {
3950         SSI_SDATA4_MARK,
3951 };
3952 static const unsigned int ssi4_ctrl_pins[] = {
3953         /* SCK, WS */
3954         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3955 };
3956 static const unsigned int ssi4_ctrl_mux[] = {
3957         SSI_SCK4_MARK, SSI_WS4_MARK,
3958 };
3959 static const unsigned int ssi5_data_pins[] = {
3960         /* SDATA */
3961         RCAR_GP_PIN(6, 13),
3962 };
3963 static const unsigned int ssi5_data_mux[] = {
3964         SSI_SDATA5_MARK,
3965 };
3966 static const unsigned int ssi5_ctrl_pins[] = {
3967         /* SCK, WS */
3968         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3969 };
3970 static const unsigned int ssi5_ctrl_mux[] = {
3971         SSI_SCK5_MARK, SSI_WS5_MARK,
3972 };
3973 static const unsigned int ssi6_data_pins[] = {
3974         /* SDATA */
3975         RCAR_GP_PIN(6, 16),
3976 };
3977 static const unsigned int ssi6_data_mux[] = {
3978         SSI_SDATA6_MARK,
3979 };
3980 static const unsigned int ssi6_ctrl_pins[] = {
3981         /* SCK, WS */
3982         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3983 };
3984 static const unsigned int ssi6_ctrl_mux[] = {
3985         SSI_SCK6_MARK, SSI_WS6_MARK,
3986 };
3987 static const unsigned int ssi7_data_pins[] = {
3988         /* SDATA */
3989         RCAR_GP_PIN(6, 19),
3990 };
3991 static const unsigned int ssi7_data_mux[] = {
3992         SSI_SDATA7_MARK,
3993 };
3994 static const unsigned int ssi78_ctrl_pins[] = {
3995         /* SCK, WS */
3996         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3997 };
3998 static const unsigned int ssi78_ctrl_mux[] = {
3999         SSI_SCK78_MARK, SSI_WS78_MARK,
4000 };
4001 static const unsigned int ssi8_data_pins[] = {
4002         /* SDATA */
4003         RCAR_GP_PIN(6, 20),
4004 };
4005 static const unsigned int ssi8_data_mux[] = {
4006         SSI_SDATA8_MARK,
4007 };
4008 static const unsigned int ssi9_data_a_pins[] = {
4009         /* SDATA */
4010         RCAR_GP_PIN(6, 21),
4011 };
4012 static const unsigned int ssi9_data_a_mux[] = {
4013         SSI_SDATA9_A_MARK,
4014 };
4015 static const unsigned int ssi9_data_b_pins[] = {
4016         /* SDATA */
4017         RCAR_GP_PIN(5, 14),
4018 };
4019 static const unsigned int ssi9_data_b_mux[] = {
4020         SSI_SDATA9_B_MARK,
4021 };
4022 static const unsigned int ssi9_ctrl_a_pins[] = {
4023         /* SCK, WS */
4024         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4025 };
4026 static const unsigned int ssi9_ctrl_a_mux[] = {
4027         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4028 };
4029 static const unsigned int ssi9_ctrl_b_pins[] = {
4030         /* SCK, WS */
4031         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4032 };
4033 static const unsigned int ssi9_ctrl_b_mux[] = {
4034         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4035 };
4036
4037 /* - TMU -------------------------------------------------------------------- */
4038 static const unsigned int tmu_tclk1_a_pins[] = {
4039         /* TCLK */
4040         RCAR_GP_PIN(6, 23),
4041 };
4042
4043 static const unsigned int tmu_tclk1_a_mux[] = {
4044         TCLK1_A_MARK,
4045 };
4046
4047 static const unsigned int tmu_tclk1_b_pins[] = {
4048         /* TCLK */
4049         RCAR_GP_PIN(5, 19),
4050 };
4051
4052 static const unsigned int tmu_tclk1_b_mux[] = {
4053         TCLK1_B_MARK,
4054 };
4055
4056 static const unsigned int tmu_tclk2_a_pins[] = {
4057         /* TCLK */
4058         RCAR_GP_PIN(6, 19),
4059 };
4060
4061 static const unsigned int tmu_tclk2_a_mux[] = {
4062         TCLK2_A_MARK,
4063 };
4064
4065 static const unsigned int tmu_tclk2_b_pins[] = {
4066         /* TCLK */
4067         RCAR_GP_PIN(6, 28),
4068 };
4069
4070 static const unsigned int tmu_tclk2_b_mux[] = {
4071         TCLK2_B_MARK,
4072 };
4073
4074 /* - USB0 ------------------------------------------------------------------- */
4075 static const unsigned int usb0_pins[] = {
4076         /* PWEN, OVC */
4077         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4078 };
4079
4080 static const unsigned int usb0_mux[] = {
4081         USB0_PWEN_MARK, USB0_OVC_MARK,
4082 };
4083
4084 /* - USB1 ------------------------------------------------------------------- */
4085 static const unsigned int usb1_pins[] = {
4086         /* PWEN, OVC */
4087         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4088 };
4089
4090 static const unsigned int usb1_mux[] = {
4091         USB1_PWEN_MARK, USB1_OVC_MARK,
4092 };
4093
4094 /* - USB30 ------------------------------------------------------------------ */
4095 static const unsigned int usb30_pins[] = {
4096         /* PWEN, OVC */
4097         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4098 };
4099
4100 static const unsigned int usb30_mux[] = {
4101         USB30_PWEN_MARK, USB30_OVC_MARK,
4102 };
4103
4104 /* - VIN4 ------------------------------------------------------------------- */
4105 static const unsigned int vin4_data18_a_pins[] = {
4106         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4107         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4108         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4109         RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
4110         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
4111         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
4112         RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
4113         RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
4114         RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
4115 };
4116
4117 static const unsigned int vin4_data18_a_mux[] = {
4118         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4119         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4120         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4121         VI4_DATA10_MARK,  VI4_DATA11_MARK,
4122         VI4_DATA12_MARK,  VI4_DATA13_MARK,
4123         VI4_DATA14_MARK,  VI4_DATA15_MARK,
4124         VI4_DATA18_MARK,  VI4_DATA19_MARK,
4125         VI4_DATA20_MARK,  VI4_DATA21_MARK,
4126         VI4_DATA22_MARK,  VI4_DATA23_MARK,
4127 };
4128
4129 static const union vin_data vin4_data_a_pins = {
4130         .data24 = {
4131                 RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
4132                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4133                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4134                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4135                 RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
4136                 RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
4137                 RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
4138                 RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
4139                 RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
4140                 RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
4141                 RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
4142                 RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
4143         },
4144 };
4145
4146 static const union vin_data vin4_data_a_mux = {
4147         .data24 = {
4148                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4149                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4150                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4151                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4152                 VI4_DATA8_MARK,   VI4_DATA9_MARK,
4153                 VI4_DATA10_MARK,  VI4_DATA11_MARK,
4154                 VI4_DATA12_MARK,  VI4_DATA13_MARK,
4155                 VI4_DATA14_MARK,  VI4_DATA15_MARK,
4156                 VI4_DATA16_MARK,  VI4_DATA17_MARK,
4157                 VI4_DATA18_MARK,  VI4_DATA19_MARK,
4158                 VI4_DATA20_MARK,  VI4_DATA21_MARK,
4159                 VI4_DATA22_MARK,  VI4_DATA23_MARK,
4160         },
4161 };
4162
4163 static const unsigned int vin4_data18_b_pins[] = {
4164         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4165         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4166         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4167         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4168         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4169         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4170         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4171         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4172         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4173 };
4174
4175 static const unsigned int vin4_data18_b_mux[] = {
4176         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4177         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4178         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4179         VI4_DATA10_MARK,  VI4_DATA11_MARK,
4180         VI4_DATA12_MARK,  VI4_DATA13_MARK,
4181         VI4_DATA14_MARK,  VI4_DATA15_MARK,
4182         VI4_DATA18_MARK,  VI4_DATA19_MARK,
4183         VI4_DATA20_MARK,  VI4_DATA21_MARK,
4184         VI4_DATA22_MARK,  VI4_DATA23_MARK,
4185 };
4186
4187 static const union vin_data vin4_data_b_pins = {
4188         .data24 = {
4189                 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4190                 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4191                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4192                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4193                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4194                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4195                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4196                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4197                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4198                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4199                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4200                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4201         },
4202 };
4203
4204 static const union vin_data vin4_data_b_mux = {
4205         .data24 = {
4206                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4207                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4208                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4209                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4210                 VI4_DATA8_MARK,   VI4_DATA9_MARK,
4211                 VI4_DATA10_MARK,  VI4_DATA11_MARK,
4212                 VI4_DATA12_MARK,  VI4_DATA13_MARK,
4213                 VI4_DATA14_MARK,  VI4_DATA15_MARK,
4214                 VI4_DATA16_MARK,  VI4_DATA17_MARK,
4215                 VI4_DATA18_MARK,  VI4_DATA19_MARK,
4216                 VI4_DATA20_MARK,  VI4_DATA21_MARK,
4217                 VI4_DATA22_MARK,  VI4_DATA23_MARK,
4218         },
4219 };
4220
4221 static const unsigned int vin4_sync_pins[] = {
4222         /* VSYNC_N, HSYNC_N */
4223         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4224 };
4225
4226 static const unsigned int vin4_sync_mux[] = {
4227         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4228 };
4229
4230 static const unsigned int vin4_field_pins[] = {
4231         RCAR_GP_PIN(1, 16),
4232 };
4233
4234 static const unsigned int vin4_field_mux[] = {
4235         VI4_FIELD_MARK,
4236 };
4237
4238 static const unsigned int vin4_clkenb_pins[] = {
4239         RCAR_GP_PIN(1, 19),
4240 };
4241
4242 static const unsigned int vin4_clkenb_mux[] = {
4243         VI4_CLKENB_MARK,
4244 };
4245
4246 static const unsigned int vin4_clk_pins[] = {
4247         RCAR_GP_PIN(1, 27),
4248 };
4249
4250 static const unsigned int vin4_clk_mux[] = {
4251         VI4_CLK_MARK,
4252 };
4253
4254 /* - VIN5 ------------------------------------------------------------------- */
4255 static const union vin_data16 vin5_data_pins = {
4256         .data16 = {
4257                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4258                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4259                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4260                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4261                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4262                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4263                 RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
4264                 RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
4265         },
4266 };
4267
4268 static const union vin_data16 vin5_data_mux = {
4269         .data16 = {
4270                 VI5_DATA0_MARK, VI5_DATA1_MARK,
4271                 VI5_DATA2_MARK, VI5_DATA3_MARK,
4272                 VI5_DATA4_MARK, VI5_DATA5_MARK,
4273                 VI5_DATA6_MARK, VI5_DATA7_MARK,
4274                 VI5_DATA8_MARK,  VI5_DATA9_MARK,
4275                 VI5_DATA10_MARK, VI5_DATA11_MARK,
4276                 VI5_DATA12_MARK, VI5_DATA13_MARK,
4277                 VI5_DATA14_MARK, VI5_DATA15_MARK,
4278         },
4279 };
4280
4281 static const unsigned int vin5_sync_pins[] = {
4282         /* VSYNC_N, HSYNC_N */
4283         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4284 };
4285
4286 static const unsigned int vin5_sync_mux[] = {
4287         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4288 };
4289
4290 static const unsigned int vin5_field_pins[] = {
4291         RCAR_GP_PIN(1, 11),
4292 };
4293
4294 static const unsigned int vin5_field_mux[] = {
4295         VI5_FIELD_MARK,
4296 };
4297
4298 static const unsigned int vin5_clkenb_pins[] = {
4299         RCAR_GP_PIN(1, 20),
4300 };
4301
4302 static const unsigned int vin5_clkenb_mux[] = {
4303         VI5_CLKENB_MARK,
4304 };
4305
4306 static const unsigned int vin5_clk_pins[] = {
4307         RCAR_GP_PIN(1, 21),
4308 };
4309
4310 static const unsigned int vin5_clk_mux[] = {
4311         VI5_CLK_MARK,
4312 };
4313
4314 static const struct sh_pfc_pin_group pinmux_groups[] = {
4315         SH_PFC_PIN_GROUP(audio_clk_a_a),
4316         SH_PFC_PIN_GROUP(audio_clk_a_b),
4317         SH_PFC_PIN_GROUP(audio_clk_a_c),
4318         SH_PFC_PIN_GROUP(audio_clk_b_a),
4319         SH_PFC_PIN_GROUP(audio_clk_b_b),
4320         SH_PFC_PIN_GROUP(audio_clk_c_a),
4321         SH_PFC_PIN_GROUP(audio_clk_c_b),
4322         SH_PFC_PIN_GROUP(audio_clkout_a),
4323         SH_PFC_PIN_GROUP(audio_clkout_b),
4324         SH_PFC_PIN_GROUP(audio_clkout_c),
4325         SH_PFC_PIN_GROUP(audio_clkout_d),
4326         SH_PFC_PIN_GROUP(audio_clkout1_a),
4327         SH_PFC_PIN_GROUP(audio_clkout1_b),
4328         SH_PFC_PIN_GROUP(audio_clkout2_a),
4329         SH_PFC_PIN_GROUP(audio_clkout2_b),
4330         SH_PFC_PIN_GROUP(audio_clkout3_a),
4331         SH_PFC_PIN_GROUP(audio_clkout3_b),
4332         SH_PFC_PIN_GROUP(avb_link),
4333         SH_PFC_PIN_GROUP(avb_magic),
4334         SH_PFC_PIN_GROUP(avb_phy_int),
4335         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
4336         SH_PFC_PIN_GROUP(avb_mdio),
4337         SH_PFC_PIN_GROUP(avb_mii),
4338         SH_PFC_PIN_GROUP(avb_avtp_pps),
4339         SH_PFC_PIN_GROUP(avb_avtp_match_a),
4340         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4341         SH_PFC_PIN_GROUP(avb_avtp_match_b),
4342         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4343         SH_PFC_PIN_GROUP(can0_data_a),
4344         SH_PFC_PIN_GROUP(can0_data_b),
4345         SH_PFC_PIN_GROUP(can1_data),
4346         SH_PFC_PIN_GROUP(can_clk),
4347         SH_PFC_PIN_GROUP(canfd0_data_a),
4348         SH_PFC_PIN_GROUP(canfd0_data_b),
4349         SH_PFC_PIN_GROUP(canfd1_data),
4350         SH_PFC_PIN_GROUP(drif0_ctrl_a),
4351         SH_PFC_PIN_GROUP(drif0_data0_a),
4352         SH_PFC_PIN_GROUP(drif0_data1_a),
4353         SH_PFC_PIN_GROUP(drif0_ctrl_b),
4354         SH_PFC_PIN_GROUP(drif0_data0_b),
4355         SH_PFC_PIN_GROUP(drif0_data1_b),
4356         SH_PFC_PIN_GROUP(drif0_ctrl_c),
4357         SH_PFC_PIN_GROUP(drif0_data0_c),
4358         SH_PFC_PIN_GROUP(drif0_data1_c),
4359         SH_PFC_PIN_GROUP(drif1_ctrl_a),
4360         SH_PFC_PIN_GROUP(drif1_data0_a),
4361         SH_PFC_PIN_GROUP(drif1_data1_a),
4362         SH_PFC_PIN_GROUP(drif1_ctrl_b),
4363         SH_PFC_PIN_GROUP(drif1_data0_b),
4364         SH_PFC_PIN_GROUP(drif1_data1_b),
4365         SH_PFC_PIN_GROUP(drif1_ctrl_c),
4366         SH_PFC_PIN_GROUP(drif1_data0_c),
4367         SH_PFC_PIN_GROUP(drif1_data1_c),
4368         SH_PFC_PIN_GROUP(drif2_ctrl_a),
4369         SH_PFC_PIN_GROUP(drif2_data0_a),
4370         SH_PFC_PIN_GROUP(drif2_data1_a),
4371         SH_PFC_PIN_GROUP(drif2_ctrl_b),
4372         SH_PFC_PIN_GROUP(drif2_data0_b),
4373         SH_PFC_PIN_GROUP(drif2_data1_b),
4374         SH_PFC_PIN_GROUP(drif3_ctrl_a),
4375         SH_PFC_PIN_GROUP(drif3_data0_a),
4376         SH_PFC_PIN_GROUP(drif3_data1_a),
4377         SH_PFC_PIN_GROUP(drif3_ctrl_b),
4378         SH_PFC_PIN_GROUP(drif3_data0_b),
4379         SH_PFC_PIN_GROUP(drif3_data1_b),
4380         SH_PFC_PIN_GROUP(du_rgb666),
4381         SH_PFC_PIN_GROUP(du_rgb888),
4382         SH_PFC_PIN_GROUP(du_clk_out_0),
4383         SH_PFC_PIN_GROUP(du_clk_out_1),
4384         SH_PFC_PIN_GROUP(du_sync),
4385         SH_PFC_PIN_GROUP(du_oddf),
4386         SH_PFC_PIN_GROUP(du_cde),
4387         SH_PFC_PIN_GROUP(du_disp),
4388         SH_PFC_PIN_GROUP(hscif0_data),
4389         SH_PFC_PIN_GROUP(hscif0_clk),
4390         SH_PFC_PIN_GROUP(hscif0_ctrl),
4391         SH_PFC_PIN_GROUP(hscif1_data_a),
4392         SH_PFC_PIN_GROUP(hscif1_clk_a),
4393         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4394         SH_PFC_PIN_GROUP(hscif1_data_b),
4395         SH_PFC_PIN_GROUP(hscif1_clk_b),
4396         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4397         SH_PFC_PIN_GROUP(hscif2_data_a),
4398         SH_PFC_PIN_GROUP(hscif2_clk_a),
4399         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4400         SH_PFC_PIN_GROUP(hscif2_data_b),
4401         SH_PFC_PIN_GROUP(hscif2_clk_b),
4402         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4403         SH_PFC_PIN_GROUP(hscif2_data_c),
4404         SH_PFC_PIN_GROUP(hscif2_clk_c),
4405         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4406         SH_PFC_PIN_GROUP(hscif3_data_a),
4407         SH_PFC_PIN_GROUP(hscif3_clk),
4408         SH_PFC_PIN_GROUP(hscif3_ctrl),
4409         SH_PFC_PIN_GROUP(hscif3_data_b),
4410         SH_PFC_PIN_GROUP(hscif3_data_c),
4411         SH_PFC_PIN_GROUP(hscif3_data_d),
4412         SH_PFC_PIN_GROUP(hscif4_data_a),
4413         SH_PFC_PIN_GROUP(hscif4_clk),
4414         SH_PFC_PIN_GROUP(hscif4_ctrl),
4415         SH_PFC_PIN_GROUP(hscif4_data_b),
4416         SH_PFC_PIN_GROUP(i2c1_a),
4417         SH_PFC_PIN_GROUP(i2c1_b),
4418         SH_PFC_PIN_GROUP(i2c2_a),
4419         SH_PFC_PIN_GROUP(i2c2_b),
4420         SH_PFC_PIN_GROUP(i2c6_a),
4421         SH_PFC_PIN_GROUP(i2c6_b),
4422         SH_PFC_PIN_GROUP(i2c6_c),
4423         SH_PFC_PIN_GROUP(intc_ex_irq0),
4424         SH_PFC_PIN_GROUP(intc_ex_irq1),
4425         SH_PFC_PIN_GROUP(intc_ex_irq2),
4426         SH_PFC_PIN_GROUP(intc_ex_irq3),
4427         SH_PFC_PIN_GROUP(intc_ex_irq4),
4428         SH_PFC_PIN_GROUP(intc_ex_irq5),
4429         SH_PFC_PIN_GROUP(msiof0_clk),
4430         SH_PFC_PIN_GROUP(msiof0_sync),
4431         SH_PFC_PIN_GROUP(msiof0_ss1),
4432         SH_PFC_PIN_GROUP(msiof0_ss2),
4433         SH_PFC_PIN_GROUP(msiof0_txd),
4434         SH_PFC_PIN_GROUP(msiof0_rxd),
4435         SH_PFC_PIN_GROUP(msiof1_clk_a),
4436         SH_PFC_PIN_GROUP(msiof1_sync_a),
4437         SH_PFC_PIN_GROUP(msiof1_ss1_a),
4438         SH_PFC_PIN_GROUP(msiof1_ss2_a),
4439         SH_PFC_PIN_GROUP(msiof1_txd_a),
4440         SH_PFC_PIN_GROUP(msiof1_rxd_a),
4441         SH_PFC_PIN_GROUP(msiof1_clk_b),
4442         SH_PFC_PIN_GROUP(msiof1_sync_b),
4443         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4444         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4445         SH_PFC_PIN_GROUP(msiof1_txd_b),
4446         SH_PFC_PIN_GROUP(msiof1_rxd_b),
4447         SH_PFC_PIN_GROUP(msiof1_clk_c),
4448         SH_PFC_PIN_GROUP(msiof1_sync_c),
4449         SH_PFC_PIN_GROUP(msiof1_ss1_c),
4450         SH_PFC_PIN_GROUP(msiof1_ss2_c),
4451         SH_PFC_PIN_GROUP(msiof1_txd_c),
4452         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4453         SH_PFC_PIN_GROUP(msiof1_clk_d),
4454         SH_PFC_PIN_GROUP(msiof1_sync_d),
4455         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4456         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4457         SH_PFC_PIN_GROUP(msiof1_txd_d),
4458         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4459         SH_PFC_PIN_GROUP(msiof1_clk_e),
4460         SH_PFC_PIN_GROUP(msiof1_sync_e),
4461         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4462         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4463         SH_PFC_PIN_GROUP(msiof1_txd_e),
4464         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4465         SH_PFC_PIN_GROUP(msiof1_clk_f),
4466         SH_PFC_PIN_GROUP(msiof1_sync_f),
4467         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4468         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4469         SH_PFC_PIN_GROUP(msiof1_txd_f),
4470         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4471         SH_PFC_PIN_GROUP(msiof1_clk_g),
4472         SH_PFC_PIN_GROUP(msiof1_sync_g),
4473         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4474         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4475         SH_PFC_PIN_GROUP(msiof1_txd_g),
4476         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4477         SH_PFC_PIN_GROUP(msiof2_clk_a),
4478         SH_PFC_PIN_GROUP(msiof2_sync_a),
4479         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4480         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4481         SH_PFC_PIN_GROUP(msiof2_txd_a),
4482         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4483         SH_PFC_PIN_GROUP(msiof2_clk_b),
4484         SH_PFC_PIN_GROUP(msiof2_sync_b),
4485         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4486         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4487         SH_PFC_PIN_GROUP(msiof2_txd_b),
4488         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4489         SH_PFC_PIN_GROUP(msiof2_clk_c),
4490         SH_PFC_PIN_GROUP(msiof2_sync_c),
4491         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4492         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4493         SH_PFC_PIN_GROUP(msiof2_txd_c),
4494         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4495         SH_PFC_PIN_GROUP(msiof2_clk_d),
4496         SH_PFC_PIN_GROUP(msiof2_sync_d),
4497         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4498         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4499         SH_PFC_PIN_GROUP(msiof2_txd_d),
4500         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4501         SH_PFC_PIN_GROUP(msiof3_clk_a),
4502         SH_PFC_PIN_GROUP(msiof3_sync_a),
4503         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4504         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4505         SH_PFC_PIN_GROUP(msiof3_txd_a),
4506         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4507         SH_PFC_PIN_GROUP(msiof3_clk_b),
4508         SH_PFC_PIN_GROUP(msiof3_sync_b),
4509         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4510         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4511         SH_PFC_PIN_GROUP(msiof3_txd_b),
4512         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4513         SH_PFC_PIN_GROUP(msiof3_clk_c),
4514         SH_PFC_PIN_GROUP(msiof3_sync_c),
4515         SH_PFC_PIN_GROUP(msiof3_txd_c),
4516         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4517         SH_PFC_PIN_GROUP(msiof3_clk_d),
4518         SH_PFC_PIN_GROUP(msiof3_sync_d),
4519         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4520         SH_PFC_PIN_GROUP(msiof3_txd_d),
4521         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4522         SH_PFC_PIN_GROUP(msiof3_clk_e),
4523         SH_PFC_PIN_GROUP(msiof3_sync_e),
4524         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4525         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4526         SH_PFC_PIN_GROUP(msiof3_txd_e),
4527         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4528         SH_PFC_PIN_GROUP(pwm0),
4529         SH_PFC_PIN_GROUP(pwm1_a),
4530         SH_PFC_PIN_GROUP(pwm1_b),
4531         SH_PFC_PIN_GROUP(pwm2_a),
4532         SH_PFC_PIN_GROUP(pwm2_b),
4533         SH_PFC_PIN_GROUP(pwm3_a),
4534         SH_PFC_PIN_GROUP(pwm3_b),
4535         SH_PFC_PIN_GROUP(pwm4_a),
4536         SH_PFC_PIN_GROUP(pwm4_b),
4537         SH_PFC_PIN_GROUP(pwm5_a),
4538         SH_PFC_PIN_GROUP(pwm5_b),
4539         SH_PFC_PIN_GROUP(pwm6_a),
4540         SH_PFC_PIN_GROUP(pwm6_b),
4541         SH_PFC_PIN_GROUP(sata0_devslp_a),
4542         SH_PFC_PIN_GROUP(sata0_devslp_b),
4543         SH_PFC_PIN_GROUP(scif0_data),
4544         SH_PFC_PIN_GROUP(scif0_clk),
4545         SH_PFC_PIN_GROUP(scif0_ctrl),
4546         SH_PFC_PIN_GROUP(scif1_data_a),
4547         SH_PFC_PIN_GROUP(scif1_clk),
4548         SH_PFC_PIN_GROUP(scif1_ctrl),
4549         SH_PFC_PIN_GROUP(scif1_data_b),
4550         SH_PFC_PIN_GROUP(scif2_data_a),
4551         SH_PFC_PIN_GROUP(scif2_clk),
4552         SH_PFC_PIN_GROUP(scif2_data_b),
4553         SH_PFC_PIN_GROUP(scif3_data_a),
4554         SH_PFC_PIN_GROUP(scif3_clk),
4555         SH_PFC_PIN_GROUP(scif3_ctrl),
4556         SH_PFC_PIN_GROUP(scif3_data_b),
4557         SH_PFC_PIN_GROUP(scif4_data_a),
4558         SH_PFC_PIN_GROUP(scif4_clk_a),
4559         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4560         SH_PFC_PIN_GROUP(scif4_data_b),
4561         SH_PFC_PIN_GROUP(scif4_clk_b),
4562         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4563         SH_PFC_PIN_GROUP(scif4_data_c),
4564         SH_PFC_PIN_GROUP(scif4_clk_c),
4565         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4566         SH_PFC_PIN_GROUP(scif5_data_a),
4567         SH_PFC_PIN_GROUP(scif5_clk_a),
4568         SH_PFC_PIN_GROUP(scif5_data_b),
4569         SH_PFC_PIN_GROUP(scif5_clk_b),
4570         SH_PFC_PIN_GROUP(scif_clk_a),
4571         SH_PFC_PIN_GROUP(scif_clk_b),
4572         SH_PFC_PIN_GROUP(sdhi0_data1),
4573         SH_PFC_PIN_GROUP(sdhi0_data4),
4574         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4575         SH_PFC_PIN_GROUP(sdhi0_cd),
4576         SH_PFC_PIN_GROUP(sdhi0_wp),
4577         SH_PFC_PIN_GROUP(sdhi1_data1),
4578         SH_PFC_PIN_GROUP(sdhi1_data4),
4579         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4580         SH_PFC_PIN_GROUP(sdhi1_cd),
4581         SH_PFC_PIN_GROUP(sdhi1_wp),
4582         SH_PFC_PIN_GROUP(sdhi2_data1),
4583         SH_PFC_PIN_GROUP(sdhi2_data4),
4584         SH_PFC_PIN_GROUP(sdhi2_data8),
4585         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4586         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4587         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4588         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4589         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4590         SH_PFC_PIN_GROUP(sdhi2_ds),
4591         SH_PFC_PIN_GROUP(sdhi3_data1),
4592         SH_PFC_PIN_GROUP(sdhi3_data4),
4593         SH_PFC_PIN_GROUP(sdhi3_data8),
4594         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4595         SH_PFC_PIN_GROUP(sdhi3_cd),
4596         SH_PFC_PIN_GROUP(sdhi3_wp),
4597         SH_PFC_PIN_GROUP(sdhi3_ds),
4598         SH_PFC_PIN_GROUP(ssi0_data),
4599         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4600         SH_PFC_PIN_GROUP(ssi1_data_a),
4601         SH_PFC_PIN_GROUP(ssi1_data_b),
4602         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4603         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4604         SH_PFC_PIN_GROUP(ssi2_data_a),
4605         SH_PFC_PIN_GROUP(ssi2_data_b),
4606         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4607         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4608         SH_PFC_PIN_GROUP(ssi3_data),
4609         SH_PFC_PIN_GROUP(ssi349_ctrl),
4610         SH_PFC_PIN_GROUP(ssi4_data),
4611         SH_PFC_PIN_GROUP(ssi4_ctrl),
4612         SH_PFC_PIN_GROUP(ssi5_data),
4613         SH_PFC_PIN_GROUP(ssi5_ctrl),
4614         SH_PFC_PIN_GROUP(ssi6_data),
4615         SH_PFC_PIN_GROUP(ssi6_ctrl),
4616         SH_PFC_PIN_GROUP(ssi7_data),
4617         SH_PFC_PIN_GROUP(ssi78_ctrl),
4618         SH_PFC_PIN_GROUP(ssi8_data),
4619         SH_PFC_PIN_GROUP(ssi9_data_a),
4620         SH_PFC_PIN_GROUP(ssi9_data_b),
4621         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4622         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4623         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4624         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4625         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4626         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4627         SH_PFC_PIN_GROUP(usb0),
4628         SH_PFC_PIN_GROUP(usb1),
4629         SH_PFC_PIN_GROUP(usb30),
4630         VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4631         VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4632         VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4633         VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4634         SH_PFC_PIN_GROUP(vin4_data18_a),
4635         VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4636         VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4637         VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4638         VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4639         VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4640         VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4641         SH_PFC_PIN_GROUP(vin4_data18_b),
4642         VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4643         VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4644         SH_PFC_PIN_GROUP(vin4_sync),
4645         SH_PFC_PIN_GROUP(vin4_field),
4646         SH_PFC_PIN_GROUP(vin4_clkenb),
4647         SH_PFC_PIN_GROUP(vin4_clk),
4648         VIN_DATA_PIN_GROUP(vin5_data, 8),
4649         VIN_DATA_PIN_GROUP(vin5_data, 10),
4650         VIN_DATA_PIN_GROUP(vin5_data, 12),
4651         VIN_DATA_PIN_GROUP(vin5_data, 16),
4652         SH_PFC_PIN_GROUP(vin5_sync),
4653         SH_PFC_PIN_GROUP(vin5_field),
4654         SH_PFC_PIN_GROUP(vin5_clkenb),
4655         SH_PFC_PIN_GROUP(vin5_clk),
4656 };
4657
4658 static const char * const audio_clk_groups[] = {
4659         "audio_clk_a_a",
4660         "audio_clk_a_b",
4661         "audio_clk_a_c",
4662         "audio_clk_b_a",
4663         "audio_clk_b_b",
4664         "audio_clk_c_a",
4665         "audio_clk_c_b",
4666         "audio_clkout_a",
4667         "audio_clkout_b",
4668         "audio_clkout_c",
4669         "audio_clkout_d",
4670         "audio_clkout1_a",
4671         "audio_clkout1_b",
4672         "audio_clkout2_a",
4673         "audio_clkout2_b",
4674         "audio_clkout3_a",
4675         "audio_clkout3_b",
4676 };
4677
4678 static const char * const avb_groups[] = {
4679         "avb_link",
4680         "avb_magic",
4681         "avb_phy_int",
4682         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4683         "avb_mdio",
4684         "avb_mii",
4685         "avb_avtp_pps",
4686         "avb_avtp_match_a",
4687         "avb_avtp_capture_a",
4688         "avb_avtp_match_b",
4689         "avb_avtp_capture_b",
4690 };
4691
4692 static const char * const can0_groups[] = {
4693         "can0_data_a",
4694         "can0_data_b",
4695 };
4696
4697 static const char * const can1_groups[] = {
4698         "can1_data",
4699 };
4700
4701 static const char * const can_clk_groups[] = {
4702         "can_clk",
4703 };
4704
4705 static const char * const canfd0_groups[] = {
4706         "canfd0_data_a",
4707         "canfd0_data_b",
4708 };
4709
4710 static const char * const canfd1_groups[] = {
4711         "canfd1_data",
4712 };
4713
4714 static const char * const drif0_groups[] = {
4715         "drif0_ctrl_a",
4716         "drif0_data0_a",
4717         "drif0_data1_a",
4718         "drif0_ctrl_b",
4719         "drif0_data0_b",
4720         "drif0_data1_b",
4721         "drif0_ctrl_c",
4722         "drif0_data0_c",
4723         "drif0_data1_c",
4724 };
4725
4726 static const char * const drif1_groups[] = {
4727         "drif1_ctrl_a",
4728         "drif1_data0_a",
4729         "drif1_data1_a",
4730         "drif1_ctrl_b",
4731         "drif1_data0_b",
4732         "drif1_data1_b",
4733         "drif1_ctrl_c",
4734         "drif1_data0_c",
4735         "drif1_data1_c",
4736 };
4737
4738 static const char * const drif2_groups[] = {
4739         "drif2_ctrl_a",
4740         "drif2_data0_a",
4741         "drif2_data1_a",
4742         "drif2_ctrl_b",
4743         "drif2_data0_b",
4744         "drif2_data1_b",
4745 };
4746
4747 static const char * const drif3_groups[] = {
4748         "drif3_ctrl_a",
4749         "drif3_data0_a",
4750         "drif3_data1_a",
4751         "drif3_ctrl_b",
4752         "drif3_data0_b",
4753         "drif3_data1_b",
4754 };
4755
4756 static const char * const du_groups[] = {
4757         "du_rgb666",
4758         "du_rgb888",
4759         "du_clk_out_0",
4760         "du_clk_out_1",
4761         "du_sync",
4762         "du_oddf",
4763         "du_cde",
4764         "du_disp",
4765 };
4766
4767 static const char * const hscif0_groups[] = {
4768         "hscif0_data",
4769         "hscif0_clk",
4770         "hscif0_ctrl",
4771 };
4772
4773 static const char * const hscif1_groups[] = {
4774         "hscif1_data_a",
4775         "hscif1_clk_a",
4776         "hscif1_ctrl_a",
4777         "hscif1_data_b",
4778         "hscif1_clk_b",
4779         "hscif1_ctrl_b",
4780 };
4781
4782 static const char * const hscif2_groups[] = {
4783         "hscif2_data_a",
4784         "hscif2_clk_a",
4785         "hscif2_ctrl_a",
4786         "hscif2_data_b",
4787         "hscif2_clk_b",
4788         "hscif2_ctrl_b",
4789         "hscif2_data_c",
4790         "hscif2_clk_c",
4791         "hscif2_ctrl_c",
4792 };
4793
4794 static const char * const hscif3_groups[] = {
4795         "hscif3_data_a",
4796         "hscif3_clk",
4797         "hscif3_ctrl",
4798         "hscif3_data_b",
4799         "hscif3_data_c",
4800         "hscif3_data_d",
4801 };
4802
4803 static const char * const hscif4_groups[] = {
4804         "hscif4_data_a",
4805         "hscif4_clk",
4806         "hscif4_ctrl",
4807         "hscif4_data_b",
4808 };
4809
4810 static const char * const i2c1_groups[] = {
4811         "i2c1_a",
4812         "i2c1_b",
4813 };
4814
4815 static const char * const i2c2_groups[] = {
4816         "i2c2_a",
4817         "i2c2_b",
4818 };
4819
4820 static const char * const i2c6_groups[] = {
4821         "i2c6_a",
4822         "i2c6_b",
4823         "i2c6_c",
4824 };
4825
4826 static const char * const intc_ex_groups[] = {
4827         "intc_ex_irq0",
4828         "intc_ex_irq1",
4829         "intc_ex_irq2",
4830         "intc_ex_irq3",
4831         "intc_ex_irq4",
4832         "intc_ex_irq5",
4833 };
4834
4835 static const char * const msiof0_groups[] = {
4836         "msiof0_clk",
4837         "msiof0_sync",
4838         "msiof0_ss1",
4839         "msiof0_ss2",
4840         "msiof0_txd",
4841         "msiof0_rxd",
4842 };
4843
4844 static const char * const msiof1_groups[] = {
4845         "msiof1_clk_a",
4846         "msiof1_sync_a",
4847         "msiof1_ss1_a",
4848         "msiof1_ss2_a",
4849         "msiof1_txd_a",
4850         "msiof1_rxd_a",
4851         "msiof1_clk_b",
4852         "msiof1_sync_b",
4853         "msiof1_ss1_b",
4854         "msiof1_ss2_b",
4855         "msiof1_txd_b",
4856         "msiof1_rxd_b",
4857         "msiof1_clk_c",
4858         "msiof1_sync_c",
4859         "msiof1_ss1_c",
4860         "msiof1_ss2_c",
4861         "msiof1_txd_c",
4862         "msiof1_rxd_c",
4863         "msiof1_clk_d",
4864         "msiof1_sync_d",
4865         "msiof1_ss1_d",
4866         "msiof1_ss2_d",
4867         "msiof1_txd_d",
4868         "msiof1_rxd_d",
4869         "msiof1_clk_e",
4870         "msiof1_sync_e",
4871         "msiof1_ss1_e",
4872         "msiof1_ss2_e",
4873         "msiof1_txd_e",
4874         "msiof1_rxd_e",
4875         "msiof1_clk_f",
4876         "msiof1_sync_f",
4877         "msiof1_ss1_f",
4878         "msiof1_ss2_f",
4879         "msiof1_txd_f",
4880         "msiof1_rxd_f",
4881         "msiof1_clk_g",
4882         "msiof1_sync_g",
4883         "msiof1_ss1_g",
4884         "msiof1_ss2_g",
4885         "msiof1_txd_g",
4886         "msiof1_rxd_g",
4887 };
4888
4889 static const char * const msiof2_groups[] = {
4890         "msiof2_clk_a",
4891         "msiof2_sync_a",
4892         "msiof2_ss1_a",
4893         "msiof2_ss2_a",
4894         "msiof2_txd_a",
4895         "msiof2_rxd_a",
4896         "msiof2_clk_b",
4897         "msiof2_sync_b",
4898         "msiof2_ss1_b",
4899         "msiof2_ss2_b",
4900         "msiof2_txd_b",
4901         "msiof2_rxd_b",
4902         "msiof2_clk_c",
4903         "msiof2_sync_c",
4904         "msiof2_ss1_c",
4905         "msiof2_ss2_c",
4906         "msiof2_txd_c",
4907         "msiof2_rxd_c",
4908         "msiof2_clk_d",
4909         "msiof2_sync_d",
4910         "msiof2_ss1_d",
4911         "msiof2_ss2_d",
4912         "msiof2_txd_d",
4913         "msiof2_rxd_d",
4914 };
4915
4916 static const char * const msiof3_groups[] = {
4917         "msiof3_clk_a",
4918         "msiof3_sync_a",
4919         "msiof3_ss1_a",
4920         "msiof3_ss2_a",
4921         "msiof3_txd_a",
4922         "msiof3_rxd_a",
4923         "msiof3_clk_b",
4924         "msiof3_sync_b",
4925         "msiof3_ss1_b",
4926         "msiof3_ss2_b",
4927         "msiof3_txd_b",
4928         "msiof3_rxd_b",
4929         "msiof3_clk_c",
4930         "msiof3_sync_c",
4931         "msiof3_txd_c",
4932         "msiof3_rxd_c",
4933         "msiof3_clk_d",
4934         "msiof3_sync_d",
4935         "msiof3_ss1_d",
4936         "msiof3_txd_d",
4937         "msiof3_rxd_d",
4938         "msiof3_clk_e",
4939         "msiof3_sync_e",
4940         "msiof3_ss1_e",
4941         "msiof3_ss2_e",
4942         "msiof3_txd_e",
4943         "msiof3_rxd_e",
4944 };
4945
4946 static const char * const pwm0_groups[] = {
4947         "pwm0",
4948 };
4949
4950 static const char * const pwm1_groups[] = {
4951         "pwm1_a",
4952         "pwm1_b",
4953 };
4954
4955 static const char * const pwm2_groups[] = {
4956         "pwm2_a",
4957         "pwm2_b",
4958 };
4959
4960 static const char * const pwm3_groups[] = {
4961         "pwm3_a",
4962         "pwm3_b",
4963 };
4964
4965 static const char * const pwm4_groups[] = {
4966         "pwm4_a",
4967         "pwm4_b",
4968 };
4969
4970 static const char * const pwm5_groups[] = {
4971         "pwm5_a",
4972         "pwm5_b",
4973 };
4974
4975 static const char * const pwm6_groups[] = {
4976         "pwm6_a",
4977         "pwm6_b",
4978 };
4979
4980 static const char * const sata0_groups[] = {
4981         "sata0_devslp_a",
4982         "sata0_devslp_b",
4983 };
4984
4985 static const char * const scif0_groups[] = {
4986         "scif0_data",
4987         "scif0_clk",
4988         "scif0_ctrl",
4989 };
4990
4991 static const char * const scif1_groups[] = {
4992         "scif1_data_a",
4993         "scif1_clk",
4994         "scif1_ctrl",
4995         "scif1_data_b",
4996 };
4997 static const char * const scif2_groups[] = {
4998         "scif2_data_a",
4999         "scif2_clk",
5000         "scif2_data_b",
5001 };
5002
5003 static const char * const scif3_groups[] = {
5004         "scif3_data_a",
5005         "scif3_clk",
5006         "scif3_ctrl",
5007         "scif3_data_b",
5008 };
5009
5010 static const char * const scif4_groups[] = {
5011         "scif4_data_a",
5012         "scif4_clk_a",
5013         "scif4_ctrl_a",
5014         "scif4_data_b",
5015         "scif4_clk_b",
5016         "scif4_ctrl_b",
5017         "scif4_data_c",
5018         "scif4_clk_c",
5019         "scif4_ctrl_c",
5020 };
5021
5022 static const char * const scif5_groups[] = {
5023         "scif5_data_a",
5024         "scif5_clk_a",
5025         "scif5_data_b",
5026         "scif5_clk_b",
5027 };
5028
5029 static const char * const scif_clk_groups[] = {
5030         "scif_clk_a",
5031         "scif_clk_b",
5032 };
5033
5034 static const char * const sdhi0_groups[] = {
5035         "sdhi0_data1",
5036         "sdhi0_data4",
5037         "sdhi0_ctrl",
5038         "sdhi0_cd",
5039         "sdhi0_wp",
5040 };
5041
5042 static const char * const sdhi1_groups[] = {
5043         "sdhi1_data1",
5044         "sdhi1_data4",
5045         "sdhi1_ctrl",
5046         "sdhi1_cd",
5047         "sdhi1_wp",
5048 };
5049
5050 static const char * const sdhi2_groups[] = {
5051         "sdhi2_data1",
5052         "sdhi2_data4",
5053         "sdhi2_data8",
5054         "sdhi2_ctrl",
5055         "sdhi2_cd_a",
5056         "sdhi2_wp_a",
5057         "sdhi2_cd_b",
5058         "sdhi2_wp_b",
5059         "sdhi2_ds",
5060 };
5061
5062 static const char * const sdhi3_groups[] = {
5063         "sdhi3_data1",
5064         "sdhi3_data4",
5065         "sdhi3_data8",
5066         "sdhi3_ctrl",
5067         "sdhi3_cd",
5068         "sdhi3_wp",
5069         "sdhi3_ds",
5070 };
5071
5072 static const char * const ssi_groups[] = {
5073         "ssi0_data",
5074         "ssi01239_ctrl",
5075         "ssi1_data_a",
5076         "ssi1_data_b",
5077         "ssi1_ctrl_a",
5078         "ssi1_ctrl_b",
5079         "ssi2_data_a",
5080         "ssi2_data_b",
5081         "ssi2_ctrl_a",
5082         "ssi2_ctrl_b",
5083         "ssi3_data",
5084         "ssi349_ctrl",
5085         "ssi4_data",
5086         "ssi4_ctrl",
5087         "ssi5_data",
5088         "ssi5_ctrl",
5089         "ssi6_data",
5090         "ssi6_ctrl",
5091         "ssi7_data",
5092         "ssi78_ctrl",
5093         "ssi8_data",
5094         "ssi9_data_a",
5095         "ssi9_data_b",
5096         "ssi9_ctrl_a",
5097         "ssi9_ctrl_b",
5098 };
5099
5100 static const char * const tmu_groups[] = {
5101         "tmu_tclk1_a",
5102         "tmu_tclk1_b",
5103         "tmu_tclk2_a",
5104         "tmu_tclk2_b",
5105 };
5106
5107 static const char * const usb0_groups[] = {
5108         "usb0",
5109 };
5110
5111 static const char * const usb1_groups[] = {
5112         "usb1",
5113 };
5114
5115 static const char * const usb30_groups[] = {
5116         "usb30",
5117 };
5118
5119 static const char * const vin4_groups[] = {
5120         "vin4_data8_a",
5121         "vin4_data10_a",
5122         "vin4_data12_a",
5123         "vin4_data16_a",
5124         "vin4_data18_a",
5125         "vin4_data20_a",
5126         "vin4_data24_a",
5127         "vin4_data8_b",
5128         "vin4_data10_b",
5129         "vin4_data12_b",
5130         "vin4_data16_b",
5131         "vin4_data18_b",
5132         "vin4_data20_b",
5133         "vin4_data24_b",
5134         "vin4_sync",
5135         "vin4_field",
5136         "vin4_clkenb",
5137         "vin4_clk",
5138 };
5139
5140 static const char * const vin5_groups[] = {
5141         "vin5_data8",
5142         "vin5_data10",
5143         "vin5_data12",
5144         "vin5_data16",
5145         "vin5_sync",
5146         "vin5_field",
5147         "vin5_clkenb",
5148         "vin5_clk",
5149 };
5150
5151 static const struct sh_pfc_function pinmux_functions[] = {
5152         SH_PFC_FUNCTION(audio_clk),
5153         SH_PFC_FUNCTION(avb),
5154         SH_PFC_FUNCTION(can0),
5155         SH_PFC_FUNCTION(can1),
5156         SH_PFC_FUNCTION(can_clk),
5157         SH_PFC_FUNCTION(canfd0),
5158         SH_PFC_FUNCTION(canfd1),
5159         SH_PFC_FUNCTION(drif0),
5160         SH_PFC_FUNCTION(drif1),
5161         SH_PFC_FUNCTION(drif2),
5162         SH_PFC_FUNCTION(drif3),
5163         SH_PFC_FUNCTION(du),
5164         SH_PFC_FUNCTION(hscif0),
5165         SH_PFC_FUNCTION(hscif1),
5166         SH_PFC_FUNCTION(hscif2),
5167         SH_PFC_FUNCTION(hscif3),
5168         SH_PFC_FUNCTION(hscif4),
5169         SH_PFC_FUNCTION(i2c1),
5170         SH_PFC_FUNCTION(i2c2),
5171         SH_PFC_FUNCTION(i2c6),
5172         SH_PFC_FUNCTION(intc_ex),
5173         SH_PFC_FUNCTION(msiof0),
5174         SH_PFC_FUNCTION(msiof1),
5175         SH_PFC_FUNCTION(msiof2),
5176         SH_PFC_FUNCTION(msiof3),
5177         SH_PFC_FUNCTION(pwm0),
5178         SH_PFC_FUNCTION(pwm1),
5179         SH_PFC_FUNCTION(pwm2),
5180         SH_PFC_FUNCTION(pwm3),
5181         SH_PFC_FUNCTION(pwm4),
5182         SH_PFC_FUNCTION(pwm5),
5183         SH_PFC_FUNCTION(pwm6),
5184         SH_PFC_FUNCTION(sata0),
5185         SH_PFC_FUNCTION(scif0),
5186         SH_PFC_FUNCTION(scif1),
5187         SH_PFC_FUNCTION(scif2),
5188         SH_PFC_FUNCTION(scif3),
5189         SH_PFC_FUNCTION(scif4),
5190         SH_PFC_FUNCTION(scif5),
5191         SH_PFC_FUNCTION(scif_clk),
5192         SH_PFC_FUNCTION(sdhi0),
5193         SH_PFC_FUNCTION(sdhi1),
5194         SH_PFC_FUNCTION(sdhi2),
5195         SH_PFC_FUNCTION(sdhi3),
5196         SH_PFC_FUNCTION(ssi),
5197         SH_PFC_FUNCTION(tmu),
5198         SH_PFC_FUNCTION(usb0),
5199         SH_PFC_FUNCTION(usb1),
5200         SH_PFC_FUNCTION(usb30),
5201         SH_PFC_FUNCTION(vin4),
5202         SH_PFC_FUNCTION(vin5),
5203 };
5204
5205 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5206 #define F_(x, y)        FN_##y
5207 #define FM(x)           FN_##x
5208         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5209                 0, 0,
5210                 0, 0,
5211                 0, 0,
5212                 0, 0,
5213                 0, 0,
5214                 0, 0,
5215                 0, 0,
5216                 0, 0,
5217                 0, 0,
5218                 0, 0,
5219                 0, 0,
5220                 0, 0,
5221                 0, 0,
5222                 0, 0,
5223                 0, 0,
5224                 0, 0,
5225                 GP_0_15_FN,     GPSR0_15,
5226                 GP_0_14_FN,     GPSR0_14,
5227                 GP_0_13_FN,     GPSR0_13,
5228                 GP_0_12_FN,     GPSR0_12,
5229                 GP_0_11_FN,     GPSR0_11,
5230                 GP_0_10_FN,     GPSR0_10,
5231                 GP_0_9_FN,      GPSR0_9,
5232                 GP_0_8_FN,      GPSR0_8,
5233                 GP_0_7_FN,      GPSR0_7,
5234                 GP_0_6_FN,      GPSR0_6,
5235                 GP_0_5_FN,      GPSR0_5,
5236                 GP_0_4_FN,      GPSR0_4,
5237                 GP_0_3_FN,      GPSR0_3,
5238                 GP_0_2_FN,      GPSR0_2,
5239                 GP_0_1_FN,      GPSR0_1,
5240                 GP_0_0_FN,      GPSR0_0, ))
5241         },
5242         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5243                 0, 0,
5244                 0, 0,
5245                 0, 0,
5246                 GP_1_28_FN,     GPSR1_28,
5247                 GP_1_27_FN,     GPSR1_27,
5248                 GP_1_26_FN,     GPSR1_26,
5249                 GP_1_25_FN,     GPSR1_25,
5250                 GP_1_24_FN,     GPSR1_24,
5251                 GP_1_23_FN,     GPSR1_23,
5252                 GP_1_22_FN,     GPSR1_22,
5253                 GP_1_21_FN,     GPSR1_21,
5254                 GP_1_20_FN,     GPSR1_20,
5255                 GP_1_19_FN,     GPSR1_19,
5256                 GP_1_18_FN,     GPSR1_18,
5257                 GP_1_17_FN,     GPSR1_17,
5258                 GP_1_16_FN,     GPSR1_16,
5259                 GP_1_15_FN,     GPSR1_15,
5260                 GP_1_14_FN,     GPSR1_14,
5261                 GP_1_13_FN,     GPSR1_13,
5262                 GP_1_12_FN,     GPSR1_12,
5263                 GP_1_11_FN,     GPSR1_11,
5264                 GP_1_10_FN,     GPSR1_10,
5265                 GP_1_9_FN,      GPSR1_9,
5266                 GP_1_8_FN,      GPSR1_8,
5267                 GP_1_7_FN,      GPSR1_7,
5268                 GP_1_6_FN,      GPSR1_6,
5269                 GP_1_5_FN,      GPSR1_5,
5270                 GP_1_4_FN,      GPSR1_4,
5271                 GP_1_3_FN,      GPSR1_3,
5272                 GP_1_2_FN,      GPSR1_2,
5273                 GP_1_1_FN,      GPSR1_1,
5274                 GP_1_0_FN,      GPSR1_0, ))
5275         },
5276         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5277                 0, 0,
5278                 0, 0,
5279                 0, 0,
5280                 0, 0,
5281                 0, 0,
5282                 0, 0,
5283                 0, 0,
5284                 0, 0,
5285                 0, 0,
5286                 0, 0,
5287                 0, 0,
5288                 0, 0,
5289                 0, 0,
5290                 0, 0,
5291                 0, 0,
5292                 0, 0,
5293                 0, 0,
5294                 GP_2_14_FN,     GPSR2_14,
5295                 GP_2_13_FN,     GPSR2_13,
5296                 GP_2_12_FN,     GPSR2_12,
5297                 GP_2_11_FN,     GPSR2_11,
5298                 GP_2_10_FN,     GPSR2_10,
5299                 GP_2_9_FN,      GPSR2_9,
5300                 GP_2_8_FN,      GPSR2_8,
5301                 GP_2_7_FN,      GPSR2_7,
5302                 GP_2_6_FN,      GPSR2_6,
5303                 GP_2_5_FN,      GPSR2_5,
5304                 GP_2_4_FN,      GPSR2_4,
5305                 GP_2_3_FN,      GPSR2_3,
5306                 GP_2_2_FN,      GPSR2_2,
5307                 GP_2_1_FN,      GPSR2_1,
5308                 GP_2_0_FN,      GPSR2_0, ))
5309         },
5310         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5311                 0, 0,
5312                 0, 0,
5313                 0, 0,
5314                 0, 0,
5315                 0, 0,
5316                 0, 0,
5317                 0, 0,
5318                 0, 0,
5319                 0, 0,
5320                 0, 0,
5321                 0, 0,
5322                 0, 0,
5323                 0, 0,
5324                 0, 0,
5325                 0, 0,
5326                 0, 0,
5327                 GP_3_15_FN,     GPSR3_15,
5328                 GP_3_14_FN,     GPSR3_14,
5329                 GP_3_13_FN,     GPSR3_13,
5330                 GP_3_12_FN,     GPSR3_12,
5331                 GP_3_11_FN,     GPSR3_11,
5332                 GP_3_10_FN,     GPSR3_10,
5333                 GP_3_9_FN,      GPSR3_9,
5334                 GP_3_8_FN,      GPSR3_8,
5335                 GP_3_7_FN,      GPSR3_7,
5336                 GP_3_6_FN,      GPSR3_6,
5337                 GP_3_5_FN,      GPSR3_5,
5338                 GP_3_4_FN,      GPSR3_4,
5339                 GP_3_3_FN,      GPSR3_3,
5340                 GP_3_2_FN,      GPSR3_2,
5341                 GP_3_1_FN,      GPSR3_1,
5342                 GP_3_0_FN,      GPSR3_0, ))
5343         },
5344         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5345                 0, 0,
5346                 0, 0,
5347                 0, 0,
5348                 0, 0,
5349                 0, 0,
5350                 0, 0,
5351                 0, 0,
5352                 0, 0,
5353                 0, 0,
5354                 0, 0,
5355                 0, 0,
5356                 0, 0,
5357                 0, 0,
5358                 0, 0,
5359                 GP_4_17_FN,     GPSR4_17,
5360                 GP_4_16_FN,     GPSR4_16,
5361                 GP_4_15_FN,     GPSR4_15,
5362                 GP_4_14_FN,     GPSR4_14,
5363                 GP_4_13_FN,     GPSR4_13,
5364                 GP_4_12_FN,     GPSR4_12,
5365                 GP_4_11_FN,     GPSR4_11,
5366                 GP_4_10_FN,     GPSR4_10,
5367                 GP_4_9_FN,      GPSR4_9,
5368                 GP_4_8_FN,      GPSR4_8,
5369                 GP_4_7_FN,      GPSR4_7,
5370                 GP_4_6_FN,      GPSR4_6,
5371                 GP_4_5_FN,      GPSR4_5,
5372                 GP_4_4_FN,      GPSR4_4,
5373                 GP_4_3_FN,      GPSR4_3,
5374                 GP_4_2_FN,      GPSR4_2,
5375                 GP_4_1_FN,      GPSR4_1,
5376                 GP_4_0_FN,      GPSR4_0, ))
5377         },
5378         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5379                 0, 0,
5380                 0, 0,
5381                 0, 0,
5382                 0, 0,
5383                 0, 0,
5384                 0, 0,
5385                 GP_5_25_FN,     GPSR5_25,
5386                 GP_5_24_FN,     GPSR5_24,
5387                 GP_5_23_FN,     GPSR5_23,
5388                 GP_5_22_FN,     GPSR5_22,
5389                 GP_5_21_FN,     GPSR5_21,
5390                 GP_5_20_FN,     GPSR5_20,
5391                 GP_5_19_FN,     GPSR5_19,
5392                 GP_5_18_FN,     GPSR5_18,
5393                 GP_5_17_FN,     GPSR5_17,
5394                 GP_5_16_FN,     GPSR5_16,
5395                 GP_5_15_FN,     GPSR5_15,
5396                 GP_5_14_FN,     GPSR5_14,
5397                 GP_5_13_FN,     GPSR5_13,
5398                 GP_5_12_FN,     GPSR5_12,
5399                 GP_5_11_FN,     GPSR5_11,
5400                 GP_5_10_FN,     GPSR5_10,
5401                 GP_5_9_FN,      GPSR5_9,
5402                 GP_5_8_FN,      GPSR5_8,
5403                 GP_5_7_FN,      GPSR5_7,
5404                 GP_5_6_FN,      GPSR5_6,
5405                 GP_5_5_FN,      GPSR5_5,
5406                 GP_5_4_FN,      GPSR5_4,
5407                 GP_5_3_FN,      GPSR5_3,
5408                 GP_5_2_FN,      GPSR5_2,
5409                 GP_5_1_FN,      GPSR5_1,
5410                 GP_5_0_FN,      GPSR5_0, ))
5411         },
5412         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5413                 GP_6_31_FN,     GPSR6_31,
5414                 GP_6_30_FN,     GPSR6_30,
5415                 GP_6_29_FN,     GPSR6_29,
5416                 GP_6_28_FN,     GPSR6_28,
5417                 GP_6_27_FN,     GPSR6_27,
5418                 GP_6_26_FN,     GPSR6_26,
5419                 GP_6_25_FN,     GPSR6_25,
5420                 GP_6_24_FN,     GPSR6_24,
5421                 GP_6_23_FN,     GPSR6_23,
5422                 GP_6_22_FN,     GPSR6_22,
5423                 GP_6_21_FN,     GPSR6_21,
5424                 GP_6_20_FN,     GPSR6_20,
5425                 GP_6_19_FN,     GPSR6_19,
5426                 GP_6_18_FN,     GPSR6_18,
5427                 GP_6_17_FN,     GPSR6_17,
5428                 GP_6_16_FN,     GPSR6_16,
5429                 GP_6_15_FN,     GPSR6_15,
5430                 GP_6_14_FN,     GPSR6_14,
5431                 GP_6_13_FN,     GPSR6_13,
5432                 GP_6_12_FN,     GPSR6_12,
5433                 GP_6_11_FN,     GPSR6_11,
5434                 GP_6_10_FN,     GPSR6_10,
5435                 GP_6_9_FN,      GPSR6_9,
5436                 GP_6_8_FN,      GPSR6_8,
5437                 GP_6_7_FN,      GPSR6_7,
5438                 GP_6_6_FN,      GPSR6_6,
5439                 GP_6_5_FN,      GPSR6_5,
5440                 GP_6_4_FN,      GPSR6_4,
5441                 GP_6_3_FN,      GPSR6_3,
5442                 GP_6_2_FN,      GPSR6_2,
5443                 GP_6_1_FN,      GPSR6_1,
5444                 GP_6_0_FN,      GPSR6_0, ))
5445         },
5446         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5447                 0, 0,
5448                 0, 0,
5449                 0, 0,
5450                 0, 0,
5451                 0, 0,
5452                 0, 0,
5453                 0, 0,
5454                 0, 0,
5455                 0, 0,
5456                 0, 0,
5457                 0, 0,
5458                 0, 0,
5459                 0, 0,
5460                 0, 0,
5461                 0, 0,
5462                 0, 0,
5463                 0, 0,
5464                 0, 0,
5465                 0, 0,
5466                 0, 0,
5467                 0, 0,
5468                 0, 0,
5469                 0, 0,
5470                 0, 0,
5471                 0, 0,
5472                 0, 0,
5473                 0, 0,
5474                 0, 0,
5475                 GP_7_3_FN, GPSR7_3,
5476                 GP_7_2_FN, GPSR7_2,
5477                 GP_7_1_FN, GPSR7_1,
5478                 GP_7_0_FN, GPSR7_0, ))
5479         },
5480 #undef F_
5481 #undef FM
5482
5483 #define F_(x, y)        x,
5484 #define FM(x)           FN_##x,
5485         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5486                 IP0_31_28
5487                 IP0_27_24
5488                 IP0_23_20
5489                 IP0_19_16
5490                 IP0_15_12
5491                 IP0_11_8
5492                 IP0_7_4
5493                 IP0_3_0 ))
5494         },
5495         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5496                 IP1_31_28
5497                 IP1_27_24
5498                 IP1_23_20
5499                 IP1_19_16
5500                 IP1_15_12
5501                 IP1_11_8
5502                 IP1_7_4
5503                 IP1_3_0 ))
5504         },
5505         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5506                 IP2_31_28
5507                 IP2_27_24
5508                 IP2_23_20
5509                 IP2_19_16
5510                 IP2_15_12
5511                 IP2_11_8
5512                 IP2_7_4
5513                 IP2_3_0 ))
5514         },
5515         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5516                 IP3_31_28
5517                 IP3_27_24
5518                 IP3_23_20
5519                 IP3_19_16
5520                 IP3_15_12
5521                 IP3_11_8
5522                 IP3_7_4
5523                 IP3_3_0 ))
5524         },
5525         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5526                 IP4_31_28
5527                 IP4_27_24
5528                 IP4_23_20
5529                 IP4_19_16
5530                 IP4_15_12
5531                 IP4_11_8
5532                 IP4_7_4
5533                 IP4_3_0 ))
5534         },
5535         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5536                 IP5_31_28
5537                 IP5_27_24
5538                 IP5_23_20
5539                 IP5_19_16
5540                 IP5_15_12
5541                 IP5_11_8
5542                 IP5_7_4
5543                 IP5_3_0 ))
5544         },
5545         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5546                 IP6_31_28
5547                 IP6_27_24
5548                 IP6_23_20
5549                 IP6_19_16
5550                 IP6_15_12
5551                 IP6_11_8
5552                 IP6_7_4
5553                 IP6_3_0 ))
5554         },
5555         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5556                 IP7_31_28
5557                 IP7_27_24
5558                 IP7_23_20
5559                 IP7_19_16
5560                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5561                 IP7_11_8
5562                 IP7_7_4
5563                 IP7_3_0 ))
5564         },
5565         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5566                 IP8_31_28
5567                 IP8_27_24
5568                 IP8_23_20
5569                 IP8_19_16
5570                 IP8_15_12
5571                 IP8_11_8
5572                 IP8_7_4
5573                 IP8_3_0 ))
5574         },
5575         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5576                 IP9_31_28
5577                 IP9_27_24
5578                 IP9_23_20
5579                 IP9_19_16
5580                 IP9_15_12
5581                 IP9_11_8
5582                 IP9_7_4
5583                 IP9_3_0 ))
5584         },
5585         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5586                 IP10_31_28
5587                 IP10_27_24
5588                 IP10_23_20
5589                 IP10_19_16
5590                 IP10_15_12
5591                 IP10_11_8
5592                 IP10_7_4
5593                 IP10_3_0 ))
5594         },
5595         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5596                 IP11_31_28
5597                 IP11_27_24
5598                 IP11_23_20
5599                 IP11_19_16
5600                 IP11_15_12
5601                 IP11_11_8
5602                 IP11_7_4
5603                 IP11_3_0 ))
5604         },
5605         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5606                 IP12_31_28
5607                 IP12_27_24
5608                 IP12_23_20
5609                 IP12_19_16
5610                 IP12_15_12
5611                 IP12_11_8
5612                 IP12_7_4
5613                 IP12_3_0 ))
5614         },
5615         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5616                 IP13_31_28
5617                 IP13_27_24
5618                 IP13_23_20
5619                 IP13_19_16
5620                 IP13_15_12
5621                 IP13_11_8
5622                 IP13_7_4
5623                 IP13_3_0 ))
5624         },
5625         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5626                 IP14_31_28
5627                 IP14_27_24
5628                 IP14_23_20
5629                 IP14_19_16
5630                 IP14_15_12
5631                 IP14_11_8
5632                 IP14_7_4
5633                 IP14_3_0 ))
5634         },
5635         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5636                 IP15_31_28
5637                 IP15_27_24
5638                 IP15_23_20
5639                 IP15_19_16
5640                 IP15_15_12
5641                 IP15_11_8
5642                 IP15_7_4
5643                 IP15_3_0 ))
5644         },
5645         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5646                 IP16_31_28
5647                 IP16_27_24
5648                 IP16_23_20
5649                 IP16_19_16
5650                 IP16_15_12
5651                 IP16_11_8
5652                 IP16_7_4
5653                 IP16_3_0 ))
5654         },
5655         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5656                 IP17_31_28
5657                 IP17_27_24
5658                 IP17_23_20
5659                 IP17_19_16
5660                 IP17_15_12
5661                 IP17_11_8
5662                 IP17_7_4
5663                 IP17_3_0 ))
5664         },
5665         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5666                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5667                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5668                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5669                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5670                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5671                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5672                 IP18_7_4
5673                 IP18_3_0 ))
5674         },
5675 #undef F_
5676 #undef FM
5677
5678 #define F_(x, y)        x,
5679 #define FM(x)           FN_##x,
5680         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5681                              GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5682                                    1, 1, 1, 2, 2, 1, 2, 3),
5683                              GROUP(
5684                 MOD_SEL0_31_30_29
5685                 MOD_SEL0_28_27
5686                 MOD_SEL0_26_25_24
5687                 MOD_SEL0_23
5688                 MOD_SEL0_22
5689                 MOD_SEL0_21
5690                 MOD_SEL0_20
5691                 MOD_SEL0_19
5692                 MOD_SEL0_18_17
5693                 MOD_SEL0_16
5694                 0, 0, /* RESERVED 15 */
5695                 MOD_SEL0_14_13
5696                 MOD_SEL0_12
5697                 MOD_SEL0_11
5698                 MOD_SEL0_10
5699                 MOD_SEL0_9_8
5700                 MOD_SEL0_7_6
5701                 MOD_SEL0_5
5702                 MOD_SEL0_4_3
5703                 /* RESERVED 2, 1, 0 */
5704                 0, 0, 0, 0, 0, 0, 0, 0 ))
5705         },
5706         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5707                              GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5708                                    1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5709                              GROUP(
5710                 MOD_SEL1_31_30
5711                 MOD_SEL1_29_28_27
5712                 MOD_SEL1_26
5713                 MOD_SEL1_25_24
5714                 MOD_SEL1_23_22_21
5715                 MOD_SEL1_20
5716                 MOD_SEL1_19
5717                 MOD_SEL1_18_17
5718                 MOD_SEL1_16
5719                 MOD_SEL1_15_14
5720                 MOD_SEL1_13
5721                 MOD_SEL1_12
5722                 MOD_SEL1_11
5723                 MOD_SEL1_10
5724                 MOD_SEL1_9
5725                 0, 0, 0, 0, /* RESERVED 8, 7 */
5726                 MOD_SEL1_6
5727                 MOD_SEL1_5
5728                 MOD_SEL1_4
5729                 MOD_SEL1_3
5730                 MOD_SEL1_2
5731                 MOD_SEL1_1
5732                 MOD_SEL1_0 ))
5733         },
5734         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5735                              GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5736                                    1, 4, 4, 4, 3, 1),
5737                              GROUP(
5738                 MOD_SEL2_31
5739                 MOD_SEL2_30
5740                 MOD_SEL2_29
5741                 MOD_SEL2_28_27
5742                 MOD_SEL2_26
5743                 MOD_SEL2_25_24_23
5744                 MOD_SEL2_22
5745                 MOD_SEL2_21
5746                 MOD_SEL2_20
5747                 MOD_SEL2_19
5748                 MOD_SEL2_18
5749                 MOD_SEL2_17
5750                 /* RESERVED 16 */
5751                 0, 0,
5752                 /* RESERVED 15, 14, 13, 12 */
5753                 0, 0, 0, 0, 0, 0, 0, 0,
5754                 0, 0, 0, 0, 0, 0, 0, 0,
5755                 /* RESERVED 11, 10, 9, 8 */
5756                 0, 0, 0, 0, 0, 0, 0, 0,
5757                 0, 0, 0, 0, 0, 0, 0, 0,
5758                 /* RESERVED 7, 6, 5, 4 */
5759                 0, 0, 0, 0, 0, 0, 0, 0,
5760                 0, 0, 0, 0, 0, 0, 0, 0,
5761                 /* RESERVED 3, 2, 1 */
5762                 0, 0, 0, 0, 0, 0, 0, 0,
5763                 MOD_SEL2_0 ))
5764         },
5765         { },
5766 };
5767
5768 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5769         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5770                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5771                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5772                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5773                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5774                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5775                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5776                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5777                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5778         } },
5779         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5780                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5781                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5782                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5783                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5784                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5785                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5786                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5787                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5788         } },
5789         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5790                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5791                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5792                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5793                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5794                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5795                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5796                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5797                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5798         } },
5799         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5800                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5801                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5802                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5803                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5804                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5805                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5806                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5807                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5808         } },
5809         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5810                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5811                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5812                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5813                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5814                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5815                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5816                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5817                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5818         } },
5819         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5820                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5821                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5822                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5823                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5824                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5825                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5826                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5827                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5828         } },
5829         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5830                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5831                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5832                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5833                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5834                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5835                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5836                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5837                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5838         } },
5839         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5840                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5841                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5842                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5843                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5844                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5845                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5846                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5847                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5848         } },
5849         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5850                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5851                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5852                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5853                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5854                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5855                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5856                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5857                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5858         } },
5859         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5860                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5861                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5862                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5863                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5864                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5865                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5866                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5867                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5868         } },
5869         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5870                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5871                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5872                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5873                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5874                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5875                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5876                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5877                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5878         } },
5879         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5880                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5881                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5882                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5883                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5884                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* GP7_02 */
5885                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5886                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5887                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5888         } },
5889         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5890                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN3 */
5891                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5892                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5893         } },
5894         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5895                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5896                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5897                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5898                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5899                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5900                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5901                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5902                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5903         } },
5904         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5905                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5906                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5907                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5908                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5909                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5910                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5911                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5912                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5913         } },
5914         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5915                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5916                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5917                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5918                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5919                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5920                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5921                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5922                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5923         } },
5924         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5925                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5926                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5927                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5928                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5929                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5930                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5931                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5932                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5933         } },
5934         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5935                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5936                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5937                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5938                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5939                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5940                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5941                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5942                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5943         } },
5944         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5945                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5946                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5947                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5948                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5949                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5950                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5951                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5952                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5953         } },
5954         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5955                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5956                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5957                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5958                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5959                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5960                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5961                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5962                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5963         } },
5964         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5965                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5966                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5967                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5968                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5969                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5970                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5971                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5972                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5973         } },
5974         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5975                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5976                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5977                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5978                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5979                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5980                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5981                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5982                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5983         } },
5984         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5985                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5986                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5987                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5988                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5989                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5990                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5991                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5992                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5993         } },
5994         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5995                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5996                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5997                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5998                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5999                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
6000                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
6001                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
6002                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
6003         } },
6004         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6005                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
6006                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
6007                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
6008                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
6009                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
6010                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
6011                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
6012         } },
6013         { },
6014 };
6015
6016 enum ioctrl_regs {
6017         POCCTRL,
6018         TDSELCTRL,
6019 };
6020
6021 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6022         [POCCTRL] = { 0xe6060380, },
6023         [TDSELCTRL] = { 0xe60603c0, },
6024         { /* sentinel */ },
6025 };
6026
6027 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6028 {
6029         int bit = -EINVAL;
6030
6031         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6032
6033         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6034                 bit = pin & 0x1f;
6035
6036         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6037                 bit = (pin & 0x1f) + 12;
6038
6039         return bit;
6040 }
6041
6042 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6043         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6044                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
6045                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
6046                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
6047                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
6048                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
6049                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
6050                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
6051                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
6052                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
6053                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
6054                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
6055                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
6056                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
6057                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
6058                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
6059                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
6060                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
6061                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
6062                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
6063                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
6064                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
6065                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
6066                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
6067                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
6068                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
6069                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
6070                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
6071                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
6072                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
6073                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
6074                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
6075                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
6076         } },
6077         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6078                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
6079                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
6080                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
6081                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
6082                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
6083                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
6084                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
6085                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
6086                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
6087                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
6088                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
6089                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
6090                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
6091                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
6092                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
6093                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
6094                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
6095                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
6096                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
6097                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
6098                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
6099                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
6100                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
6101                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
6102                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
6103                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
6104                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
6105                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
6106                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
6107                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
6108                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
6109                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
6110         } },
6111         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6112                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
6113                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
6114                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
6115                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
6116                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
6117                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
6118                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
6119                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
6120                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
6121                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
6122                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
6123                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
6124                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
6125                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
6126                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
6127                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
6128                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
6129                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
6130                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
6131                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
6132                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
6133                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
6134                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
6135                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
6136                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
6137                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
6138                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
6139                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
6140                 [28] = RCAR_GP_PIN(7,  2),      /* GP7_02 */
6141                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
6142                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
6143                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
6144         } },
6145         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6146                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN3 */
6147                 [ 1] = PIN_NONE,
6148                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
6149                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
6150                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
6151                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
6152                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
6153                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
6154                 [ 8] = PIN_NONE,
6155                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
6156                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
6157                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
6158                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
6159                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
6160                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
6161                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
6162                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
6163                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
6164                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
6165                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
6166                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
6167                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
6168                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
6169                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
6170                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
6171                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
6172                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
6173                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
6174                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
6175                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
6176                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
6177                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
6178         } },
6179         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6180                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
6181                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
6182                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
6183                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
6184                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
6185                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
6186                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
6187                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
6188                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
6189                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
6190                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
6191                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
6192                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
6193                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
6194                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
6195                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
6196                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
6197                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
6198                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
6199                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
6200                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
6201                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
6202                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
6203                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
6204                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
6205                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
6206                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
6207                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
6208                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
6209                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
6210                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
6211                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
6212         } },
6213         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6214                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
6215                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
6216                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
6217                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
6218                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
6219                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
6220                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
6221                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
6222                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
6223                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
6224                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
6225                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
6226                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
6227                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
6228                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
6229                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
6230                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
6231                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
6232                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
6233                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
6234                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
6235                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
6236                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
6237                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
6238                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
6239                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
6240                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
6241                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
6242                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
6243                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
6244                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
6245                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
6246         } },
6247         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6248                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
6249                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
6250                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
6251                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
6252                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
6253                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
6254                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
6255                 [ 7] = PIN_NONE,
6256                 [ 8] = PIN_NONE,
6257                 [ 9] = PIN_NONE,
6258                 [10] = PIN_NONE,
6259                 [11] = PIN_NONE,
6260                 [12] = PIN_NONE,
6261                 [13] = PIN_NONE,
6262                 [14] = PIN_NONE,
6263                 [15] = PIN_NONE,
6264                 [16] = PIN_NONE,
6265                 [17] = PIN_NONE,
6266                 [18] = PIN_NONE,
6267                 [19] = PIN_NONE,
6268                 [20] = PIN_NONE,
6269                 [21] = PIN_NONE,
6270                 [22] = PIN_NONE,
6271                 [23] = PIN_NONE,
6272                 [24] = PIN_NONE,
6273                 [25] = PIN_NONE,
6274                 [26] = PIN_NONE,
6275                 [27] = PIN_NONE,
6276                 [28] = PIN_NONE,
6277                 [29] = PIN_NONE,
6278                 [30] = PIN_NONE,
6279                 [31] = PIN_NONE,
6280         } },
6281         { /* sentinel */ },
6282 };
6283
6284 static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
6285                                             unsigned int pin)
6286 {
6287         const struct pinmux_bias_reg *reg;
6288         unsigned int bit;
6289
6290         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6291         if (!reg)
6292                 return PIN_CONFIG_BIAS_DISABLE;
6293
6294         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6295                 return PIN_CONFIG_BIAS_DISABLE;
6296         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6297                 return PIN_CONFIG_BIAS_PULL_UP;
6298         else
6299                 return PIN_CONFIG_BIAS_PULL_DOWN;
6300 }
6301
6302 static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6303                                    unsigned int bias)
6304 {
6305         const struct pinmux_bias_reg *reg;
6306         u32 enable, updown;
6307         unsigned int bit;
6308
6309         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6310         if (!reg)
6311                 return;
6312
6313         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6314         if (bias != PIN_CONFIG_BIAS_DISABLE)
6315                 enable |= BIT(bit);
6316
6317         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6318         if (bias == PIN_CONFIG_BIAS_PULL_UP)
6319                 updown |= BIT(bit);
6320
6321         sh_pfc_write(pfc, reg->pud, updown);
6322         sh_pfc_write(pfc, reg->puen, enable);
6323 }
6324
6325 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6326         .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6327         .get_bias = r8a77965_pinmux_get_bias,
6328         .set_bias = r8a77965_pinmux_set_bias,
6329 };
6330
6331 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6332         .name = "r8a77965_pfc",
6333         .ops = &r8a77965_pinmux_ops,
6334         .unlock_reg = 0xe6060000, /* PMMR */
6335
6336         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6337
6338         .pins = pinmux_pins,
6339         .nr_pins = ARRAY_SIZE(pinmux_pins),
6340         .groups = pinmux_groups,
6341         .nr_groups = ARRAY_SIZE(pinmux_groups),
6342         .functions = pinmux_functions,
6343         .nr_functions = ARRAY_SIZE(pinmux_functions),
6344
6345         .cfg_regs = pinmux_config_regs,
6346         .drive_regs = pinmux_drive_regs,
6347         .bias_regs = pinmux_bias_regs,
6348         .ioctrl_regs = pinmux_ioctrl_regs,
6349
6350         .pinmux_data = pinmux_data,
6351         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6352 };