drivers/pinctrl/sh-pfc/pfc-r8a77965.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A77965 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
   6  * Copyright (C) 2016 Renesas Electronics Corp.
   7  *
   8  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
   9  *
  10  * R-Car Gen3 processor support - PFC hardware block.
  11  *
  12  * Copyright (C) 2015  Renesas Electronics Corporation
  13  */
  14
  15 #include <linux/kernel.h>
  16
  17 #include "core.h"
  18 #include "sh_pfc.h"
  19
  20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  21                    SH_PFC_PIN_CFG_PULL_UP | \
  22                    SH_PFC_PIN_CFG_PULL_DOWN)
  23
  24 #define CPU_ALL_PORT(fn, sfx)                                           \
  25         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  26         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  27         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  29         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  30         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  31         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  34         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  35         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  36         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  37 /*
  38  * F_() : just information
  39  * FM() : macro for FN_xxx / xxx_MARK
  40  */
  41
  42 /* GPSR0 */
  43 #define GPSR0_15        F_(D15,                 IP7_11_8)
  44 #define GPSR0_14        F_(D14,                 IP7_7_4)
  45 #define GPSR0_13        F_(D13,                 IP7_3_0)
  46 #define GPSR0_12        F_(D12,                 IP6_31_28)
  47 #define GPSR0_11        F_(D11,                 IP6_27_24)
  48 #define GPSR0_10        F_(D10,                 IP6_23_20)
  49 #define GPSR0_9         F_(D9,                  IP6_19_16)
  50 #define GPSR0_8         F_(D8,                  IP6_15_12)
  51 #define GPSR0_7         F_(D7,                  IP6_11_8)
  52 #define GPSR0_6         F_(D6,                  IP6_7_4)
  53 #define GPSR0_5         F_(D5,                  IP6_3_0)
  54 #define GPSR0_4         F_(D4,                  IP5_31_28)
  55 #define GPSR0_3         F_(D3,                  IP5_27_24)
  56 #define GPSR0_2         F_(D2,                  IP5_23_20)
  57 #define GPSR0_1         F_(D1,                  IP5_19_16)
  58 #define GPSR0_0         F_(D0,                  IP5_15_12)
  59
  60 /* GPSR1 */
  61 #define GPSR1_28        FM(CLKOUT)
  62 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  63 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  64 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  65 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  66 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  67 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  68 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  69 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  70 #define GPSR1_19        F_(A19,                 IP4_11_8)
  71 #define GPSR1_18        F_(A18,                 IP4_7_4)
  72 #define GPSR1_17        F_(A17,                 IP4_3_0)
  73 #define GPSR1_16        F_(A16,                 IP3_31_28)
  74 #define GPSR1_15        F_(A15,                 IP3_27_24)
  75 #define GPSR1_14        F_(A14,                 IP3_23_20)
  76 #define GPSR1_13        F_(A13,                 IP3_19_16)
  77 #define GPSR1_12        F_(A12,                 IP3_15_12)
  78 #define GPSR1_11        F_(A11,                 IP3_11_8)
  79 #define GPSR1_10        F_(A10,                 IP3_7_4)
  80 #define GPSR1_9         F_(A9,                  IP3_3_0)
  81 #define GPSR1_8         F_(A8,                  IP2_31_28)
  82 #define GPSR1_7         F_(A7,                  IP2_27_24)
  83 #define GPSR1_6         F_(A6,                  IP2_23_20)
  84 #define GPSR1_5         F_(A5,                  IP2_19_16)
  85 #define GPSR1_4         F_(A4,                  IP2_15_12)
  86 #define GPSR1_3         F_(A3,                  IP2_11_8)
  87 #define GPSR1_2         F_(A2,                  IP2_7_4)
  88 #define GPSR1_1         F_(A1,                  IP2_3_0)
  89 #define GPSR1_0         F_(A0,                  IP1_31_28)
  90
  91 /* GPSR2 */
  92 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  93 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  94 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  95 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  96 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  97 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
  98 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
  99 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 100 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 101 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 102 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 103 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 104 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 105 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 106 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 107
 108 /* GPSR3 */
 109 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 110 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 111 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 112 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 113 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 114 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 115 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 116 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 117 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 118 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 119 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 120 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 121 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 122 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 123 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 124 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 125
 126 /* GPSR4 */
 127 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 128 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 129 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 130 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 131 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 132 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 133 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 134 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 135 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 136 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 137 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 138 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 139 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 140 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 141 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 142 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 143 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 144 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 145
 146 /* GPSR5 */
 147 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 148 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 149 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 150 #define GPSR5_22        FM(MSIOF0_RXD)
 151 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 152 #define GPSR5_20        FM(MSIOF0_TXD)
 153 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 154 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 155 #define GPSR5_17        FM(MSIOF0_SCK)
 156 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 157 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 158 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 159 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 160 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 161 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 162 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 163 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 164 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 165 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 166 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 167 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 168 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 169 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 170 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 171 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 172 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 173
 174 /* GPSR6 */
 175 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 176 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 177 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 178 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 179 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 180 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 181 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 182 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 183 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 184 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 185 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 186 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 187 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 188 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 189 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 190 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 191 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 192 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 193 #define GPSR6_13        FM(SSI_SDATA5)
 194 #define GPSR6_12        FM(SSI_WS5)
 195 #define GPSR6_11        FM(SSI_SCK5)
 196 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 197 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 198 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 199 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 200 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 201 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 202 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 203 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 204 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 205 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 206 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 207
 208 /* GPSR7 */
 209 #define GPSR7_3         FM(GP7_03)
 210 #define GPSR7_2         FM(HDMI0_CEC)
 211 #define GPSR7_1         FM(AVS2)
 212 #define GPSR7_0         FM(AVS1)
 213
 214
 215 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 216 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        FM(FSCLKST2_N_A) F_(0, 0)               F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)               FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243
 244 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 245 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274
 275 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 276 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310
 311 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 312 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 333 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340
 341 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 342 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 362 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 363 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 364 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 365 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 366 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 367 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 368 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 369
 370 #define PINMUX_GPSR     \
 371 \
 372                                                                                                 GPSR6_31 \
 373                                                                                                 GPSR6_30 \
 374                                                                                                 GPSR6_29 \
 375                 GPSR1_28                                                                        GPSR6_28 \
 376                 GPSR1_27                                                                        GPSR6_27 \
 377                 GPSR1_26                                                                        GPSR6_26 \
 378                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 379                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 380                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 381                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 382                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 383                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 384                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 385                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 386                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 387                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 388 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 389 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 390 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 391 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 392 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 393 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 394 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 395 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 396 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 397 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 398 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 399 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 400 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 401 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 402 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 403 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 404
 405 #define PINMUX_IPSR                             \
 406 \
 407 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 408 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 409 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 410 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 411 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 412 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 413 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 414 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 415 \
 416 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 417 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 418 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 419 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 420 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 421 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 422 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 423 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 424 \
 425 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 426 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 427 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 428 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 429 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 430 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 431 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 432 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 433 \
 434 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 435 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 436 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 437 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 438 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 439 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 440 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 441 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 442 \
 443 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 444 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 445 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 446 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 447 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 448 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 449 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 450 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 451
 452 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 453 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 454 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 455 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 456 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 457 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 458 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 459 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 460 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 461 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 462 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 463 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 464 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 465 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 466 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 467 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 468 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 469 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 470 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 471
 472 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 473 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 474 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 475 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 476 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 477 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 478 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 479 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 480 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 481 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 482 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 483 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 484 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 485 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 486 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 487 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 488 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 489 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 490 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 491 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 492 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 493 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 494 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 495
 496 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 497 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 498 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 499 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 500 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 501 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 502 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 503 #define MOD_SEL2_22             FM(SEL_NDFC_0)          FM(SEL_NDFC_1)
 504 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 505 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 506 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 507 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 508 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 509 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 510
 511 #define PINMUX_MOD_SELS \
 512 \
 513 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 514                                                 MOD_SEL2_30 \
 515                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 516 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 517 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 518                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 519 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 520 MOD_SEL0_22                                     MOD_SEL2_22 \
 521 MOD_SEL0_21                                     MOD_SEL2_21 \
 522 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 523 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 524 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 525                                                 MOD_SEL2_17 \
 526 MOD_SEL0_16             MOD_SEL1_16 \
 527                         MOD_SEL1_15_14 \
 528 MOD_SEL0_14_13 \
 529                         MOD_SEL1_13 \
 530 MOD_SEL0_12             MOD_SEL1_12 \
 531 MOD_SEL0_11             MOD_SEL1_11 \
 532 MOD_SEL0_10             MOD_SEL1_10 \
 533 MOD_SEL0_9_8            MOD_SEL1_9 \
 534 MOD_SEL0_7_6 \
 535                         MOD_SEL1_6 \
 536 MOD_SEL0_5              MOD_SEL1_5 \
 537 MOD_SEL0_4_3            MOD_SEL1_4 \
 538                         MOD_SEL1_3 \
 539                         MOD_SEL1_2 \
 540                         MOD_SEL1_1 \
 541                         MOD_SEL1_0              MOD_SEL2_0
 542
 543 /*
 544  * These pins are not able to be muxed but have other properties
 545  * that can be set, such as drive-strength or pull-up/pull-down enable.
 546  */
 547 #define PINMUX_STATIC \
 548         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 549         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 550         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 551         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 552         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 553         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 554         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 555         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 556         FM(PRESETOUT) \
 557         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 558         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 559
 560 enum {
 561         PINMUX_RESERVED = 0,
 562
 563         PINMUX_DATA_BEGIN,
 564         GP_ALL(DATA),
 565         PINMUX_DATA_END,
 566
 567 #define F_(x, y)
 568 #define FM(x)   FN_##x,
 569         PINMUX_FUNCTION_BEGIN,
 570         GP_ALL(FN),
 571         PINMUX_GPSR
 572         PINMUX_IPSR
 573         PINMUX_MOD_SELS
 574         PINMUX_FUNCTION_END,
 575 #undef F_
 576 #undef FM
 577
 578 #define F_(x, y)
 579 #define FM(x)   x##_MARK,
 580         PINMUX_MARK_BEGIN,
 581         PINMUX_GPSR
 582         PINMUX_IPSR
 583         PINMUX_MOD_SELS
 584         PINMUX_STATIC
 585         PINMUX_MARK_END,
 586 #undef F_
 587 #undef FM
 588 };
 589
 590 static const u16 pinmux_data[] = {
 591         PINMUX_DATA_GP_ALL(),
 592
 593         PINMUX_SINGLE(AVS1),
 594         PINMUX_SINGLE(AVS2),
 595         PINMUX_SINGLE(CLKOUT),
 596         PINMUX_SINGLE(GP7_03),
 597         PINMUX_SINGLE(HDMI0_CEC),
 598         PINMUX_SINGLE(MSIOF0_RXD),
 599         PINMUX_SINGLE(MSIOF0_SCK),
 600         PINMUX_SINGLE(MSIOF0_TXD),
 601         PINMUX_SINGLE(SSI_SCK5),
 602         PINMUX_SINGLE(SSI_SDATA5),
 603         PINMUX_SINGLE(SSI_WS5),
 604
 605         /* IPSR0 */
 606         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 607         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 608
 609         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 610         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 611         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 612
 613         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 614         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 615         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 616
 617         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 618         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 619         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 620         PINMUX_IPSR_GPSR(IP0_19_16,     FSCLKST2_N_A),
 621
 622         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 623         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 624         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 625
 626         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 627         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 628         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_A,               SEL_SCIF4_0),
 629
 630         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 631         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 632         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 633         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 634         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 635         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 636         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 637
 638         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 639         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 640         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 641         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 642         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 643         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 644         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 645
 646         /* IPSR1 */
 647         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 648         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 649         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 650         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 651         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 652         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 653
 654         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 655         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 656         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 657         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 658         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 659         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 660
 661         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 662         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 663         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 664         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 665         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 666         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 667
 668         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 669         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 670         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 671         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 672         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 673         PINMUX_IPSR_GPSR(IP1_15_12,     FSCLKST2_N_B),
 674         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 675
 676         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 677         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 678         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 679         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 680
 681         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 682         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 683         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 684         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 685
 686         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 687         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 688         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 689
 690         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 691         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 692         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 693         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 694         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 695         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 696
 697         /* IPSR2 */
 698         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 699         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 700         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 701         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 702         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 703         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 704
 705         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 706         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 707         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 708         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 709         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 710         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 711
 712         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 713         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 714         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 715         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 716         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 717         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 718
 719         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 720         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 721         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 722         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 723         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 724         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 725
 726         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 727         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 728         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 729         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 730         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 731         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 732         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 733
 734         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 735         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 736         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 737         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 738         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 739         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 740         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 741
 742         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 743         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 744         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 745         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 746         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 747         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 748         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 749
 750         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 751         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 752         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 753         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 754         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 755         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 756         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 757
 758         /* IPSR3 */
 759         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 760         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 761         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 762         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 763
 764         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 765         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 766         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 767         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 768
 769         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 770         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 771         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 772         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 773         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 774         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 775         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 776         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 777         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 778
 779         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 780         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 781         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 782         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 783         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 784         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 785
 786         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 787         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 788         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 789         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 790         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 791         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 792
 793         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 794         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 795         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 796         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 797         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 798         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 799
 800         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 801         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 802         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 803         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 804         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 805         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 806
 807         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 808         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 809         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 810         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 811
 812         /* IPSR4 */
 813         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 814         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 815         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 816         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 817
 818         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 819         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 820         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 821         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 822
 823         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 824         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 825         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 826         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 827
 828         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 829         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 830
 831         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 832         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 833         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 834
 835         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 836         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 837         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 838         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 839         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 840         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 841         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 842         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 843
 844         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 845         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 846         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 847         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 848         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 849         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 850
 851         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 852         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 853         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 854         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 855         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 856         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 857
 858         /* IPSR5 */
 859         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 860         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 861         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 862         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 863         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 864         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 865         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 866
 867         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 868         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 869         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 870         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 871         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 872         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 873         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 874         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 875
 876         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 877         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 878         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 879         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 880
 881         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 882         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 883         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 884         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 885         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 886
 887         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 888         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 889         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 890         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 891         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 892
 893         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 894         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 895         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 896         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 897
 898         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 899         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 900         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 901         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 902
 903         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 904         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 905         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 906         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 907
 908         /* IPSR6 */
 909         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 910         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 911         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 912         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 913
 914         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 915         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 916         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 917         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 918
 919         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 920         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 921         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 922         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 923
 924         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 925         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 926         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 927         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 928         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 929         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 930
 931         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 932         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 933         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 934         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 935         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 936
 937         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 938         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 939         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 940         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 941         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 942         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 943         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 944
 945         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 946         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 947         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 948         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 949         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 950         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 951         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 952
 953         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 954         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 955         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 956         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 957         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 958         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 959
 960         /* IPSR7 */
 961         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 962         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 963         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 964         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 965         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 966         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 967
 968         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 969         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 970         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 971         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 972         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 973         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 974         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 975
 976         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 977         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 978         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 979         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 980         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 981         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 982         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 983
 984         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 985         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 986         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 987
 988         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 989         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 990         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 991
 992         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 993         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 994         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 995         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 996
 997         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 998         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 999         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1000         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1001
1002         /* IPSR8 */
1003         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1004         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1005         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1006         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1007
1008         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1009         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1010         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1011         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1012
1013         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1014         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1015         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1016
1017         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1018         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1019         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDFC_1),
1020         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1021         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1022
1023         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1024         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1025         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1026         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDFC_1),
1027         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1028         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1029
1030         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1031         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1032         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1033         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDFC_1),
1034         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1035         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1036
1037         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1038         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1039         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1040         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDFC_1),
1041         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1042         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1043
1044         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1045         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1046         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1047         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDFC_1),
1048         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1049         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1050
1051         /* IPSR9 */
1052         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1053         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1054
1055         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1056         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1057
1058         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1059         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1060
1061         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1062         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1063
1064         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1065         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1066
1067         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1068         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1069
1070         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1071         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1072         PINMUX_IPSR_GPSR(IP9_27_24,     SATA_DEVSLP_B),
1073
1074         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1075         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1076
1077         /* IPSR10 */
1078         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1079         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1080
1081         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1082         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1083
1084         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1085         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1086
1087         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1088         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1089
1090         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1091         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1092
1093         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1094         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1095         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1096
1097         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1098         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1099         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1100
1101         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1102         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1103         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1104
1105         /* IPSR11 */
1106         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1107         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1108         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1109
1110         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1111         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1112
1113         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1114         PINMUX_IPSR_MSEL(IP11_11_8,     NFDATA14_A,             SEL_NDFC_0),
1115         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1116         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1117
1118         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1119         PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,             SEL_NDFC_0),
1120         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1121
1122         PINMUX_IPSR_GPSR(IP11_19_16,    SD1_CD),
1123         PINMUX_IPSR_MSEL(IP11_19_16,    NFRB_N_A,               SEL_NDFC_0),
1124         PINMUX_IPSR_MSEL(IP11_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1125
1126         PINMUX_IPSR_GPSR(IP11_23_20,    SD1_WP),
1127         PINMUX_IPSR_MSEL(IP11_23_20,    NFCE_N_A,               SEL_NDFC_0),
1128         PINMUX_IPSR_MSEL(IP11_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1129
1130         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1131         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1132         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1133         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1134         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1135         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1136         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1137         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1138         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1139         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1140
1141         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1142         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1143         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1144         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1145         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1146
1147         /* IPSR12 */
1148         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1149         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1150         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1151         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1152         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1153
1154         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1155         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1156         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1157         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1158         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1159         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1160         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1161         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1162
1163         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1164         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1165         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1166         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1167         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1168         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1169         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1170         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1171
1172         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1173         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1174         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1175         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1176         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1177
1178         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1179         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1180         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1181         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1182         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1183
1184         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1185         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1186         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1187         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1188         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1189         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1190         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1191
1192         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1193         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1194         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1195         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1196         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1197         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1198         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1199
1200         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1201         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1202         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1203         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1204         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1205         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1206         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1207
1208         /* IPSR13 */
1209         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1210         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1211         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1212         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1213         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1214         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1215
1216         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1217         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1218         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1219         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1220         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1221         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1222
1223         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1224         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1225         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1226         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1227         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1228         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1229         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1230         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1231
1232         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1233         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1234         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1235         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1237         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1238
1239         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1240         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1241         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1242         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1243         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1244         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1245
1246         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1247         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1248         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1249         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1250         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1251         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1252         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1253         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1254
1255         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1256         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1257         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1258         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1259         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1260         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1261         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1262
1263         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1264         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1265         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1266         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1267
1268         /* IPSR14 */
1269         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1270         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1271         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDFC_0),
1272         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1273         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1274         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1275         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1276         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1277
1278         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1279         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1280         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1281         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1282         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1283         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1284         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1285         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1286
1287         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1288         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1289         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1290
1291         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1292         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1293         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1294         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1295
1296         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1297         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1298         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1299
1300         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1301         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1302
1303         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1304         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1305
1306         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1307         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1308
1309         /* IPSR15 */
1310         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1311
1312         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1313         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1314
1315         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1316         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1317         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1318
1319         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1320         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1321         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1322         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1323
1324         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1325         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1328         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1329         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1330         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1331
1332         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1333         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1337         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1338         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1339
1340         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1341         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1342         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1345         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1346         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1347
1348         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1349         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1350         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1351         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1353         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1354         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1355
1356         /* IPSR16 */
1357         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1358         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1359
1360         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1361         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1362
1363         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1364         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1365         PINMUX_IPSR_GPSR(IP16_11_8,     SATA_DEVSLP_A),
1366
1367         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1368         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1369         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1370         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1371         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1372         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1373         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1374
1375         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1376         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1377         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1378         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1382
1383         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1384         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1385         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1386         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1387         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1391
1392         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1393         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1394         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1395         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1396         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1399
1400         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1401         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1402         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1403         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1404         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1405         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1406         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1408
1409         /* IPSR17 */
1410         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1411         PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
1412
1413         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1414         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1415         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1416         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1417         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1418
1419         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1420         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1421         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1422         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1423         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1424         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1425         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1426
1427         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1428         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1429         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1430         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1431         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1432         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1433
1434         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1435         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1436         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1437         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1438         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1439         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1440         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1441         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1442         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1443
1444         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1445         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1446         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1447         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1448         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1449         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1450         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1451         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1452         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1453
1454         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1455         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1456         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1457         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1458         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1459         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1460         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1461         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1462         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1463         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1464         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1465
1466         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1467         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1468         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1469         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1470         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1471         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1472         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1473         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1474         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1475
1476         /* IPSR18 */
1477         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1478         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1479         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1480         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1481         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1482         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1483         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1484         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1485         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1486
1487         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1488         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1489         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1490         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1491         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1492         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1493         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1494         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1495         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1496
1497         /* I2C */
1498         PINMUX_IPSR_NOGP(0,             I2C_SEL_0_1),
1499         PINMUX_IPSR_NOGP(0,             I2C_SEL_3_1),
1500         PINMUX_IPSR_NOGP(0,             I2C_SEL_5_1),
1501
1502 /*
1503  * Static pins can not be muxed between different functions but
1504  * still need mark entries in the pinmux list. Add each static
1505  * pin to the list without an associated function. The sh-pfc
1506  * core will do the right thing and skip trying to mux the pin
1507  * while still applying configuration to it.
1508  */
1509 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1510         PINMUX_STATIC
1511 #undef FM
1512 };
1513
1514 /*
1515  * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516  * Physical layout rows: A - AW, cols: 1 - 39.
1517  */
1518 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521 #define PIN_NONE U16_MAX
1522
1523 static const struct sh_pfc_pin pinmux_pins[] = {
1524         PINMUX_GPIO_GP_ALL(),
1525
1526         /*
1527          * Pins not associated with a GPIO port.
1528          *
1529          * The pin positions are different between different r8a77965
1530          * packages, all that is needed for the pfc driver is a unique
1531          * number for each pin. To this end use the pin layout from
1532          * R-Car M3SiP to calculate a unique number for each pin.
1533          */
1534         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1535         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1536         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576 };
1577
1578 /* - AUDIO CLOCK ------------------------------------------------------------ */
1579 static const unsigned int audio_clk_a_a_pins[] = {
1580         /* CLK A */
1581         RCAR_GP_PIN(6, 22),
1582 };
1583 static const unsigned int audio_clk_a_a_mux[] = {
1584         AUDIO_CLKA_A_MARK,
1585 };
1586 static const unsigned int audio_clk_a_b_pins[] = {
1587         /* CLK A */
1588         RCAR_GP_PIN(5, 4),
1589 };
1590 static const unsigned int audio_clk_a_b_mux[] = {
1591         AUDIO_CLKA_B_MARK,
1592 };
1593 static const unsigned int audio_clk_a_c_pins[] = {
1594         /* CLK A */
1595         RCAR_GP_PIN(5, 19),
1596 };
1597 static const unsigned int audio_clk_a_c_mux[] = {
1598         AUDIO_CLKA_C_MARK,
1599 };
1600 static const unsigned int audio_clk_b_a_pins[] = {
1601         /* CLK B */
1602         RCAR_GP_PIN(5, 12),
1603 };
1604 static const unsigned int audio_clk_b_a_mux[] = {
1605         AUDIO_CLKB_A_MARK,
1606 };
1607 static const unsigned int audio_clk_b_b_pins[] = {
1608         /* CLK B */
1609         RCAR_GP_PIN(6, 23),
1610 };
1611 static const unsigned int audio_clk_b_b_mux[] = {
1612         AUDIO_CLKB_B_MARK,
1613 };
1614 static const unsigned int audio_clk_c_a_pins[] = {
1615         /* CLK C */
1616         RCAR_GP_PIN(5, 21),
1617 };
1618 static const unsigned int audio_clk_c_a_mux[] = {
1619         AUDIO_CLKC_A_MARK,
1620 };
1621 static const unsigned int audio_clk_c_b_pins[] = {
1622         /* CLK C */
1623         RCAR_GP_PIN(5, 0),
1624 };
1625 static const unsigned int audio_clk_c_b_mux[] = {
1626         AUDIO_CLKC_B_MARK,
1627 };
1628 static const unsigned int audio_clkout_a_pins[] = {
1629         /* CLKOUT */
1630         RCAR_GP_PIN(5, 18),
1631 };
1632 static const unsigned int audio_clkout_a_mux[] = {
1633         AUDIO_CLKOUT_A_MARK,
1634 };
1635 static const unsigned int audio_clkout_b_pins[] = {
1636         /* CLKOUT */
1637         RCAR_GP_PIN(6, 28),
1638 };
1639 static const unsigned int audio_clkout_b_mux[] = {
1640         AUDIO_CLKOUT_B_MARK,
1641 };
1642 static const unsigned int audio_clkout_c_pins[] = {
1643         /* CLKOUT */
1644         RCAR_GP_PIN(5, 3),
1645 };
1646 static const unsigned int audio_clkout_c_mux[] = {
1647         AUDIO_CLKOUT_C_MARK,
1648 };
1649 static const unsigned int audio_clkout_d_pins[] = {
1650         /* CLKOUT */
1651         RCAR_GP_PIN(5, 21),
1652 };
1653 static const unsigned int audio_clkout_d_mux[] = {
1654         AUDIO_CLKOUT_D_MARK,
1655 };
1656 static const unsigned int audio_clkout1_a_pins[] = {
1657         /* CLKOUT1 */
1658         RCAR_GP_PIN(5, 15),
1659 };
1660 static const unsigned int audio_clkout1_a_mux[] = {
1661         AUDIO_CLKOUT1_A_MARK,
1662 };
1663 static const unsigned int audio_clkout1_b_pins[] = {
1664         /* CLKOUT1 */
1665         RCAR_GP_PIN(6, 29),
1666 };
1667 static const unsigned int audio_clkout1_b_mux[] = {
1668         AUDIO_CLKOUT1_B_MARK,
1669 };
1670 static const unsigned int audio_clkout2_a_pins[] = {
1671         /* CLKOUT2 */
1672         RCAR_GP_PIN(5, 16),
1673 };
1674 static const unsigned int audio_clkout2_a_mux[] = {
1675         AUDIO_CLKOUT2_A_MARK,
1676 };
1677 static const unsigned int audio_clkout2_b_pins[] = {
1678         /* CLKOUT2 */
1679         RCAR_GP_PIN(6, 30),
1680 };
1681 static const unsigned int audio_clkout2_b_mux[] = {
1682         AUDIO_CLKOUT2_B_MARK,
1683 };
1684
1685 static const unsigned int audio_clkout3_a_pins[] = {
1686         /* CLKOUT3 */
1687         RCAR_GP_PIN(5, 19),
1688 };
1689 static const unsigned int audio_clkout3_a_mux[] = {
1690         AUDIO_CLKOUT3_A_MARK,
1691 };
1692 static const unsigned int audio_clkout3_b_pins[] = {
1693         /* CLKOUT3 */
1694         RCAR_GP_PIN(6, 31),
1695 };
1696 static const unsigned int audio_clkout3_b_mux[] = {
1697         AUDIO_CLKOUT3_B_MARK,
1698 };
1699
1700 /* - EtherAVB --------------------------------------------------------------- */
1701 static const unsigned int avb_link_pins[] = {
1702         /* AVB_LINK */
1703         RCAR_GP_PIN(2, 12),
1704 };
1705 static const unsigned int avb_link_mux[] = {
1706         AVB_LINK_MARK,
1707 };
1708 static const unsigned int avb_magic_pins[] = {
1709         /* AVB_MAGIC_ */
1710         RCAR_GP_PIN(2, 10),
1711 };
1712 static const unsigned int avb_magic_mux[] = {
1713         AVB_MAGIC_MARK,
1714 };
1715 static const unsigned int avb_phy_int_pins[] = {
1716         /* AVB_PHY_INT */
1717         RCAR_GP_PIN(2, 11),
1718 };
1719 static const unsigned int avb_phy_int_mux[] = {
1720         AVB_PHY_INT_MARK,
1721 };
1722 static const unsigned int avb_mdio_pins[] = {
1723         /* AVB_MDC, AVB_MDIO */
1724         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1725 };
1726 static const unsigned int avb_mdio_mux[] = {
1727         AVB_MDC_MARK, AVB_MDIO_MARK,
1728 };
1729 static const unsigned int avb_mii_pins[] = {
1730         /*
1731          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1732          * AVB_TD1, AVB_TD2, AVB_TD3,
1733          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1734          * AVB_RD1, AVB_RD2, AVB_RD3,
1735          * AVB_TXCREFCLK
1736          */
1737         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1738         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1739         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1740         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1741         PIN_NUMBER('A', 12),
1742
1743 };
1744 static const unsigned int avb_mii_mux[] = {
1745         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1746         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1747         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1748         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1749         AVB_TXCREFCLK_MARK,
1750 };
1751 static const unsigned int avb_avtp_pps_pins[] = {
1752         /* AVB_AVTP_PPS */
1753         RCAR_GP_PIN(2, 6),
1754 };
1755 static const unsigned int avb_avtp_pps_mux[] = {
1756         AVB_AVTP_PPS_MARK,
1757 };
1758 static const unsigned int avb_avtp_match_a_pins[] = {
1759         /* AVB_AVTP_MATCH_A */
1760         RCAR_GP_PIN(2, 13),
1761 };
1762 static const unsigned int avb_avtp_match_a_mux[] = {
1763         AVB_AVTP_MATCH_A_MARK,
1764 };
1765 static const unsigned int avb_avtp_capture_a_pins[] = {
1766         /* AVB_AVTP_CAPTURE_A */
1767         RCAR_GP_PIN(2, 14),
1768 };
1769 static const unsigned int avb_avtp_capture_a_mux[] = {
1770         AVB_AVTP_CAPTURE_A_MARK,
1771 };
1772 static const unsigned int avb_avtp_match_b_pins[] = {
1773         /*  AVB_AVTP_MATCH_B */
1774         RCAR_GP_PIN(1, 8),
1775 };
1776 static const unsigned int avb_avtp_match_b_mux[] = {
1777         AVB_AVTP_MATCH_B_MARK,
1778 };
1779 static const unsigned int avb_avtp_capture_b_pins[] = {
1780         /* AVB_AVTP_CAPTURE_B */
1781         RCAR_GP_PIN(1, 11),
1782 };
1783 static const unsigned int avb_avtp_capture_b_mux[] = {
1784         AVB_AVTP_CAPTURE_B_MARK,
1785 };
1786
1787 /* - CAN ------------------------------------------------------------------ */
1788 static const unsigned int can0_data_a_pins[] = {
1789         /* TX, RX */
1790         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1791 };
1792
1793 static const unsigned int can0_data_a_mux[] = {
1794         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1795 };
1796
1797 static const unsigned int can0_data_b_pins[] = {
1798         /* TX, RX */
1799         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1800 };
1801
1802 static const unsigned int can0_data_b_mux[] = {
1803         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1804 };
1805
1806 static const unsigned int can1_data_pins[] = {
1807         /* TX, RX */
1808         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1809 };
1810
1811 static const unsigned int can1_data_mux[] = {
1812         CAN1_TX_MARK,           CAN1_RX_MARK,
1813 };
1814
1815 /* - CAN Clock -------------------------------------------------------------- */
1816 static const unsigned int can_clk_pins[] = {
1817         /* CLK */
1818         RCAR_GP_PIN(1, 25),
1819 };
1820
1821 static const unsigned int can_clk_mux[] = {
1822         CAN_CLK_MARK,
1823 };
1824
1825 /* - CAN FD --------------------------------------------------------------- */
1826 static const unsigned int canfd0_data_a_pins[] = {
1827         /* TX, RX */
1828         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1829 };
1830
1831 static const unsigned int canfd0_data_a_mux[] = {
1832         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1833 };
1834
1835 static const unsigned int canfd0_data_b_pins[] = {
1836         /* TX, RX */
1837         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1838 };
1839
1840 static const unsigned int canfd0_data_b_mux[] = {
1841         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1842 };
1843
1844 static const unsigned int canfd1_data_pins[] = {
1845         /* TX, RX */
1846         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1847 };
1848
1849 static const unsigned int canfd1_data_mux[] = {
1850         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1851 };
1852
1853 /* - DU --------------------------------------------------------------------- */
1854 static const unsigned int du_rgb666_pins[] = {
1855         /* R[7:2], G[7:2], B[7:2] */
1856         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1857         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1858         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1859         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1860         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1861         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1862 };
1863
1864 static const unsigned int du_rgb666_mux[] = {
1865         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1866         DU_DR3_MARK, DU_DR2_MARK,
1867         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1868         DU_DG3_MARK, DU_DG2_MARK,
1869         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1870         DU_DB3_MARK, DU_DB2_MARK,
1871 };
1872
1873 static const unsigned int du_rgb888_pins[] = {
1874         /* R[7:0], G[7:0], B[7:0] */
1875         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1876         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1877         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
1878         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1879         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1880         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1881         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1882         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1883         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
1884 };
1885
1886 static const unsigned int du_rgb888_mux[] = {
1887         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1888         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1889         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1890         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1891         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1892         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1893 };
1894
1895 static const unsigned int du_clk_out_0_pins[] = {
1896         /* CLKOUT */
1897         RCAR_GP_PIN(1, 27),
1898 };
1899
1900 static const unsigned int du_clk_out_0_mux[] = {
1901         DU_DOTCLKOUT0_MARK
1902 };
1903
1904 static const unsigned int du_clk_out_1_pins[] = {
1905         /* CLKOUT */
1906         RCAR_GP_PIN(2, 3),
1907 };
1908
1909 static const unsigned int du_clk_out_1_mux[] = {
1910         DU_DOTCLKOUT1_MARK
1911 };
1912
1913 static const unsigned int du_sync_pins[] = {
1914         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1915         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1916 };
1917
1918 static const unsigned int du_sync_mux[] = {
1919         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1920 };
1921
1922 static const unsigned int du_oddf_pins[] = {
1923         /* EXDISP/EXODDF/EXCDE */
1924         RCAR_GP_PIN(2, 2),
1925 };
1926
1927 static const unsigned int du_oddf_mux[] = {
1928         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1929 };
1930
1931 static const unsigned int du_cde_pins[] = {
1932         /* CDE */
1933         RCAR_GP_PIN(2, 0),
1934 };
1935
1936 static const unsigned int du_cde_mux[] = {
1937         DU_CDE_MARK,
1938 };
1939
1940 static const unsigned int du_disp_pins[] = {
1941         /* DISP */
1942         RCAR_GP_PIN(2, 1),
1943 };
1944
1945 static const unsigned int du_disp_mux[] = {
1946         DU_DISP_MARK,
1947 };
1948
1949 /* - HSCIF0 ----------------------------------------------------------------- */
1950 static const unsigned int hscif0_data_pins[] = {
1951         /* RX, TX */
1952         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1953 };
1954
1955 static const unsigned int hscif0_data_mux[] = {
1956         HRX0_MARK, HTX0_MARK,
1957 };
1958
1959 static const unsigned int hscif0_clk_pins[] = {
1960         /* SCK */
1961         RCAR_GP_PIN(5, 12),
1962 };
1963
1964 static const unsigned int hscif0_clk_mux[] = {
1965         HSCK0_MARK,
1966 };
1967
1968 static const unsigned int hscif0_ctrl_pins[] = {
1969         /* RTS, CTS */
1970         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1971 };
1972
1973 static const unsigned int hscif0_ctrl_mux[] = {
1974         HRTS0_N_MARK, HCTS0_N_MARK,
1975 };
1976
1977 /* - HSCIF1 ----------------------------------------------------------------- */
1978 static const unsigned int hscif1_data_a_pins[] = {
1979         /* RX, TX */
1980         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1981 };
1982
1983 static const unsigned int hscif1_data_a_mux[] = {
1984         HRX1_A_MARK, HTX1_A_MARK,
1985 };
1986
1987 static const unsigned int hscif1_clk_a_pins[] = {
1988         /* SCK */
1989         RCAR_GP_PIN(6, 21),
1990 };
1991
1992 static const unsigned int hscif1_clk_a_mux[] = {
1993         HSCK1_A_MARK,
1994 };
1995
1996 static const unsigned int hscif1_ctrl_a_pins[] = {
1997         /* RTS, CTS */
1998         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1999 };
2000
2001 static const unsigned int hscif1_ctrl_a_mux[] = {
2002         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2003 };
2004
2005 static const unsigned int hscif1_data_b_pins[] = {
2006         /* RX, TX */
2007         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2008 };
2009
2010 static const unsigned int hscif1_data_b_mux[] = {
2011         HRX1_B_MARK, HTX1_B_MARK,
2012 };
2013
2014 static const unsigned int hscif1_clk_b_pins[] = {
2015         /* SCK */
2016         RCAR_GP_PIN(5, 0),
2017 };
2018
2019 static const unsigned int hscif1_clk_b_mux[] = {
2020         HSCK1_B_MARK,
2021 };
2022
2023 static const unsigned int hscif1_ctrl_b_pins[] = {
2024         /* RTS, CTS */
2025         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2026 };
2027
2028 static const unsigned int hscif1_ctrl_b_mux[] = {
2029         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2030 };
2031
2032 /* - HSCIF2 ----------------------------------------------------------------- */
2033 static const unsigned int hscif2_data_a_pins[] = {
2034         /* RX, TX */
2035         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2036 };
2037
2038 static const unsigned int hscif2_data_a_mux[] = {
2039         HRX2_A_MARK, HTX2_A_MARK,
2040 };
2041
2042 static const unsigned int hscif2_clk_a_pins[] = {
2043         /* SCK */
2044         RCAR_GP_PIN(6, 10),
2045 };
2046
2047 static const unsigned int hscif2_clk_a_mux[] = {
2048         HSCK2_A_MARK,
2049 };
2050
2051 static const unsigned int hscif2_ctrl_a_pins[] = {
2052         /* RTS, CTS */
2053         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2054 };
2055
2056 static const unsigned int hscif2_ctrl_a_mux[] = {
2057         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2058 };
2059
2060 static const unsigned int hscif2_data_b_pins[] = {
2061         /* RX, TX */
2062         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2063 };
2064
2065 static const unsigned int hscif2_data_b_mux[] = {
2066         HRX2_B_MARK, HTX2_B_MARK,
2067 };
2068
2069 static const unsigned int hscif2_clk_b_pins[] = {
2070         /* SCK */
2071         RCAR_GP_PIN(6, 21),
2072 };
2073
2074 static const unsigned int hscif2_clk_b_mux[] = {
2075         HSCK2_B_MARK,
2076 };
2077
2078 static const unsigned int hscif2_ctrl_b_pins[] = {
2079         /* RTS, CTS */
2080         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2081 };
2082
2083 static const unsigned int hscif2_ctrl_b_mux[] = {
2084         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2085 };
2086
2087 static const unsigned int hscif2_data_c_pins[] = {
2088         /* RX, TX */
2089         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2090 };
2091
2092 static const unsigned int hscif2_data_c_mux[] = {
2093         HRX2_C_MARK, HTX2_C_MARK,
2094 };
2095
2096 static const unsigned int hscif2_clk_c_pins[] = {
2097         /* SCK */
2098         RCAR_GP_PIN(6, 24),
2099 };
2100
2101 static const unsigned int hscif2_clk_c_mux[] = {
2102         HSCK2_C_MARK,
2103 };
2104
2105 static const unsigned int hscif2_ctrl_c_pins[] = {
2106         /* RTS, CTS */
2107         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2108 };
2109
2110 static const unsigned int hscif2_ctrl_c_mux[] = {
2111         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2112 };
2113
2114 /* - HSCIF3 ----------------------------------------------------------------- */
2115 static const unsigned int hscif3_data_a_pins[] = {
2116         /* RX, TX */
2117         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2118 };
2119
2120 static const unsigned int hscif3_data_a_mux[] = {
2121         HRX3_A_MARK, HTX3_A_MARK,
2122 };
2123
2124 static const unsigned int hscif3_clk_pins[] = {
2125         /* SCK */
2126         RCAR_GP_PIN(1, 22),
2127 };
2128
2129 static const unsigned int hscif3_clk_mux[] = {
2130         HSCK3_MARK,
2131 };
2132
2133 static const unsigned int hscif3_ctrl_pins[] = {
2134         /* RTS, CTS */
2135         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2136 };
2137
2138 static const unsigned int hscif3_ctrl_mux[] = {
2139         HRTS3_N_MARK, HCTS3_N_MARK,
2140 };
2141
2142 static const unsigned int hscif3_data_b_pins[] = {
2143         /* RX, TX */
2144         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2145 };
2146
2147 static const unsigned int hscif3_data_b_mux[] = {
2148         HRX3_B_MARK, HTX3_B_MARK,
2149 };
2150
2151 static const unsigned int hscif3_data_c_pins[] = {
2152         /* RX, TX */
2153         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2154 };
2155
2156 static const unsigned int hscif3_data_c_mux[] = {
2157         HRX3_C_MARK, HTX3_C_MARK,
2158 };
2159
2160 static const unsigned int hscif3_data_d_pins[] = {
2161         /* RX, TX */
2162         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2163 };
2164
2165 static const unsigned int hscif3_data_d_mux[] = {
2166         HRX3_D_MARK, HTX3_D_MARK,
2167 };
2168
2169 /* - HSCIF4 ----------------------------------------------------------------- */
2170 static const unsigned int hscif4_data_a_pins[] = {
2171         /* RX, TX */
2172         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2173 };
2174
2175 static const unsigned int hscif4_data_a_mux[] = {
2176         HRX4_A_MARK, HTX4_A_MARK,
2177 };
2178
2179 static const unsigned int hscif4_clk_pins[] = {
2180         /* SCK */
2181         RCAR_GP_PIN(1, 11),
2182 };
2183
2184 static const unsigned int hscif4_clk_mux[] = {
2185         HSCK4_MARK,
2186 };
2187
2188 static const unsigned int hscif4_ctrl_pins[] = {
2189         /* RTS, CTS */
2190         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2191 };
2192
2193 static const unsigned int hscif4_ctrl_mux[] = {
2194         HRTS4_N_MARK, HCTS4_N_MARK,
2195 };
2196
2197 static const unsigned int hscif4_data_b_pins[] = {
2198         /* RX, TX */
2199         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2200 };
2201
2202 static const unsigned int hscif4_data_b_mux[] = {
2203         HRX4_B_MARK, HTX4_B_MARK,
2204 };
2205
2206 /* - I2C -------------------------------------------------------------------- */
2207 static const unsigned int i2c1_a_pins[] = {
2208         /* SDA, SCL */
2209         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2210 };
2211 static const unsigned int i2c1_a_mux[] = {
2212         SDA1_A_MARK, SCL1_A_MARK,
2213 };
2214 static const unsigned int i2c1_b_pins[] = {
2215         /* SDA, SCL */
2216         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2217 };
2218 static const unsigned int i2c1_b_mux[] = {
2219         SDA1_B_MARK, SCL1_B_MARK,
2220 };
2221 static const unsigned int i2c2_a_pins[] = {
2222         /* SDA, SCL */
2223         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2224 };
2225 static const unsigned int i2c2_a_mux[] = {
2226         SDA2_A_MARK, SCL2_A_MARK,
2227 };
2228 static const unsigned int i2c2_b_pins[] = {
2229         /* SDA, SCL */
2230         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2231 };
2232 static const unsigned int i2c2_b_mux[] = {
2233         SDA2_B_MARK, SCL2_B_MARK,
2234 };
2235 static const unsigned int i2c6_a_pins[] = {
2236         /* SDA, SCL */
2237         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2238 };
2239 static const unsigned int i2c6_a_mux[] = {
2240         SDA6_A_MARK, SCL6_A_MARK,
2241 };
2242 static const unsigned int i2c6_b_pins[] = {
2243         /* SDA, SCL */
2244         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2245 };
2246 static const unsigned int i2c6_b_mux[] = {
2247         SDA6_B_MARK, SCL6_B_MARK,
2248 };
2249 static const unsigned int i2c6_c_pins[] = {
2250         /* SDA, SCL */
2251         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2252 };
2253 static const unsigned int i2c6_c_mux[] = {
2254         SDA6_C_MARK, SCL6_C_MARK,
2255 };
2256
2257 /* - INTC-EX ---------------------------------------------------------------- */
2258 static const unsigned int intc_ex_irq0_pins[] = {
2259         /* IRQ0 */
2260         RCAR_GP_PIN(2, 0),
2261 };
2262 static const unsigned int intc_ex_irq0_mux[] = {
2263         IRQ0_MARK,
2264 };
2265 static const unsigned int intc_ex_irq1_pins[] = {
2266         /* IRQ1 */
2267         RCAR_GP_PIN(2, 1),
2268 };
2269 static const unsigned int intc_ex_irq1_mux[] = {
2270         IRQ1_MARK,
2271 };
2272 static const unsigned int intc_ex_irq2_pins[] = {
2273         /* IRQ2 */
2274         RCAR_GP_PIN(2, 2),
2275 };
2276 static const unsigned int intc_ex_irq2_mux[] = {
2277         IRQ2_MARK,
2278 };
2279 static const unsigned int intc_ex_irq3_pins[] = {
2280         /* IRQ3 */
2281         RCAR_GP_PIN(2, 3),
2282 };
2283 static const unsigned int intc_ex_irq3_mux[] = {
2284         IRQ3_MARK,
2285 };
2286 static const unsigned int intc_ex_irq4_pins[] = {
2287         /* IRQ4 */
2288         RCAR_GP_PIN(2, 4),
2289 };
2290 static const unsigned int intc_ex_irq4_mux[] = {
2291         IRQ4_MARK,
2292 };
2293 static const unsigned int intc_ex_irq5_pins[] = {
2294         /* IRQ5 */
2295         RCAR_GP_PIN(2, 5),
2296 };
2297 static const unsigned int intc_ex_irq5_mux[] = {
2298         IRQ5_MARK,
2299 };
2300
2301 /* - MSIOF0 ----------------------------------------------------------------- */
2302 static const unsigned int msiof0_clk_pins[] = {
2303         /* SCK */
2304         RCAR_GP_PIN(5, 17),
2305 };
2306 static const unsigned int msiof0_clk_mux[] = {
2307         MSIOF0_SCK_MARK,
2308 };
2309 static const unsigned int msiof0_sync_pins[] = {
2310         /* SYNC */
2311         RCAR_GP_PIN(5, 18),
2312 };
2313 static const unsigned int msiof0_sync_mux[] = {
2314         MSIOF0_SYNC_MARK,
2315 };
2316 static const unsigned int msiof0_ss1_pins[] = {
2317         /* SS1 */
2318         RCAR_GP_PIN(5, 19),
2319 };
2320 static const unsigned int msiof0_ss1_mux[] = {
2321         MSIOF0_SS1_MARK,
2322 };
2323 static const unsigned int msiof0_ss2_pins[] = {
2324         /* SS2 */
2325         RCAR_GP_PIN(5, 21),
2326 };
2327 static const unsigned int msiof0_ss2_mux[] = {
2328         MSIOF0_SS2_MARK,
2329 };
2330 static const unsigned int msiof0_txd_pins[] = {
2331         /* TXD */
2332         RCAR_GP_PIN(5, 20),
2333 };
2334 static const unsigned int msiof0_txd_mux[] = {
2335         MSIOF0_TXD_MARK,
2336 };
2337 static const unsigned int msiof0_rxd_pins[] = {
2338         /* RXD */
2339         RCAR_GP_PIN(5, 22),
2340 };
2341 static const unsigned int msiof0_rxd_mux[] = {
2342         MSIOF0_RXD_MARK,
2343 };
2344 /* - MSIOF1 ----------------------------------------------------------------- */
2345 static const unsigned int msiof1_clk_a_pins[] = {
2346         /* SCK */
2347         RCAR_GP_PIN(6, 8),
2348 };
2349 static const unsigned int msiof1_clk_a_mux[] = {
2350         MSIOF1_SCK_A_MARK,
2351 };
2352 static const unsigned int msiof1_sync_a_pins[] = {
2353         /* SYNC */
2354         RCAR_GP_PIN(6, 9),
2355 };
2356 static const unsigned int msiof1_sync_a_mux[] = {
2357         MSIOF1_SYNC_A_MARK,
2358 };
2359 static const unsigned int msiof1_ss1_a_pins[] = {
2360         /* SS1 */
2361         RCAR_GP_PIN(6, 5),
2362 };
2363 static const unsigned int msiof1_ss1_a_mux[] = {
2364         MSIOF1_SS1_A_MARK,
2365 };
2366 static const unsigned int msiof1_ss2_a_pins[] = {
2367         /* SS2 */
2368         RCAR_GP_PIN(6, 6),
2369 };
2370 static const unsigned int msiof1_ss2_a_mux[] = {
2371         MSIOF1_SS2_A_MARK,
2372 };
2373 static const unsigned int msiof1_txd_a_pins[] = {
2374         /* TXD */
2375         RCAR_GP_PIN(6, 7),
2376 };
2377 static const unsigned int msiof1_txd_a_mux[] = {
2378         MSIOF1_TXD_A_MARK,
2379 };
2380 static const unsigned int msiof1_rxd_a_pins[] = {
2381         /* RXD */
2382         RCAR_GP_PIN(6, 10),
2383 };
2384 static const unsigned int msiof1_rxd_a_mux[] = {
2385         MSIOF1_RXD_A_MARK,
2386 };
2387 static const unsigned int msiof1_clk_b_pins[] = {
2388         /* SCK */
2389         RCAR_GP_PIN(5, 9),
2390 };
2391 static const unsigned int msiof1_clk_b_mux[] = {
2392         MSIOF1_SCK_B_MARK,
2393 };
2394 static const unsigned int msiof1_sync_b_pins[] = {
2395         /* SYNC */
2396         RCAR_GP_PIN(5, 3),
2397 };
2398 static const unsigned int msiof1_sync_b_mux[] = {
2399         MSIOF1_SYNC_B_MARK,
2400 };
2401 static const unsigned int msiof1_ss1_b_pins[] = {
2402         /* SS1 */
2403         RCAR_GP_PIN(5, 4),
2404 };
2405 static const unsigned int msiof1_ss1_b_mux[] = {
2406         MSIOF1_SS1_B_MARK,
2407 };
2408 static const unsigned int msiof1_ss2_b_pins[] = {
2409         /* SS2 */
2410         RCAR_GP_PIN(5, 0),
2411 };
2412 static const unsigned int msiof1_ss2_b_mux[] = {
2413         MSIOF1_SS2_B_MARK,
2414 };
2415 static const unsigned int msiof1_txd_b_pins[] = {
2416         /* TXD */
2417         RCAR_GP_PIN(5, 8),
2418 };
2419 static const unsigned int msiof1_txd_b_mux[] = {
2420         MSIOF1_TXD_B_MARK,
2421 };
2422 static const unsigned int msiof1_rxd_b_pins[] = {
2423         /* RXD */
2424         RCAR_GP_PIN(5, 7),
2425 };
2426 static const unsigned int msiof1_rxd_b_mux[] = {
2427         MSIOF1_RXD_B_MARK,
2428 };
2429 static const unsigned int msiof1_clk_c_pins[] = {
2430         /* SCK */
2431         RCAR_GP_PIN(6, 17),
2432 };
2433 static const unsigned int msiof1_clk_c_mux[] = {
2434         MSIOF1_SCK_C_MARK,
2435 };
2436 static const unsigned int msiof1_sync_c_pins[] = {
2437         /* SYNC */
2438         RCAR_GP_PIN(6, 18),
2439 };
2440 static const unsigned int msiof1_sync_c_mux[] = {
2441         MSIOF1_SYNC_C_MARK,
2442 };
2443 static const unsigned int msiof1_ss1_c_pins[] = {
2444         /* SS1 */
2445         RCAR_GP_PIN(6, 21),
2446 };
2447 static const unsigned int msiof1_ss1_c_mux[] = {
2448         MSIOF1_SS1_C_MARK,
2449 };
2450 static const unsigned int msiof1_ss2_c_pins[] = {
2451         /* SS2 */
2452         RCAR_GP_PIN(6, 27),
2453 };
2454 static const unsigned int msiof1_ss2_c_mux[] = {
2455         MSIOF1_SS2_C_MARK,
2456 };
2457 static const unsigned int msiof1_txd_c_pins[] = {
2458         /* TXD */
2459         RCAR_GP_PIN(6, 20),
2460 };
2461 static const unsigned int msiof1_txd_c_mux[] = {
2462         MSIOF1_TXD_C_MARK,
2463 };
2464 static const unsigned int msiof1_rxd_c_pins[] = {
2465         /* RXD */
2466         RCAR_GP_PIN(6, 19),
2467 };
2468 static const unsigned int msiof1_rxd_c_mux[] = {
2469         MSIOF1_RXD_C_MARK,
2470 };
2471 static const unsigned int msiof1_clk_d_pins[] = {
2472         /* SCK */
2473         RCAR_GP_PIN(5, 12),
2474 };
2475 static const unsigned int msiof1_clk_d_mux[] = {
2476         MSIOF1_SCK_D_MARK,
2477 };
2478 static const unsigned int msiof1_sync_d_pins[] = {
2479         /* SYNC */
2480         RCAR_GP_PIN(5, 15),
2481 };
2482 static const unsigned int msiof1_sync_d_mux[] = {
2483         MSIOF1_SYNC_D_MARK,
2484 };
2485 static const unsigned int msiof1_ss1_d_pins[] = {
2486         /* SS1 */
2487         RCAR_GP_PIN(5, 16),
2488 };
2489 static const unsigned int msiof1_ss1_d_mux[] = {
2490         MSIOF1_SS1_D_MARK,
2491 };
2492 static const unsigned int msiof1_ss2_d_pins[] = {
2493         /* SS2 */
2494         RCAR_GP_PIN(5, 21),
2495 };
2496 static const unsigned int msiof1_ss2_d_mux[] = {
2497         MSIOF1_SS2_D_MARK,
2498 };
2499 static const unsigned int msiof1_txd_d_pins[] = {
2500         /* TXD */
2501         RCAR_GP_PIN(5, 14),
2502 };
2503 static const unsigned int msiof1_txd_d_mux[] = {
2504         MSIOF1_TXD_D_MARK,
2505 };
2506 static const unsigned int msiof1_rxd_d_pins[] = {
2507         /* RXD */
2508         RCAR_GP_PIN(5, 13),
2509 };
2510 static const unsigned int msiof1_rxd_d_mux[] = {
2511         MSIOF1_RXD_D_MARK,
2512 };
2513 static const unsigned int msiof1_clk_e_pins[] = {
2514         /* SCK */
2515         RCAR_GP_PIN(3, 0),
2516 };
2517 static const unsigned int msiof1_clk_e_mux[] = {
2518         MSIOF1_SCK_E_MARK,
2519 };
2520 static const unsigned int msiof1_sync_e_pins[] = {
2521         /* SYNC */
2522         RCAR_GP_PIN(3, 1),
2523 };
2524 static const unsigned int msiof1_sync_e_mux[] = {
2525         MSIOF1_SYNC_E_MARK,
2526 };
2527 static const unsigned int msiof1_ss1_e_pins[] = {
2528         /* SS1 */
2529         RCAR_GP_PIN(3, 4),
2530 };
2531 static const unsigned int msiof1_ss1_e_mux[] = {
2532         MSIOF1_SS1_E_MARK,
2533 };
2534 static const unsigned int msiof1_ss2_e_pins[] = {
2535         /* SS2 */
2536         RCAR_GP_PIN(3, 5),
2537 };
2538 static const unsigned int msiof1_ss2_e_mux[] = {
2539         MSIOF1_SS2_E_MARK,
2540 };
2541 static const unsigned int msiof1_txd_e_pins[] = {
2542         /* TXD */
2543         RCAR_GP_PIN(3, 3),
2544 };
2545 static const unsigned int msiof1_txd_e_mux[] = {
2546         MSIOF1_TXD_E_MARK,
2547 };
2548 static const unsigned int msiof1_rxd_e_pins[] = {
2549         /* RXD */
2550         RCAR_GP_PIN(3, 2),
2551 };
2552 static const unsigned int msiof1_rxd_e_mux[] = {
2553         MSIOF1_RXD_E_MARK,
2554 };
2555 static const unsigned int msiof1_clk_f_pins[] = {
2556         /* SCK */
2557         RCAR_GP_PIN(5, 23),
2558 };
2559 static const unsigned int msiof1_clk_f_mux[] = {
2560         MSIOF1_SCK_F_MARK,
2561 };
2562 static const unsigned int msiof1_sync_f_pins[] = {
2563         /* SYNC */
2564         RCAR_GP_PIN(5, 24),
2565 };
2566 static const unsigned int msiof1_sync_f_mux[] = {
2567         MSIOF1_SYNC_F_MARK,
2568 };
2569 static const unsigned int msiof1_ss1_f_pins[] = {
2570         /* SS1 */
2571         RCAR_GP_PIN(6, 1),
2572 };
2573 static const unsigned int msiof1_ss1_f_mux[] = {
2574         MSIOF1_SS1_F_MARK,
2575 };
2576 static const unsigned int msiof1_ss2_f_pins[] = {
2577         /* SS2 */
2578         RCAR_GP_PIN(6, 2),
2579 };
2580 static const unsigned int msiof1_ss2_f_mux[] = {
2581         MSIOF1_SS2_F_MARK,
2582 };
2583 static const unsigned int msiof1_txd_f_pins[] = {
2584         /* TXD */
2585         RCAR_GP_PIN(6, 0),
2586 };
2587 static const unsigned int msiof1_txd_f_mux[] = {
2588         MSIOF1_TXD_F_MARK,
2589 };
2590 static const unsigned int msiof1_rxd_f_pins[] = {
2591         /* RXD */
2592         RCAR_GP_PIN(5, 25),
2593 };
2594 static const unsigned int msiof1_rxd_f_mux[] = {
2595         MSIOF1_RXD_F_MARK,
2596 };
2597 static const unsigned int msiof1_clk_g_pins[] = {
2598         /* SCK */
2599         RCAR_GP_PIN(3, 6),
2600 };
2601 static const unsigned int msiof1_clk_g_mux[] = {
2602         MSIOF1_SCK_G_MARK,
2603 };
2604 static const unsigned int msiof1_sync_g_pins[] = {
2605         /* SYNC */
2606         RCAR_GP_PIN(3, 7),
2607 };
2608 static const unsigned int msiof1_sync_g_mux[] = {
2609         MSIOF1_SYNC_G_MARK,
2610 };
2611 static const unsigned int msiof1_ss1_g_pins[] = {
2612         /* SS1 */
2613         RCAR_GP_PIN(3, 10),
2614 };
2615 static const unsigned int msiof1_ss1_g_mux[] = {
2616         MSIOF1_SS1_G_MARK,
2617 };
2618 static const unsigned int msiof1_ss2_g_pins[] = {
2619         /* SS2 */
2620         RCAR_GP_PIN(3, 11),
2621 };
2622 static const unsigned int msiof1_ss2_g_mux[] = {
2623         MSIOF1_SS2_G_MARK,
2624 };
2625 static const unsigned int msiof1_txd_g_pins[] = {
2626         /* TXD */
2627         RCAR_GP_PIN(3, 9),
2628 };
2629 static const unsigned int msiof1_txd_g_mux[] = {
2630         MSIOF1_TXD_G_MARK,
2631 };
2632 static const unsigned int msiof1_rxd_g_pins[] = {
2633         /* RXD */
2634         RCAR_GP_PIN(3, 8),
2635 };
2636 static const unsigned int msiof1_rxd_g_mux[] = {
2637         MSIOF1_RXD_G_MARK,
2638 };
2639 /* - MSIOF2 ----------------------------------------------------------------- */
2640 static const unsigned int msiof2_clk_a_pins[] = {
2641         /* SCK */
2642         RCAR_GP_PIN(1, 9),
2643 };
2644 static const unsigned int msiof2_clk_a_mux[] = {
2645         MSIOF2_SCK_A_MARK,
2646 };
2647 static const unsigned int msiof2_sync_a_pins[] = {
2648         /* SYNC */
2649         RCAR_GP_PIN(1, 8),
2650 };
2651 static const unsigned int msiof2_sync_a_mux[] = {
2652         MSIOF2_SYNC_A_MARK,
2653 };
2654 static const unsigned int msiof2_ss1_a_pins[] = {
2655         /* SS1 */
2656         RCAR_GP_PIN(1, 6),
2657 };
2658 static const unsigned int msiof2_ss1_a_mux[] = {
2659         MSIOF2_SS1_A_MARK,
2660 };
2661 static const unsigned int msiof2_ss2_a_pins[] = {
2662         /* SS2 */
2663         RCAR_GP_PIN(1, 7),
2664 };
2665 static const unsigned int msiof2_ss2_a_mux[] = {
2666         MSIOF2_SS2_A_MARK,
2667 };
2668 static const unsigned int msiof2_txd_a_pins[] = {
2669         /* TXD */
2670         RCAR_GP_PIN(1, 11),
2671 };
2672 static const unsigned int msiof2_txd_a_mux[] = {
2673         MSIOF2_TXD_A_MARK,
2674 };
2675 static const unsigned int msiof2_rxd_a_pins[] = {
2676         /* RXD */
2677         RCAR_GP_PIN(1, 10),
2678 };
2679 static const unsigned int msiof2_rxd_a_mux[] = {
2680         MSIOF2_RXD_A_MARK,
2681 };
2682 static const unsigned int msiof2_clk_b_pins[] = {
2683         /* SCK */
2684         RCAR_GP_PIN(0, 4),
2685 };
2686 static const unsigned int msiof2_clk_b_mux[] = {
2687         MSIOF2_SCK_B_MARK,
2688 };
2689 static const unsigned int msiof2_sync_b_pins[] = {
2690         /* SYNC */
2691         RCAR_GP_PIN(0, 5),
2692 };
2693 static const unsigned int msiof2_sync_b_mux[] = {
2694         MSIOF2_SYNC_B_MARK,
2695 };
2696 static const unsigned int msiof2_ss1_b_pins[] = {
2697         /* SS1 */
2698         RCAR_GP_PIN(0, 0),
2699 };
2700 static const unsigned int msiof2_ss1_b_mux[] = {
2701         MSIOF2_SS1_B_MARK,
2702 };
2703 static const unsigned int msiof2_ss2_b_pins[] = {
2704         /* SS2 */
2705         RCAR_GP_PIN(0, 1),
2706 };
2707 static const unsigned int msiof2_ss2_b_mux[] = {
2708         MSIOF2_SS2_B_MARK,
2709 };
2710 static const unsigned int msiof2_txd_b_pins[] = {
2711         /* TXD */
2712         RCAR_GP_PIN(0, 7),
2713 };
2714 static const unsigned int msiof2_txd_b_mux[] = {
2715         MSIOF2_TXD_B_MARK,
2716 };
2717 static const unsigned int msiof2_rxd_b_pins[] = {
2718         /* RXD */
2719         RCAR_GP_PIN(0, 6),
2720 };
2721 static const unsigned int msiof2_rxd_b_mux[] = {
2722         MSIOF2_RXD_B_MARK,
2723 };
2724 static const unsigned int msiof2_clk_c_pins[] = {
2725         /* SCK */
2726         RCAR_GP_PIN(2, 12),
2727 };
2728 static const unsigned int msiof2_clk_c_mux[] = {
2729         MSIOF2_SCK_C_MARK,
2730 };
2731 static const unsigned int msiof2_sync_c_pins[] = {
2732         /* SYNC */
2733         RCAR_GP_PIN(2, 11),
2734 };
2735 static const unsigned int msiof2_sync_c_mux[] = {
2736         MSIOF2_SYNC_C_MARK,
2737 };
2738 static const unsigned int msiof2_ss1_c_pins[] = {
2739         /* SS1 */
2740         RCAR_GP_PIN(2, 10),
2741 };
2742 static const unsigned int msiof2_ss1_c_mux[] = {
2743         MSIOF2_SS1_C_MARK,
2744 };
2745 static const unsigned int msiof2_ss2_c_pins[] = {
2746         /* SS2 */
2747         RCAR_GP_PIN(2, 9),
2748 };
2749 static const unsigned int msiof2_ss2_c_mux[] = {
2750         MSIOF2_SS2_C_MARK,
2751 };
2752 static const unsigned int msiof2_txd_c_pins[] = {
2753         /* TXD */
2754         RCAR_GP_PIN(2, 14),
2755 };
2756 static const unsigned int msiof2_txd_c_mux[] = {
2757         MSIOF2_TXD_C_MARK,
2758 };
2759 static const unsigned int msiof2_rxd_c_pins[] = {
2760         /* RXD */
2761         RCAR_GP_PIN(2, 13),
2762 };
2763 static const unsigned int msiof2_rxd_c_mux[] = {
2764         MSIOF2_RXD_C_MARK,
2765 };
2766 static const unsigned int msiof2_clk_d_pins[] = {
2767         /* SCK */
2768         RCAR_GP_PIN(0, 8),
2769 };
2770 static const unsigned int msiof2_clk_d_mux[] = {
2771         MSIOF2_SCK_D_MARK,
2772 };
2773 static const unsigned int msiof2_sync_d_pins[] = {
2774         /* SYNC */
2775         RCAR_GP_PIN(0, 9),
2776 };
2777 static const unsigned int msiof2_sync_d_mux[] = {
2778         MSIOF2_SYNC_D_MARK,
2779 };
2780 static const unsigned int msiof2_ss1_d_pins[] = {
2781         /* SS1 */
2782         RCAR_GP_PIN(0, 12),
2783 };
2784 static const unsigned int msiof2_ss1_d_mux[] = {
2785         MSIOF2_SS1_D_MARK,
2786 };
2787 static const unsigned int msiof2_ss2_d_pins[] = {
2788         /* SS2 */
2789         RCAR_GP_PIN(0, 13),
2790 };
2791 static const unsigned int msiof2_ss2_d_mux[] = {
2792         MSIOF2_SS2_D_MARK,
2793 };
2794 static const unsigned int msiof2_txd_d_pins[] = {
2795         /* TXD */
2796         RCAR_GP_PIN(0, 11),
2797 };
2798 static const unsigned int msiof2_txd_d_mux[] = {
2799         MSIOF2_TXD_D_MARK,
2800 };
2801 static const unsigned int msiof2_rxd_d_pins[] = {
2802         /* RXD */
2803         RCAR_GP_PIN(0, 10),
2804 };
2805 static const unsigned int msiof2_rxd_d_mux[] = {
2806         MSIOF2_RXD_D_MARK,
2807 };
2808 /* - MSIOF3 ----------------------------------------------------------------- */
2809 static const unsigned int msiof3_clk_a_pins[] = {
2810         /* SCK */
2811         RCAR_GP_PIN(0, 0),
2812 };
2813 static const unsigned int msiof3_clk_a_mux[] = {
2814         MSIOF3_SCK_A_MARK,
2815 };
2816 static const unsigned int msiof3_sync_a_pins[] = {
2817         /* SYNC */
2818         RCAR_GP_PIN(0, 1),
2819 };
2820 static const unsigned int msiof3_sync_a_mux[] = {
2821         MSIOF3_SYNC_A_MARK,
2822 };
2823 static const unsigned int msiof3_ss1_a_pins[] = {
2824         /* SS1 */
2825         RCAR_GP_PIN(0, 14),
2826 };
2827 static const unsigned int msiof3_ss1_a_mux[] = {
2828         MSIOF3_SS1_A_MARK,
2829 };
2830 static const unsigned int msiof3_ss2_a_pins[] = {
2831         /* SS2 */
2832         RCAR_GP_PIN(0, 15),
2833 };
2834 static const unsigned int msiof3_ss2_a_mux[] = {
2835         MSIOF3_SS2_A_MARK,
2836 };
2837 static const unsigned int msiof3_txd_a_pins[] = {
2838         /* TXD */
2839         RCAR_GP_PIN(0, 3),
2840 };
2841 static const unsigned int msiof3_txd_a_mux[] = {
2842         MSIOF3_TXD_A_MARK,
2843 };
2844 static const unsigned int msiof3_rxd_a_pins[] = {
2845         /* RXD */
2846         RCAR_GP_PIN(0, 2),
2847 };
2848 static const unsigned int msiof3_rxd_a_mux[] = {
2849         MSIOF3_RXD_A_MARK,
2850 };
2851 static const unsigned int msiof3_clk_b_pins[] = {
2852         /* SCK */
2853         RCAR_GP_PIN(1, 2),
2854 };
2855 static const unsigned int msiof3_clk_b_mux[] = {
2856         MSIOF3_SCK_B_MARK,
2857 };
2858 static const unsigned int msiof3_sync_b_pins[] = {
2859         /* SYNC */
2860         RCAR_GP_PIN(1, 0),
2861 };
2862 static const unsigned int msiof3_sync_b_mux[] = {
2863         MSIOF3_SYNC_B_MARK,
2864 };
2865 static const unsigned int msiof3_ss1_b_pins[] = {
2866         /* SS1 */
2867         RCAR_GP_PIN(1, 4),
2868 };
2869 static const unsigned int msiof3_ss1_b_mux[] = {
2870         MSIOF3_SS1_B_MARK,
2871 };
2872 static const unsigned int msiof3_ss2_b_pins[] = {
2873         /* SS2 */
2874         RCAR_GP_PIN(1, 5),
2875 };
2876 static const unsigned int msiof3_ss2_b_mux[] = {
2877         MSIOF3_SS2_B_MARK,
2878 };
2879 static const unsigned int msiof3_txd_b_pins[] = {
2880         /* TXD */
2881         RCAR_GP_PIN(1, 1),
2882 };
2883 static const unsigned int msiof3_txd_b_mux[] = {
2884         MSIOF3_TXD_B_MARK,
2885 };
2886 static const unsigned int msiof3_rxd_b_pins[] = {
2887         /* RXD */
2888         RCAR_GP_PIN(1, 3),
2889 };
2890 static const unsigned int msiof3_rxd_b_mux[] = {
2891         MSIOF3_RXD_B_MARK,
2892 };
2893 static const unsigned int msiof3_clk_c_pins[] = {
2894         /* SCK */
2895         RCAR_GP_PIN(1, 12),
2896 };
2897 static const unsigned int msiof3_clk_c_mux[] = {
2898         MSIOF3_SCK_C_MARK,
2899 };
2900 static const unsigned int msiof3_sync_c_pins[] = {
2901         /* SYNC */
2902         RCAR_GP_PIN(1, 13),
2903 };
2904 static const unsigned int msiof3_sync_c_mux[] = {
2905         MSIOF3_SYNC_C_MARK,
2906 };
2907 static const unsigned int msiof3_txd_c_pins[] = {
2908         /* TXD */
2909         RCAR_GP_PIN(1, 15),
2910 };
2911 static const unsigned int msiof3_txd_c_mux[] = {
2912         MSIOF3_TXD_C_MARK,
2913 };
2914 static const unsigned int msiof3_rxd_c_pins[] = {
2915         /* RXD */
2916         RCAR_GP_PIN(1, 14),
2917 };
2918 static const unsigned int msiof3_rxd_c_mux[] = {
2919         MSIOF3_RXD_C_MARK,
2920 };
2921 static const unsigned int msiof3_clk_d_pins[] = {
2922         /* SCK */
2923         RCAR_GP_PIN(1, 22),
2924 };
2925 static const unsigned int msiof3_clk_d_mux[] = {
2926         MSIOF3_SCK_D_MARK,
2927 };
2928 static const unsigned int msiof3_sync_d_pins[] = {
2929         /* SYNC */
2930         RCAR_GP_PIN(1, 23),
2931 };
2932 static const unsigned int msiof3_sync_d_mux[] = {
2933         MSIOF3_SYNC_D_MARK,
2934 };
2935 static const unsigned int msiof3_ss1_d_pins[] = {
2936         /* SS1 */
2937         RCAR_GP_PIN(1, 26),
2938 };
2939 static const unsigned int msiof3_ss1_d_mux[] = {
2940         MSIOF3_SS1_D_MARK,
2941 };
2942 static const unsigned int msiof3_txd_d_pins[] = {
2943         /* TXD */
2944         RCAR_GP_PIN(1, 25),
2945 };
2946 static const unsigned int msiof3_txd_d_mux[] = {
2947         MSIOF3_TXD_D_MARK,
2948 };
2949 static const unsigned int msiof3_rxd_d_pins[] = {
2950         /* RXD */
2951         RCAR_GP_PIN(1, 24),
2952 };
2953 static const unsigned int msiof3_rxd_d_mux[] = {
2954         MSIOF3_RXD_D_MARK,
2955 };
2956 static const unsigned int msiof3_clk_e_pins[] = {
2957         /* SCK */
2958         RCAR_GP_PIN(2, 3),
2959 };
2960 static const unsigned int msiof3_clk_e_mux[] = {
2961         MSIOF3_SCK_E_MARK,
2962 };
2963 static const unsigned int msiof3_sync_e_pins[] = {
2964         /* SYNC */
2965         RCAR_GP_PIN(2, 2),
2966 };
2967 static const unsigned int msiof3_sync_e_mux[] = {
2968         MSIOF3_SYNC_E_MARK,
2969 };
2970 static const unsigned int msiof3_ss1_e_pins[] = {
2971         /* SS1 */
2972         RCAR_GP_PIN(2, 1),
2973 };
2974 static const unsigned int msiof3_ss1_e_mux[] = {
2975         MSIOF3_SS1_E_MARK,
2976 };
2977 static const unsigned int msiof3_ss2_e_pins[] = {
2978         /* SS2 */
2979         RCAR_GP_PIN(2, 0),
2980 };
2981 static const unsigned int msiof3_ss2_e_mux[] = {
2982         MSIOF3_SS2_E_MARK,
2983 };
2984 static const unsigned int msiof3_txd_e_pins[] = {
2985         /* TXD */
2986         RCAR_GP_PIN(2, 5),
2987 };
2988 static const unsigned int msiof3_txd_e_mux[] = {
2989         MSIOF3_TXD_E_MARK,
2990 };
2991 static const unsigned int msiof3_rxd_e_pins[] = {
2992         /* RXD */
2993         RCAR_GP_PIN(2, 4),
2994 };
2995 static const unsigned int msiof3_rxd_e_mux[] = {
2996         MSIOF3_RXD_E_MARK,
2997 };
2998
2999 /* - PWM0 --------------------------------------------------------------------*/
3000 static const unsigned int pwm0_pins[] = {
3001         /* PWM */
3002         RCAR_GP_PIN(2, 6),
3003 };
3004 static const unsigned int pwm0_mux[] = {
3005         PWM0_MARK,
3006 };
3007 /* - PWM1 --------------------------------------------------------------------*/
3008 static const unsigned int pwm1_a_pins[] = {
3009         /* PWM */
3010         RCAR_GP_PIN(2, 7),
3011 };
3012 static const unsigned int pwm1_a_mux[] = {
3013         PWM1_A_MARK,
3014 };
3015 static const unsigned int pwm1_b_pins[] = {
3016         /* PWM */
3017         RCAR_GP_PIN(1, 8),
3018 };
3019 static const unsigned int pwm1_b_mux[] = {
3020         PWM1_B_MARK,
3021 };
3022 /* - PWM2 --------------------------------------------------------------------*/
3023 static const unsigned int pwm2_a_pins[] = {
3024         /* PWM */
3025         RCAR_GP_PIN(2, 8),
3026 };
3027 static const unsigned int pwm2_a_mux[] = {
3028         PWM2_A_MARK,
3029 };
3030 static const unsigned int pwm2_b_pins[] = {
3031         /* PWM */
3032         RCAR_GP_PIN(1, 11),
3033 };
3034 static const unsigned int pwm2_b_mux[] = {
3035         PWM2_B_MARK,
3036 };
3037 /* - PWM3 --------------------------------------------------------------------*/
3038 static const unsigned int pwm3_a_pins[] = {
3039         /* PWM */
3040         RCAR_GP_PIN(1, 0),
3041 };
3042 static const unsigned int pwm3_a_mux[] = {
3043         PWM3_A_MARK,
3044 };
3045 static const unsigned int pwm3_b_pins[] = {
3046         /* PWM */
3047         RCAR_GP_PIN(2, 2),
3048 };
3049 static const unsigned int pwm3_b_mux[] = {
3050         PWM3_B_MARK,
3051 };
3052 /* - PWM4 --------------------------------------------------------------------*/
3053 static const unsigned int pwm4_a_pins[] = {
3054         /* PWM */
3055         RCAR_GP_PIN(1, 1),
3056 };
3057 static const unsigned int pwm4_a_mux[] = {
3058         PWM4_A_MARK,
3059 };
3060 static const unsigned int pwm4_b_pins[] = {
3061         /* PWM */
3062         RCAR_GP_PIN(2, 3),
3063 };
3064 static const unsigned int pwm4_b_mux[] = {
3065         PWM4_B_MARK,
3066 };
3067 /* - PWM5 --------------------------------------------------------------------*/
3068 static const unsigned int pwm5_a_pins[] = {
3069         /* PWM */
3070         RCAR_GP_PIN(1, 2),
3071 };
3072 static const unsigned int pwm5_a_mux[] = {
3073         PWM5_A_MARK,
3074 };
3075 static const unsigned int pwm5_b_pins[] = {
3076         /* PWM */
3077         RCAR_GP_PIN(2, 4),
3078 };
3079 static const unsigned int pwm5_b_mux[] = {
3080         PWM5_B_MARK,
3081 };
3082 /* - PWM6 --------------------------------------------------------------------*/
3083 static const unsigned int pwm6_a_pins[] = {
3084         /* PWM */
3085         RCAR_GP_PIN(1, 3),
3086 };
3087 static const unsigned int pwm6_a_mux[] = {
3088         PWM6_A_MARK,
3089 };
3090 static const unsigned int pwm6_b_pins[] = {
3091         /* PWM */
3092         RCAR_GP_PIN(2, 5),
3093 };
3094 static const unsigned int pwm6_b_mux[] = {
3095         PWM6_B_MARK,
3096 };
3097
3098 /* - SATA --------------------------------------------------------------------*/
3099 static const unsigned int sata0_devslp_a_pins[] = {
3100         /* DEVSLP */
3101         RCAR_GP_PIN(6, 16),
3102 };
3103
3104 static const unsigned int sata0_devslp_a_mux[] = {
3105         SATA_DEVSLP_A_MARK,
3106 };
3107
3108 static const unsigned int sata0_devslp_b_pins[] = {
3109         /* DEVSLP */
3110         RCAR_GP_PIN(4, 6),
3111 };
3112
3113 static const unsigned int sata0_devslp_b_mux[] = {
3114         SATA_DEVSLP_B_MARK,
3115 };
3116
3117 /* - SCIF0 ------------------------------------------------------------------ */
3118 static const unsigned int scif0_data_pins[] = {
3119         /* RX, TX */
3120         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3121 };
3122 static const unsigned int scif0_data_mux[] = {
3123         RX0_MARK, TX0_MARK,
3124 };
3125 static const unsigned int scif0_clk_pins[] = {
3126         /* SCK */
3127         RCAR_GP_PIN(5, 0),
3128 };
3129 static const unsigned int scif0_clk_mux[] = {
3130         SCK0_MARK,
3131 };
3132 static const unsigned int scif0_ctrl_pins[] = {
3133         /* RTS, CTS */
3134         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3135 };
3136 static const unsigned int scif0_ctrl_mux[] = {
3137         RTS0_N_MARK, CTS0_N_MARK,
3138 };
3139 /* - SCIF1 ------------------------------------------------------------------ */
3140 static const unsigned int scif1_data_a_pins[] = {
3141         /* RX, TX */
3142         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3143 };
3144 static const unsigned int scif1_data_a_mux[] = {
3145         RX1_A_MARK, TX1_A_MARK,
3146 };
3147 static const unsigned int scif1_clk_pins[] = {
3148         /* SCK */
3149         RCAR_GP_PIN(6, 21),
3150 };
3151 static const unsigned int scif1_clk_mux[] = {
3152         SCK1_MARK,
3153 };
3154 static const unsigned int scif1_ctrl_pins[] = {
3155         /* RTS, CTS */
3156         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3157 };
3158 static const unsigned int scif1_ctrl_mux[] = {
3159         RTS1_N_MARK, CTS1_N_MARK,
3160 };
3161 static const unsigned int scif1_data_b_pins[] = {
3162         /* RX, TX */
3163         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3164 };
3165 static const unsigned int scif1_data_b_mux[] = {
3166         RX1_B_MARK, TX1_B_MARK,
3167 };
3168 /* - SCIF2 ------------------------------------------------------------------ */
3169 static const unsigned int scif2_data_a_pins[] = {
3170         /* RX, TX */
3171         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3172 };
3173 static const unsigned int scif2_data_a_mux[] = {
3174         RX2_A_MARK, TX2_A_MARK,
3175 };
3176 static const unsigned int scif2_clk_pins[] = {
3177         /* SCK */
3178         RCAR_GP_PIN(5, 9),
3179 };
3180 static const unsigned int scif2_clk_mux[] = {
3181         SCK2_MARK,
3182 };
3183 static const unsigned int scif2_data_b_pins[] = {
3184         /* RX, TX */
3185         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3186 };
3187 static const unsigned int scif2_data_b_mux[] = {
3188         RX2_B_MARK, TX2_B_MARK,
3189 };
3190 /* - SCIF3 ------------------------------------------------------------------ */
3191 static const unsigned int scif3_data_a_pins[] = {
3192         /* RX, TX */
3193         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3194 };
3195 static const unsigned int scif3_data_a_mux[] = {
3196         RX3_A_MARK, TX3_A_MARK,
3197 };
3198 static const unsigned int scif3_clk_pins[] = {
3199         /* SCK */
3200         RCAR_GP_PIN(1, 22),
3201 };
3202 static const unsigned int scif3_clk_mux[] = {
3203         SCK3_MARK,
3204 };
3205 static const unsigned int scif3_ctrl_pins[] = {
3206         /* RTS, CTS */
3207         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3208 };
3209 static const unsigned int scif3_ctrl_mux[] = {
3210         RTS3_N_MARK, CTS3_N_MARK,
3211 };
3212 static const unsigned int scif3_data_b_pins[] = {
3213         /* RX, TX */
3214         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3215 };
3216 static const unsigned int scif3_data_b_mux[] = {
3217         RX3_B_MARK, TX3_B_MARK,
3218 };
3219 /* - SCIF4 ------------------------------------------------------------------ */
3220 static const unsigned int scif4_data_a_pins[] = {
3221         /* RX, TX */
3222         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3223 };
3224 static const unsigned int scif4_data_a_mux[] = {
3225         RX4_A_MARK, TX4_A_MARK,
3226 };
3227 static const unsigned int scif4_clk_a_pins[] = {
3228         /* SCK */
3229         RCAR_GP_PIN(2, 10),
3230 };
3231 static const unsigned int scif4_clk_a_mux[] = {
3232         SCK4_A_MARK,
3233 };
3234 static const unsigned int scif4_ctrl_a_pins[] = {
3235         /* RTS, CTS */
3236         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3237 };
3238 static const unsigned int scif4_ctrl_a_mux[] = {
3239         RTS4_N_A_MARK, CTS4_N_A_MARK,
3240 };
3241 static const unsigned int scif4_data_b_pins[] = {
3242         /* RX, TX */
3243         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3244 };
3245 static const unsigned int scif4_data_b_mux[] = {
3246         RX4_B_MARK, TX4_B_MARK,
3247 };
3248 static const unsigned int scif4_clk_b_pins[] = {
3249         /* SCK */
3250         RCAR_GP_PIN(1, 5),
3251 };
3252 static const unsigned int scif4_clk_b_mux[] = {
3253         SCK4_B_MARK,
3254 };
3255 static const unsigned int scif4_ctrl_b_pins[] = {
3256         /* RTS, CTS */
3257         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3258 };
3259 static const unsigned int scif4_ctrl_b_mux[] = {
3260         RTS4_N_B_MARK, CTS4_N_B_MARK,
3261 };
3262 static const unsigned int scif4_data_c_pins[] = {
3263         /* RX, TX */
3264         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3265 };
3266 static const unsigned int scif4_data_c_mux[] = {
3267         RX4_C_MARK, TX4_C_MARK,
3268 };
3269 static const unsigned int scif4_clk_c_pins[] = {
3270         /* SCK */
3271         RCAR_GP_PIN(0, 8),
3272 };
3273 static const unsigned int scif4_clk_c_mux[] = {
3274         SCK4_C_MARK,
3275 };
3276 static const unsigned int scif4_ctrl_c_pins[] = {
3277         /* RTS, CTS */
3278         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3279 };
3280 static const unsigned int scif4_ctrl_c_mux[] = {
3281         RTS4_N_C_MARK, CTS4_N_C_MARK,
3282 };
3283 /* - SCIF5 ------------------------------------------------------------------ */
3284 static const unsigned int scif5_data_a_pins[] = {
3285         /* RX, TX */
3286         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3287 };
3288 static const unsigned int scif5_data_a_mux[] = {
3289         RX5_A_MARK, TX5_A_MARK,
3290 };
3291 static const unsigned int scif5_clk_a_pins[] = {
3292         /* SCK */
3293         RCAR_GP_PIN(6, 21),
3294 };
3295 static const unsigned int scif5_clk_a_mux[] = {
3296         SCK5_A_MARK,
3297 };
3298 static const unsigned int scif5_data_b_pins[] = {
3299         /* RX, TX */
3300         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3301 };
3302 static const unsigned int scif5_data_b_mux[] = {
3303         RX5_B_MARK, TX5_B_MARK,
3304 };
3305 static const unsigned int scif5_clk_b_pins[] = {
3306         /* SCK */
3307         RCAR_GP_PIN(5, 0),
3308 };
3309 static const unsigned int scif5_clk_b_mux[] = {
3310         SCK5_B_MARK,
3311 };
3312 /* - SCIF Clock ------------------------------------------------------------- */
3313 static const unsigned int scif_clk_a_pins[] = {
3314         /* SCIF_CLK */
3315         RCAR_GP_PIN(6, 23),
3316 };
3317 static const unsigned int scif_clk_a_mux[] = {
3318         SCIF_CLK_A_MARK,
3319 };
3320 static const unsigned int scif_clk_b_pins[] = {
3321         /* SCIF_CLK */
3322         RCAR_GP_PIN(5, 9),
3323 };
3324 static const unsigned int scif_clk_b_mux[] = {
3325         SCIF_CLK_B_MARK,
3326 };
3327
3328 /* - SDHI0 ------------------------------------------------------------------ */
3329 static const unsigned int sdhi0_data1_pins[] = {
3330         /* D0 */
3331         RCAR_GP_PIN(3, 2),
3332 };
3333
3334 static const unsigned int sdhi0_data1_mux[] = {
3335         SD0_DAT0_MARK,
3336 };
3337
3338 static const unsigned int sdhi0_data4_pins[] = {
3339         /* D[0:3] */
3340         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3341         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3342 };
3343
3344 static const unsigned int sdhi0_data4_mux[] = {
3345         SD0_DAT0_MARK, SD0_DAT1_MARK,
3346         SD0_DAT2_MARK, SD0_DAT3_MARK,
3347 };
3348
3349 static const unsigned int sdhi0_ctrl_pins[] = {
3350         /* CLK, CMD */
3351         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3352 };
3353
3354 static const unsigned int sdhi0_ctrl_mux[] = {
3355         SD0_CLK_MARK, SD0_CMD_MARK,
3356 };
3357
3358 static const unsigned int sdhi0_cd_pins[] = {
3359         /* CD */
3360         RCAR_GP_PIN(3, 12),
3361 };
3362
3363 static const unsigned int sdhi0_cd_mux[] = {
3364         SD0_CD_MARK,
3365 };
3366
3367 static const unsigned int sdhi0_wp_pins[] = {
3368         /* WP */
3369         RCAR_GP_PIN(3, 13),
3370 };
3371
3372 static const unsigned int sdhi0_wp_mux[] = {
3373         SD0_WP_MARK,
3374 };
3375
3376 /* - SDHI1 ------------------------------------------------------------------ */
3377 static const unsigned int sdhi1_data1_pins[] = {
3378         /* D0 */
3379         RCAR_GP_PIN(3, 8),
3380 };
3381
3382 static const unsigned int sdhi1_data1_mux[] = {
3383         SD1_DAT0_MARK,
3384 };
3385
3386 static const unsigned int sdhi1_data4_pins[] = {
3387         /* D[0:3] */
3388         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3389         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3390 };
3391
3392 static const unsigned int sdhi1_data4_mux[] = {
3393         SD1_DAT0_MARK, SD1_DAT1_MARK,
3394         SD1_DAT2_MARK, SD1_DAT3_MARK,
3395 };
3396
3397 static const unsigned int sdhi1_ctrl_pins[] = {
3398         /* CLK, CMD */
3399         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3400 };
3401
3402 static const unsigned int sdhi1_ctrl_mux[] = {
3403         SD1_CLK_MARK, SD1_CMD_MARK,
3404 };
3405
3406 static const unsigned int sdhi1_cd_pins[] = {
3407         /* CD */
3408         RCAR_GP_PIN(3, 14),
3409 };
3410
3411 static const unsigned int sdhi1_cd_mux[] = {
3412         SD1_CD_MARK,
3413 };
3414
3415 static const unsigned int sdhi1_wp_pins[] = {
3416         /* WP */
3417         RCAR_GP_PIN(3, 15),
3418 };
3419
3420 static const unsigned int sdhi1_wp_mux[] = {
3421         SD1_WP_MARK,
3422 };
3423
3424 /* - SDHI2 ------------------------------------------------------------------ */
3425 static const unsigned int sdhi2_data1_pins[] = {
3426         /* D0 */
3427         RCAR_GP_PIN(4, 2),
3428 };
3429
3430 static const unsigned int sdhi2_data1_mux[] = {
3431         SD2_DAT0_MARK,
3432 };
3433
3434 static const unsigned int sdhi2_data4_pins[] = {
3435         /* D[0:3] */
3436         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3437         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3438 };
3439
3440 static const unsigned int sdhi2_data4_mux[] = {
3441         SD2_DAT0_MARK, SD2_DAT1_MARK,
3442         SD2_DAT2_MARK, SD2_DAT3_MARK,
3443 };
3444
3445 static const unsigned int sdhi2_data8_pins[] = {
3446         /* D[0:7] */
3447         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3448         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3449         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3450         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3451 };
3452
3453 static const unsigned int sdhi2_data8_mux[] = {
3454         SD2_DAT0_MARK, SD2_DAT1_MARK,
3455         SD2_DAT2_MARK, SD2_DAT3_MARK,
3456         SD2_DAT4_MARK, SD2_DAT5_MARK,
3457         SD2_DAT6_MARK, SD2_DAT7_MARK,
3458 };
3459
3460 static const unsigned int sdhi2_ctrl_pins[] = {
3461         /* CLK, CMD */
3462         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3463 };
3464
3465 static const unsigned int sdhi2_ctrl_mux[] = {
3466         SD2_CLK_MARK, SD2_CMD_MARK,
3467 };
3468
3469 static const unsigned int sdhi2_cd_a_pins[] = {
3470         /* CD */
3471         RCAR_GP_PIN(4, 13),
3472 };
3473
3474 static const unsigned int sdhi2_cd_a_mux[] = {
3475         SD2_CD_A_MARK,
3476 };
3477
3478 static const unsigned int sdhi2_cd_b_pins[] = {
3479         /* CD */
3480         RCAR_GP_PIN(5, 10),
3481 };
3482
3483 static const unsigned int sdhi2_cd_b_mux[] = {
3484         SD2_CD_B_MARK,
3485 };
3486
3487 static const unsigned int sdhi2_wp_a_pins[] = {
3488         /* WP */
3489         RCAR_GP_PIN(4, 14),
3490 };
3491
3492 static const unsigned int sdhi2_wp_a_mux[] = {
3493         SD2_WP_A_MARK,
3494 };
3495
3496 static const unsigned int sdhi2_wp_b_pins[] = {
3497         /* WP */
3498         RCAR_GP_PIN(5, 11),
3499 };
3500
3501 static const unsigned int sdhi2_wp_b_mux[] = {
3502         SD2_WP_B_MARK,
3503 };
3504
3505 static const unsigned int sdhi2_ds_pins[] = {
3506         /* DS */
3507         RCAR_GP_PIN(4, 6),
3508 };
3509
3510 static const unsigned int sdhi2_ds_mux[] = {
3511         SD2_DS_MARK,
3512 };
3513
3514 /* - SDHI3 ------------------------------------------------------------------ */
3515 static const unsigned int sdhi3_data1_pins[] = {
3516         /* D0 */
3517         RCAR_GP_PIN(4, 9),
3518 };
3519
3520 static const unsigned int sdhi3_data1_mux[] = {
3521         SD3_DAT0_MARK,
3522 };
3523
3524 static const unsigned int sdhi3_data4_pins[] = {
3525         /* D[0:3] */
3526         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3527         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3528 };
3529
3530 static const unsigned int sdhi3_data4_mux[] = {
3531         SD3_DAT0_MARK, SD3_DAT1_MARK,
3532         SD3_DAT2_MARK, SD3_DAT3_MARK,
3533 };
3534
3535 static const unsigned int sdhi3_data8_pins[] = {
3536         /* D[0:7] */
3537         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3538         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3539         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3540         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3541 };
3542
3543 static const unsigned int sdhi3_data8_mux[] = {
3544         SD3_DAT0_MARK, SD3_DAT1_MARK,
3545         SD3_DAT2_MARK, SD3_DAT3_MARK,
3546         SD3_DAT4_MARK, SD3_DAT5_MARK,
3547         SD3_DAT6_MARK, SD3_DAT7_MARK,
3548 };
3549
3550 static const unsigned int sdhi3_ctrl_pins[] = {
3551         /* CLK, CMD */
3552         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3553 };
3554
3555 static const unsigned int sdhi3_ctrl_mux[] = {
3556         SD3_CLK_MARK, SD3_CMD_MARK,
3557 };
3558
3559 static const unsigned int sdhi3_cd_pins[] = {
3560         /* CD */
3561         RCAR_GP_PIN(4, 15),
3562 };
3563
3564 static const unsigned int sdhi3_cd_mux[] = {
3565         SD3_CD_MARK,
3566 };
3567
3568 static const unsigned int sdhi3_wp_pins[] = {
3569         /* WP */
3570         RCAR_GP_PIN(4, 16),
3571 };
3572
3573 static const unsigned int sdhi3_wp_mux[] = {
3574         SD3_WP_MARK,
3575 };
3576
3577 static const unsigned int sdhi3_ds_pins[] = {
3578         /* DS */
3579         RCAR_GP_PIN(4, 17),
3580 };
3581
3582 static const unsigned int sdhi3_ds_mux[] = {
3583         SD3_DS_MARK,
3584 };
3585
3586 /* - SSI -------------------------------------------------------------------- */
3587 static const unsigned int ssi0_data_pins[] = {
3588         /* SDATA */
3589         RCAR_GP_PIN(6, 2),
3590 };
3591 static const unsigned int ssi0_data_mux[] = {
3592         SSI_SDATA0_MARK,
3593 };
3594 static const unsigned int ssi01239_ctrl_pins[] = {
3595         /* SCK, WS */
3596         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3597 };
3598 static const unsigned int ssi01239_ctrl_mux[] = {
3599         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3600 };
3601 static const unsigned int ssi1_data_a_pins[] = {
3602         /* SDATA */
3603         RCAR_GP_PIN(6, 3),
3604 };
3605 static const unsigned int ssi1_data_a_mux[] = {
3606         SSI_SDATA1_A_MARK,
3607 };
3608 static const unsigned int ssi1_data_b_pins[] = {
3609         /* SDATA */
3610         RCAR_GP_PIN(5, 12),
3611 };
3612 static const unsigned int ssi1_data_b_mux[] = {
3613         SSI_SDATA1_B_MARK,
3614 };
3615 static const unsigned int ssi1_ctrl_a_pins[] = {
3616         /* SCK, WS */
3617         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3618 };
3619 static const unsigned int ssi1_ctrl_a_mux[] = {
3620         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3621 };
3622 static const unsigned int ssi1_ctrl_b_pins[] = {
3623         /* SCK, WS */
3624         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3625 };
3626 static const unsigned int ssi1_ctrl_b_mux[] = {
3627         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3628 };
3629 static const unsigned int ssi2_data_a_pins[] = {
3630         /* SDATA */
3631         RCAR_GP_PIN(6, 4),
3632 };
3633 static const unsigned int ssi2_data_a_mux[] = {
3634         SSI_SDATA2_A_MARK,
3635 };
3636 static const unsigned int ssi2_data_b_pins[] = {
3637         /* SDATA */
3638         RCAR_GP_PIN(5, 13),
3639 };
3640 static const unsigned int ssi2_data_b_mux[] = {
3641         SSI_SDATA2_B_MARK,
3642 };
3643 static const unsigned int ssi2_ctrl_a_pins[] = {
3644         /* SCK, WS */
3645         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3646 };
3647 static const unsigned int ssi2_ctrl_a_mux[] = {
3648         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3649 };
3650 static const unsigned int ssi2_ctrl_b_pins[] = {
3651         /* SCK, WS */
3652         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3653 };
3654 static const unsigned int ssi2_ctrl_b_mux[] = {
3655         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3656 };
3657 static const unsigned int ssi3_data_pins[] = {
3658         /* SDATA */
3659         RCAR_GP_PIN(6, 7),
3660 };
3661 static const unsigned int ssi3_data_mux[] = {
3662         SSI_SDATA3_MARK,
3663 };
3664 static const unsigned int ssi349_ctrl_pins[] = {
3665         /* SCK, WS */
3666         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3667 };
3668 static const unsigned int ssi349_ctrl_mux[] = {
3669         SSI_SCK349_MARK, SSI_WS349_MARK,
3670 };
3671 static const unsigned int ssi4_data_pins[] = {
3672         /* SDATA */
3673         RCAR_GP_PIN(6, 10),
3674 };
3675 static const unsigned int ssi4_data_mux[] = {
3676         SSI_SDATA4_MARK,
3677 };
3678 static const unsigned int ssi4_ctrl_pins[] = {
3679         /* SCK, WS */
3680         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3681 };
3682 static const unsigned int ssi4_ctrl_mux[] = {
3683         SSI_SCK4_MARK, SSI_WS4_MARK,
3684 };
3685 static const unsigned int ssi5_data_pins[] = {
3686         /* SDATA */
3687         RCAR_GP_PIN(6, 13),
3688 };
3689 static const unsigned int ssi5_data_mux[] = {
3690         SSI_SDATA5_MARK,
3691 };
3692 static const unsigned int ssi5_ctrl_pins[] = {
3693         /* SCK, WS */
3694         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3695 };
3696 static const unsigned int ssi5_ctrl_mux[] = {
3697         SSI_SCK5_MARK, SSI_WS5_MARK,
3698 };
3699 static const unsigned int ssi6_data_pins[] = {
3700         /* SDATA */
3701         RCAR_GP_PIN(6, 16),
3702 };
3703 static const unsigned int ssi6_data_mux[] = {
3704         SSI_SDATA6_MARK,
3705 };
3706 static const unsigned int ssi6_ctrl_pins[] = {
3707         /* SCK, WS */
3708         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3709 };
3710 static const unsigned int ssi6_ctrl_mux[] = {
3711         SSI_SCK6_MARK, SSI_WS6_MARK,
3712 };
3713 static const unsigned int ssi7_data_pins[] = {
3714         /* SDATA */
3715         RCAR_GP_PIN(6, 19),
3716 };
3717 static const unsigned int ssi7_data_mux[] = {
3718         SSI_SDATA7_MARK,
3719 };
3720 static const unsigned int ssi78_ctrl_pins[] = {
3721         /* SCK, WS */
3722         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3723 };
3724 static const unsigned int ssi78_ctrl_mux[] = {
3725         SSI_SCK78_MARK, SSI_WS78_MARK,
3726 };
3727 static const unsigned int ssi8_data_pins[] = {
3728         /* SDATA */
3729         RCAR_GP_PIN(6, 20),
3730 };
3731 static const unsigned int ssi8_data_mux[] = {
3732         SSI_SDATA8_MARK,
3733 };
3734 static const unsigned int ssi9_data_a_pins[] = {
3735         /* SDATA */
3736         RCAR_GP_PIN(6, 21),
3737 };
3738 static const unsigned int ssi9_data_a_mux[] = {
3739         SSI_SDATA9_A_MARK,
3740 };
3741 static const unsigned int ssi9_data_b_pins[] = {
3742         /* SDATA */
3743         RCAR_GP_PIN(5, 14),
3744 };
3745 static const unsigned int ssi9_data_b_mux[] = {
3746         SSI_SDATA9_B_MARK,
3747 };
3748 static const unsigned int ssi9_ctrl_a_pins[] = {
3749         /* SCK, WS */
3750         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3751 };
3752 static const unsigned int ssi9_ctrl_a_mux[] = {
3753         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3754 };
3755 static const unsigned int ssi9_ctrl_b_pins[] = {
3756         /* SCK, WS */
3757         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3758 };
3759 static const unsigned int ssi9_ctrl_b_mux[] = {
3760         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3761 };
3762
3763
3764 /* - USB0 ------------------------------------------------------------------- */
3765 static const unsigned int usb0_pins[] = {
3766         /* PWEN, OVC */
3767         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3768 };
3769
3770 static const unsigned int usb0_mux[] = {
3771         USB0_PWEN_MARK, USB0_OVC_MARK,
3772 };
3773
3774 /* - USB1 ------------------------------------------------------------------- */
3775 static const unsigned int usb1_pins[] = {
3776         /* PWEN, OVC */
3777         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3778 };
3779
3780 static const unsigned int usb1_mux[] = {
3781         USB1_PWEN_MARK, USB1_OVC_MARK,
3782 };
3783
3784 /* - USB30 ------------------------------------------------------------------ */
3785 static const unsigned int usb30_pins[] = {
3786         /* PWEN, OVC */
3787         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3788 };
3789
3790 static const unsigned int usb30_mux[] = {
3791         USB30_PWEN_MARK, USB30_OVC_MARK,
3792 };
3793
3794 /* - VIN4 ------------------------------------------------------------------- */
3795 static const unsigned int vin4_data18_a_pins[] = {
3796         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3797         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3798         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3799         RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
3800         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
3801         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3802         RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
3803         RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
3804         RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
3805 };
3806
3807 static const unsigned int vin4_data18_a_mux[] = {
3808         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3809         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3810         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3811         VI4_DATA10_MARK,  VI4_DATA11_MARK,
3812         VI4_DATA12_MARK,  VI4_DATA13_MARK,
3813         VI4_DATA14_MARK,  VI4_DATA15_MARK,
3814         VI4_DATA18_MARK,  VI4_DATA19_MARK,
3815         VI4_DATA20_MARK,  VI4_DATA21_MARK,
3816         VI4_DATA22_MARK,  VI4_DATA23_MARK,
3817 };
3818
3819 static const union vin_data vin4_data_a_pins = {
3820         .data24 = {
3821                 RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
3822                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3823                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3824                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3825                 RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
3826                 RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
3827                 RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
3828                 RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3829                 RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
3830                 RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
3831                 RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
3832                 RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
3833         },
3834 };
3835
3836 static const union vin_data vin4_data_a_mux = {
3837         .data24 = {
3838                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3839                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3840                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3841                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3842                 VI4_DATA8_MARK,   VI4_DATA9_MARK,
3843                 VI4_DATA10_MARK,  VI4_DATA11_MARK,
3844                 VI4_DATA12_MARK,  VI4_DATA13_MARK,
3845                 VI4_DATA14_MARK,  VI4_DATA15_MARK,
3846                 VI4_DATA16_MARK,  VI4_DATA17_MARK,
3847                 VI4_DATA18_MARK,  VI4_DATA19_MARK,
3848                 VI4_DATA20_MARK,  VI4_DATA21_MARK,
3849                 VI4_DATA22_MARK,  VI4_DATA23_MARK,
3850         },
3851 };
3852
3853 static const unsigned int vin4_data18_b_pins[] = {
3854         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3855         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3856         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3857         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3858         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3859         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3860         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3861         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3862         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3863 };
3864
3865 static const unsigned int vin4_data18_b_mux[] = {
3866         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3867         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3868         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3869         VI4_DATA10_MARK,  VI4_DATA11_MARK,
3870         VI4_DATA12_MARK,  VI4_DATA13_MARK,
3871         VI4_DATA14_MARK,  VI4_DATA15_MARK,
3872         VI4_DATA18_MARK,  VI4_DATA19_MARK,
3873         VI4_DATA20_MARK,  VI4_DATA21_MARK,
3874         VI4_DATA22_MARK,  VI4_DATA23_MARK,
3875 };
3876
3877 static const union vin_data vin4_data_b_pins = {
3878         .data24 = {
3879                 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3880                 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3881                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3882                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3883                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3884                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3885                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3886                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3887                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3888                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3889                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3890                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3891         },
3892 };
3893
3894 static const union vin_data vin4_data_b_mux = {
3895         .data24 = {
3896                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3897                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3898                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3899                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3900                 VI4_DATA8_MARK,   VI4_DATA9_MARK,
3901                 VI4_DATA10_MARK,  VI4_DATA11_MARK,
3902                 VI4_DATA12_MARK,  VI4_DATA13_MARK,
3903                 VI4_DATA14_MARK,  VI4_DATA15_MARK,
3904                 VI4_DATA16_MARK,  VI4_DATA17_MARK,
3905                 VI4_DATA18_MARK,  VI4_DATA19_MARK,
3906                 VI4_DATA20_MARK,  VI4_DATA21_MARK,
3907                 VI4_DATA22_MARK,  VI4_DATA23_MARK,
3908         },
3909 };
3910
3911 static const unsigned int vin4_sync_pins[] = {
3912         /* VSYNC_N, HSYNC_N */
3913         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3914 };
3915
3916 static const unsigned int vin4_sync_mux[] = {
3917         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3918 };
3919
3920 static const unsigned int vin4_field_pins[] = {
3921         RCAR_GP_PIN(1, 16),
3922 };
3923
3924 static const unsigned int vin4_field_mux[] = {
3925         VI4_FIELD_MARK,
3926 };
3927
3928 static const unsigned int vin4_clkenb_pins[] = {
3929         RCAR_GP_PIN(1, 19),
3930 };
3931
3932 static const unsigned int vin4_clkenb_mux[] = {
3933         VI4_CLKENB_MARK,
3934 };
3935
3936 static const unsigned int vin4_clk_pins[] = {
3937         RCAR_GP_PIN(1, 27),
3938 };
3939
3940 static const unsigned int vin4_clk_mux[] = {
3941         VI4_CLK_MARK,
3942 };
3943
3944 /* - VIN5 ------------------------------------------------------------------- */
3945 static const union vin_data16 vin5_data_pins = {
3946         .data16 = {
3947                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3948                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3949                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3950                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3951                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3952                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3953                 RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
3954                 RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3955         },
3956 };
3957
3958 static const union vin_data16 vin5_data_mux = {
3959         .data16 = {
3960                 VI5_DATA0_MARK, VI5_DATA1_MARK,
3961                 VI5_DATA2_MARK, VI5_DATA3_MARK,
3962                 VI5_DATA4_MARK, VI5_DATA5_MARK,
3963                 VI5_DATA6_MARK, VI5_DATA7_MARK,
3964                 VI5_DATA8_MARK,  VI5_DATA9_MARK,
3965                 VI5_DATA10_MARK, VI5_DATA11_MARK,
3966                 VI5_DATA12_MARK, VI5_DATA13_MARK,
3967                 VI5_DATA14_MARK, VI5_DATA15_MARK,
3968         },
3969 };
3970
3971 static const unsigned int vin5_sync_pins[] = {
3972         /* VSYNC_N, HSYNC_N */
3973         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
3974 };
3975
3976 static const unsigned int vin5_sync_mux[] = {
3977         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
3978 };
3979
3980 static const unsigned int vin5_field_pins[] = {
3981         RCAR_GP_PIN(1, 11),
3982 };
3983
3984 static const unsigned int vin5_field_mux[] = {
3985         VI5_FIELD_MARK,
3986 };
3987
3988 static const unsigned int vin5_clkenb_pins[] = {
3989         RCAR_GP_PIN(1, 20),
3990 };
3991
3992 static const unsigned int vin5_clkenb_mux[] = {
3993         VI5_CLKENB_MARK,
3994 };
3995
3996 static const unsigned int vin5_clk_pins[] = {
3997         RCAR_GP_PIN(1, 21),
3998 };
3999
4000 static const unsigned int vin5_clk_mux[] = {
4001         VI5_CLK_MARK,
4002 };
4003
4004 static const struct sh_pfc_pin_group pinmux_groups[] = {
4005         SH_PFC_PIN_GROUP(audio_clk_a_a),
4006         SH_PFC_PIN_GROUP(audio_clk_a_b),
4007         SH_PFC_PIN_GROUP(audio_clk_a_c),
4008         SH_PFC_PIN_GROUP(audio_clk_b_a),
4009         SH_PFC_PIN_GROUP(audio_clk_b_b),
4010         SH_PFC_PIN_GROUP(audio_clk_c_a),
4011         SH_PFC_PIN_GROUP(audio_clk_c_b),
4012         SH_PFC_PIN_GROUP(audio_clkout_a),
4013         SH_PFC_PIN_GROUP(audio_clkout_b),
4014         SH_PFC_PIN_GROUP(audio_clkout_c),
4015         SH_PFC_PIN_GROUP(audio_clkout_d),
4016         SH_PFC_PIN_GROUP(audio_clkout1_a),
4017         SH_PFC_PIN_GROUP(audio_clkout1_b),
4018         SH_PFC_PIN_GROUP(audio_clkout2_a),
4019         SH_PFC_PIN_GROUP(audio_clkout2_b),
4020         SH_PFC_PIN_GROUP(audio_clkout3_a),
4021         SH_PFC_PIN_GROUP(audio_clkout3_b),
4022         SH_PFC_PIN_GROUP(avb_link),
4023         SH_PFC_PIN_GROUP(avb_magic),
4024         SH_PFC_PIN_GROUP(avb_phy_int),
4025         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
4026         SH_PFC_PIN_GROUP(avb_mdio),
4027         SH_PFC_PIN_GROUP(avb_mii),
4028         SH_PFC_PIN_GROUP(avb_avtp_pps),
4029         SH_PFC_PIN_GROUP(avb_avtp_match_a),
4030         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4031         SH_PFC_PIN_GROUP(avb_avtp_match_b),
4032         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4033         SH_PFC_PIN_GROUP(can0_data_a),
4034         SH_PFC_PIN_GROUP(can0_data_b),
4035         SH_PFC_PIN_GROUP(can1_data),
4036         SH_PFC_PIN_GROUP(can_clk),
4037         SH_PFC_PIN_GROUP(canfd0_data_a),
4038         SH_PFC_PIN_GROUP(canfd0_data_b),
4039         SH_PFC_PIN_GROUP(canfd1_data),
4040         SH_PFC_PIN_GROUP(du_rgb666),
4041         SH_PFC_PIN_GROUP(du_rgb888),
4042         SH_PFC_PIN_GROUP(du_clk_out_0),
4043         SH_PFC_PIN_GROUP(du_clk_out_1),
4044         SH_PFC_PIN_GROUP(du_sync),
4045         SH_PFC_PIN_GROUP(du_oddf),
4046         SH_PFC_PIN_GROUP(du_cde),
4047         SH_PFC_PIN_GROUP(du_disp),
4048         SH_PFC_PIN_GROUP(hscif0_data),
4049         SH_PFC_PIN_GROUP(hscif0_clk),
4050         SH_PFC_PIN_GROUP(hscif0_ctrl),
4051         SH_PFC_PIN_GROUP(hscif1_data_a),
4052         SH_PFC_PIN_GROUP(hscif1_clk_a),
4053         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4054         SH_PFC_PIN_GROUP(hscif1_data_b),
4055         SH_PFC_PIN_GROUP(hscif1_clk_b),
4056         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4057         SH_PFC_PIN_GROUP(hscif2_data_a),
4058         SH_PFC_PIN_GROUP(hscif2_clk_a),
4059         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4060         SH_PFC_PIN_GROUP(hscif2_data_b),
4061         SH_PFC_PIN_GROUP(hscif2_clk_b),
4062         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4063         SH_PFC_PIN_GROUP(hscif2_data_c),
4064         SH_PFC_PIN_GROUP(hscif2_clk_c),
4065         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4066         SH_PFC_PIN_GROUP(hscif3_data_a),
4067         SH_PFC_PIN_GROUP(hscif3_clk),
4068         SH_PFC_PIN_GROUP(hscif3_ctrl),
4069         SH_PFC_PIN_GROUP(hscif3_data_b),
4070         SH_PFC_PIN_GROUP(hscif3_data_c),
4071         SH_PFC_PIN_GROUP(hscif3_data_d),
4072         SH_PFC_PIN_GROUP(hscif4_data_a),
4073         SH_PFC_PIN_GROUP(hscif4_clk),
4074         SH_PFC_PIN_GROUP(hscif4_ctrl),
4075         SH_PFC_PIN_GROUP(hscif4_data_b),
4076         SH_PFC_PIN_GROUP(i2c1_a),
4077         SH_PFC_PIN_GROUP(i2c1_b),
4078         SH_PFC_PIN_GROUP(i2c2_a),
4079         SH_PFC_PIN_GROUP(i2c2_b),
4080         SH_PFC_PIN_GROUP(i2c6_a),
4081         SH_PFC_PIN_GROUP(i2c6_b),
4082         SH_PFC_PIN_GROUP(i2c6_c),
4083         SH_PFC_PIN_GROUP(intc_ex_irq0),
4084         SH_PFC_PIN_GROUP(intc_ex_irq1),
4085         SH_PFC_PIN_GROUP(intc_ex_irq2),
4086         SH_PFC_PIN_GROUP(intc_ex_irq3),
4087         SH_PFC_PIN_GROUP(intc_ex_irq4),
4088         SH_PFC_PIN_GROUP(intc_ex_irq5),
4089         SH_PFC_PIN_GROUP(msiof0_clk),
4090         SH_PFC_PIN_GROUP(msiof0_sync),
4091         SH_PFC_PIN_GROUP(msiof0_ss1),
4092         SH_PFC_PIN_GROUP(msiof0_ss2),
4093         SH_PFC_PIN_GROUP(msiof0_txd),
4094         SH_PFC_PIN_GROUP(msiof0_rxd),
4095         SH_PFC_PIN_GROUP(msiof1_clk_a),
4096         SH_PFC_PIN_GROUP(msiof1_sync_a),
4097         SH_PFC_PIN_GROUP(msiof1_ss1_a),
4098         SH_PFC_PIN_GROUP(msiof1_ss2_a),
4099         SH_PFC_PIN_GROUP(msiof1_txd_a),
4100         SH_PFC_PIN_GROUP(msiof1_rxd_a),
4101         SH_PFC_PIN_GROUP(msiof1_clk_b),
4102         SH_PFC_PIN_GROUP(msiof1_sync_b),
4103         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4104         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4105         SH_PFC_PIN_GROUP(msiof1_txd_b),
4106         SH_PFC_PIN_GROUP(msiof1_rxd_b),
4107         SH_PFC_PIN_GROUP(msiof1_clk_c),
4108         SH_PFC_PIN_GROUP(msiof1_sync_c),
4109         SH_PFC_PIN_GROUP(msiof1_ss1_c),
4110         SH_PFC_PIN_GROUP(msiof1_ss2_c),
4111         SH_PFC_PIN_GROUP(msiof1_txd_c),
4112         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4113         SH_PFC_PIN_GROUP(msiof1_clk_d),
4114         SH_PFC_PIN_GROUP(msiof1_sync_d),
4115         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4116         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4117         SH_PFC_PIN_GROUP(msiof1_txd_d),
4118         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4119         SH_PFC_PIN_GROUP(msiof1_clk_e),
4120         SH_PFC_PIN_GROUP(msiof1_sync_e),
4121         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4122         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4123         SH_PFC_PIN_GROUP(msiof1_txd_e),
4124         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4125         SH_PFC_PIN_GROUP(msiof1_clk_f),
4126         SH_PFC_PIN_GROUP(msiof1_sync_f),
4127         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4128         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4129         SH_PFC_PIN_GROUP(msiof1_txd_f),
4130         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4131         SH_PFC_PIN_GROUP(msiof1_clk_g),
4132         SH_PFC_PIN_GROUP(msiof1_sync_g),
4133         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4134         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4135         SH_PFC_PIN_GROUP(msiof1_txd_g),
4136         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4137         SH_PFC_PIN_GROUP(msiof2_clk_a),
4138         SH_PFC_PIN_GROUP(msiof2_sync_a),
4139         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4140         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4141         SH_PFC_PIN_GROUP(msiof2_txd_a),
4142         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4143         SH_PFC_PIN_GROUP(msiof2_clk_b),
4144         SH_PFC_PIN_GROUP(msiof2_sync_b),
4145         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4146         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4147         SH_PFC_PIN_GROUP(msiof2_txd_b),
4148         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4149         SH_PFC_PIN_GROUP(msiof2_clk_c),
4150         SH_PFC_PIN_GROUP(msiof2_sync_c),
4151         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4152         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4153         SH_PFC_PIN_GROUP(msiof2_txd_c),
4154         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4155         SH_PFC_PIN_GROUP(msiof2_clk_d),
4156         SH_PFC_PIN_GROUP(msiof2_sync_d),
4157         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4158         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4159         SH_PFC_PIN_GROUP(msiof2_txd_d),
4160         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4161         SH_PFC_PIN_GROUP(msiof3_clk_a),
4162         SH_PFC_PIN_GROUP(msiof3_sync_a),
4163         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4164         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4165         SH_PFC_PIN_GROUP(msiof3_txd_a),
4166         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4167         SH_PFC_PIN_GROUP(msiof3_clk_b),
4168         SH_PFC_PIN_GROUP(msiof3_sync_b),
4169         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4170         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4171         SH_PFC_PIN_GROUP(msiof3_txd_b),
4172         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4173         SH_PFC_PIN_GROUP(msiof3_clk_c),
4174         SH_PFC_PIN_GROUP(msiof3_sync_c),
4175         SH_PFC_PIN_GROUP(msiof3_txd_c),
4176         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4177         SH_PFC_PIN_GROUP(msiof3_clk_d),
4178         SH_PFC_PIN_GROUP(msiof3_sync_d),
4179         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4180         SH_PFC_PIN_GROUP(msiof3_txd_d),
4181         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4182         SH_PFC_PIN_GROUP(msiof3_clk_e),
4183         SH_PFC_PIN_GROUP(msiof3_sync_e),
4184         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4185         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4186         SH_PFC_PIN_GROUP(msiof3_txd_e),
4187         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4188         SH_PFC_PIN_GROUP(pwm0),
4189         SH_PFC_PIN_GROUP(pwm1_a),
4190         SH_PFC_PIN_GROUP(pwm1_b),
4191         SH_PFC_PIN_GROUP(pwm2_a),
4192         SH_PFC_PIN_GROUP(pwm2_b),
4193         SH_PFC_PIN_GROUP(pwm3_a),
4194         SH_PFC_PIN_GROUP(pwm3_b),
4195         SH_PFC_PIN_GROUP(pwm4_a),
4196         SH_PFC_PIN_GROUP(pwm4_b),
4197         SH_PFC_PIN_GROUP(pwm5_a),
4198         SH_PFC_PIN_GROUP(pwm5_b),
4199         SH_PFC_PIN_GROUP(pwm6_a),
4200         SH_PFC_PIN_GROUP(pwm6_b),
4201         SH_PFC_PIN_GROUP(sata0_devslp_a),
4202         SH_PFC_PIN_GROUP(sata0_devslp_b),
4203         SH_PFC_PIN_GROUP(scif0_data),
4204         SH_PFC_PIN_GROUP(scif0_clk),
4205         SH_PFC_PIN_GROUP(scif0_ctrl),
4206         SH_PFC_PIN_GROUP(scif1_data_a),
4207         SH_PFC_PIN_GROUP(scif1_clk),
4208         SH_PFC_PIN_GROUP(scif1_ctrl),
4209         SH_PFC_PIN_GROUP(scif1_data_b),
4210         SH_PFC_PIN_GROUP(scif2_data_a),
4211         SH_PFC_PIN_GROUP(scif2_clk),
4212         SH_PFC_PIN_GROUP(scif2_data_b),
4213         SH_PFC_PIN_GROUP(scif3_data_a),
4214         SH_PFC_PIN_GROUP(scif3_clk),
4215         SH_PFC_PIN_GROUP(scif3_ctrl),
4216         SH_PFC_PIN_GROUP(scif3_data_b),
4217         SH_PFC_PIN_GROUP(scif4_data_a),
4218         SH_PFC_PIN_GROUP(scif4_clk_a),
4219         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4220         SH_PFC_PIN_GROUP(scif4_data_b),
4221         SH_PFC_PIN_GROUP(scif4_clk_b),
4222         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4223         SH_PFC_PIN_GROUP(scif4_data_c),
4224         SH_PFC_PIN_GROUP(scif4_clk_c),
4225         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4226         SH_PFC_PIN_GROUP(scif5_data_a),
4227         SH_PFC_PIN_GROUP(scif5_clk_a),
4228         SH_PFC_PIN_GROUP(scif5_data_b),
4229         SH_PFC_PIN_GROUP(scif5_clk_b),
4230         SH_PFC_PIN_GROUP(scif_clk_a),
4231         SH_PFC_PIN_GROUP(scif_clk_b),
4232         SH_PFC_PIN_GROUP(sdhi0_data1),
4233         SH_PFC_PIN_GROUP(sdhi0_data4),
4234         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4235         SH_PFC_PIN_GROUP(sdhi0_cd),
4236         SH_PFC_PIN_GROUP(sdhi0_wp),
4237         SH_PFC_PIN_GROUP(sdhi1_data1),
4238         SH_PFC_PIN_GROUP(sdhi1_data4),
4239         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4240         SH_PFC_PIN_GROUP(sdhi1_cd),
4241         SH_PFC_PIN_GROUP(sdhi1_wp),
4242         SH_PFC_PIN_GROUP(sdhi2_data1),
4243         SH_PFC_PIN_GROUP(sdhi2_data4),
4244         SH_PFC_PIN_GROUP(sdhi2_data8),
4245         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4246         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4247         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4248         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4249         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4250         SH_PFC_PIN_GROUP(sdhi2_ds),
4251         SH_PFC_PIN_GROUP(sdhi3_data1),
4252         SH_PFC_PIN_GROUP(sdhi3_data4),
4253         SH_PFC_PIN_GROUP(sdhi3_data8),
4254         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4255         SH_PFC_PIN_GROUP(sdhi3_cd),
4256         SH_PFC_PIN_GROUP(sdhi3_wp),
4257         SH_PFC_PIN_GROUP(sdhi3_ds),
4258         SH_PFC_PIN_GROUP(ssi0_data),
4259         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4260         SH_PFC_PIN_GROUP(ssi1_data_a),
4261         SH_PFC_PIN_GROUP(ssi1_data_b),
4262         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4263         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4264         SH_PFC_PIN_GROUP(ssi2_data_a),
4265         SH_PFC_PIN_GROUP(ssi2_data_b),
4266         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4267         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4268         SH_PFC_PIN_GROUP(ssi3_data),
4269         SH_PFC_PIN_GROUP(ssi349_ctrl),
4270         SH_PFC_PIN_GROUP(ssi4_data),
4271         SH_PFC_PIN_GROUP(ssi4_ctrl),
4272         SH_PFC_PIN_GROUP(ssi5_data),
4273         SH_PFC_PIN_GROUP(ssi5_ctrl),
4274         SH_PFC_PIN_GROUP(ssi6_data),
4275         SH_PFC_PIN_GROUP(ssi6_ctrl),
4276         SH_PFC_PIN_GROUP(ssi7_data),
4277         SH_PFC_PIN_GROUP(ssi78_ctrl),
4278         SH_PFC_PIN_GROUP(ssi8_data),
4279         SH_PFC_PIN_GROUP(ssi9_data_a),
4280         SH_PFC_PIN_GROUP(ssi9_data_b),
4281         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4282         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4283         SH_PFC_PIN_GROUP(usb0),
4284         SH_PFC_PIN_GROUP(usb1),
4285         SH_PFC_PIN_GROUP(usb30),
4286         VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4287         VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4288         VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4289         VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4290         SH_PFC_PIN_GROUP(vin4_data18_a),
4291         VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4292         VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4293         VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4294         VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4295         VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4296         VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4297         SH_PFC_PIN_GROUP(vin4_data18_b),
4298         VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4299         VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4300         SH_PFC_PIN_GROUP(vin4_sync),
4301         SH_PFC_PIN_GROUP(vin4_field),
4302         SH_PFC_PIN_GROUP(vin4_clkenb),
4303         SH_PFC_PIN_GROUP(vin4_clk),
4304         VIN_DATA_PIN_GROUP(vin5_data, 8),
4305         VIN_DATA_PIN_GROUP(vin5_data, 10),
4306         VIN_DATA_PIN_GROUP(vin5_data, 12),
4307         VIN_DATA_PIN_GROUP(vin5_data, 16),
4308         SH_PFC_PIN_GROUP(vin5_sync),
4309         SH_PFC_PIN_GROUP(vin5_field),
4310         SH_PFC_PIN_GROUP(vin5_clkenb),
4311         SH_PFC_PIN_GROUP(vin5_clk),
4312 };
4313
4314 static const char * const audio_clk_groups[] = {
4315         "audio_clk_a_a",
4316         "audio_clk_a_b",
4317         "audio_clk_a_c",
4318         "audio_clk_b_a",
4319         "audio_clk_b_b",
4320         "audio_clk_c_a",
4321         "audio_clk_c_b",
4322         "audio_clkout_a",
4323         "audio_clkout_b",
4324         "audio_clkout_c",
4325         "audio_clkout_d",
4326         "audio_clkout1_a",
4327         "audio_clkout1_b",
4328         "audio_clkout2_a",
4329         "audio_clkout2_b",
4330         "audio_clkout3_a",
4331         "audio_clkout3_b",
4332 };
4333
4334 static const char * const avb_groups[] = {
4335         "avb_link",
4336         "avb_magic",
4337         "avb_phy_int",
4338         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4339         "avb_mdio",
4340         "avb_mii",
4341         "avb_avtp_pps",
4342         "avb_avtp_match_a",
4343         "avb_avtp_capture_a",
4344         "avb_avtp_match_b",
4345         "avb_avtp_capture_b",
4346 };
4347
4348 static const char * const can0_groups[] = {
4349         "can0_data_a",
4350         "can0_data_b",
4351 };
4352
4353 static const char * const can1_groups[] = {
4354         "can1_data",
4355 };
4356
4357 static const char * const can_clk_groups[] = {
4358         "can_clk",
4359 };
4360
4361 static const char * const canfd0_groups[] = {
4362         "canfd0_data_a",
4363         "canfd0_data_b",
4364 };
4365
4366 static const char * const canfd1_groups[] = {
4367         "canfd1_data",
4368 };
4369
4370 static const char * const du_groups[] = {
4371         "du_rgb666",
4372         "du_rgb888",
4373         "du_clk_out_0",
4374         "du_clk_out_1",
4375         "du_sync",
4376         "du_oddf",
4377         "du_cde",
4378         "du_disp",
4379 };
4380
4381 static const char * const hscif0_groups[] = {
4382         "hscif0_data",
4383         "hscif0_clk",
4384         "hscif0_ctrl",
4385 };
4386
4387 static const char * const hscif1_groups[] = {
4388         "hscif1_data_a",
4389         "hscif1_clk_a",
4390         "hscif1_ctrl_a",
4391         "hscif1_data_b",
4392         "hscif1_clk_b",
4393         "hscif1_ctrl_b",
4394 };
4395
4396 static const char * const hscif2_groups[] = {
4397         "hscif2_data_a",
4398         "hscif2_clk_a",
4399         "hscif2_ctrl_a",
4400         "hscif2_data_b",
4401         "hscif2_clk_b",
4402         "hscif2_ctrl_b",
4403         "hscif2_data_c",
4404         "hscif2_clk_c",
4405         "hscif2_ctrl_c",
4406 };
4407
4408 static const char * const hscif3_groups[] = {
4409         "hscif3_data_a",
4410         "hscif3_clk",
4411         "hscif3_ctrl",
4412         "hscif3_data_b",
4413         "hscif3_data_c",
4414         "hscif3_data_d",
4415 };
4416
4417 static const char * const hscif4_groups[] = {
4418         "hscif4_data_a",
4419         "hscif4_clk",
4420         "hscif4_ctrl",
4421         "hscif4_data_b",
4422 };
4423
4424 static const char * const i2c1_groups[] = {
4425         "i2c1_a",
4426         "i2c1_b",
4427 };
4428
4429 static const char * const i2c2_groups[] = {
4430         "i2c2_a",
4431         "i2c2_b",
4432 };
4433
4434 static const char * const i2c6_groups[] = {
4435         "i2c6_a",
4436         "i2c6_b",
4437         "i2c6_c",
4438 };
4439
4440 static const char * const intc_ex_groups[] = {
4441         "intc_ex_irq0",
4442         "intc_ex_irq1",
4443         "intc_ex_irq2",
4444         "intc_ex_irq3",
4445         "intc_ex_irq4",
4446         "intc_ex_irq5",
4447 };
4448
4449 static const char * const msiof0_groups[] = {
4450         "msiof0_clk",
4451         "msiof0_sync",
4452         "msiof0_ss1",
4453         "msiof0_ss2",
4454         "msiof0_txd",
4455         "msiof0_rxd",
4456 };
4457
4458 static const char * const msiof1_groups[] = {
4459         "msiof1_clk_a",
4460         "msiof1_sync_a",
4461         "msiof1_ss1_a",
4462         "msiof1_ss2_a",
4463         "msiof1_txd_a",
4464         "msiof1_rxd_a",
4465         "msiof1_clk_b",
4466         "msiof1_sync_b",
4467         "msiof1_ss1_b",
4468         "msiof1_ss2_b",
4469         "msiof1_txd_b",
4470         "msiof1_rxd_b",
4471         "msiof1_clk_c",
4472         "msiof1_sync_c",
4473         "msiof1_ss1_c",
4474         "msiof1_ss2_c",
4475         "msiof1_txd_c",
4476         "msiof1_rxd_c",
4477         "msiof1_clk_d",
4478         "msiof1_sync_d",
4479         "msiof1_ss1_d",
4480         "msiof1_ss2_d",
4481         "msiof1_txd_d",
4482         "msiof1_rxd_d",
4483         "msiof1_clk_e",
4484         "msiof1_sync_e",
4485         "msiof1_ss1_e",
4486         "msiof1_ss2_e",
4487         "msiof1_txd_e",
4488         "msiof1_rxd_e",
4489         "msiof1_clk_f",
4490         "msiof1_sync_f",
4491         "msiof1_ss1_f",
4492         "msiof1_ss2_f",
4493         "msiof1_txd_f",
4494         "msiof1_rxd_f",
4495         "msiof1_clk_g",
4496         "msiof1_sync_g",
4497         "msiof1_ss1_g",
4498         "msiof1_ss2_g",
4499         "msiof1_txd_g",
4500         "msiof1_rxd_g",
4501 };
4502
4503 static const char * const msiof2_groups[] = {
4504         "msiof2_clk_a",
4505         "msiof2_sync_a",
4506         "msiof2_ss1_a",
4507         "msiof2_ss2_a",
4508         "msiof2_txd_a",
4509         "msiof2_rxd_a",
4510         "msiof2_clk_b",
4511         "msiof2_sync_b",
4512         "msiof2_ss1_b",
4513         "msiof2_ss2_b",
4514         "msiof2_txd_b",
4515         "msiof2_rxd_b",
4516         "msiof2_clk_c",
4517         "msiof2_sync_c",
4518         "msiof2_ss1_c",
4519         "msiof2_ss2_c",
4520         "msiof2_txd_c",
4521         "msiof2_rxd_c",
4522         "msiof2_clk_d",
4523         "msiof2_sync_d",
4524         "msiof2_ss1_d",
4525         "msiof2_ss2_d",
4526         "msiof2_txd_d",
4527         "msiof2_rxd_d",
4528 };
4529
4530 static const char * const msiof3_groups[] = {
4531         "msiof3_clk_a",
4532         "msiof3_sync_a",
4533         "msiof3_ss1_a",
4534         "msiof3_ss2_a",
4535         "msiof3_txd_a",
4536         "msiof3_rxd_a",
4537         "msiof3_clk_b",
4538         "msiof3_sync_b",
4539         "msiof3_ss1_b",
4540         "msiof3_ss2_b",
4541         "msiof3_txd_b",
4542         "msiof3_rxd_b",
4543         "msiof3_clk_c",
4544         "msiof3_sync_c",
4545         "msiof3_txd_c",
4546         "msiof3_rxd_c",
4547         "msiof3_clk_d",
4548         "msiof3_sync_d",
4549         "msiof3_ss1_d",
4550         "msiof3_txd_d",
4551         "msiof3_rxd_d",
4552         "msiof3_clk_e",
4553         "msiof3_sync_e",
4554         "msiof3_ss1_e",
4555         "msiof3_ss2_e",
4556         "msiof3_txd_e",
4557         "msiof3_rxd_e",
4558 };
4559
4560 static const char * const pwm0_groups[] = {
4561         "pwm0",
4562 };
4563
4564 static const char * const pwm1_groups[] = {
4565         "pwm1_a",
4566         "pwm1_b",
4567 };
4568
4569 static const char * const pwm2_groups[] = {
4570         "pwm2_a",
4571         "pwm2_b",
4572 };
4573
4574 static const char * const pwm3_groups[] = {
4575         "pwm3_a",
4576         "pwm3_b",
4577 };
4578
4579 static const char * const pwm4_groups[] = {
4580         "pwm4_a",
4581         "pwm4_b",
4582 };
4583
4584 static const char * const pwm5_groups[] = {
4585         "pwm5_a",
4586         "pwm5_b",
4587 };
4588
4589 static const char * const pwm6_groups[] = {
4590         "pwm6_a",
4591         "pwm6_b",
4592 };
4593
4594 static const char * const sata0_groups[] = {
4595         "sata0_devslp_a",
4596         "sata0_devslp_b",
4597 };
4598
4599 static const char * const scif0_groups[] = {
4600         "scif0_data",
4601         "scif0_clk",
4602         "scif0_ctrl",
4603 };
4604
4605 static const char * const scif1_groups[] = {
4606         "scif1_data_a",
4607         "scif1_clk",
4608         "scif1_ctrl",
4609         "scif1_data_b",
4610 };
4611 static const char * const scif2_groups[] = {
4612         "scif2_data_a",
4613         "scif2_clk",
4614         "scif2_data_b",
4615 };
4616
4617 static const char * const scif3_groups[] = {
4618         "scif3_data_a",
4619         "scif3_clk",
4620         "scif3_ctrl",
4621         "scif3_data_b",
4622 };
4623
4624 static const char * const scif4_groups[] = {
4625         "scif4_data_a",
4626         "scif4_clk_a",
4627         "scif4_ctrl_a",
4628         "scif4_data_b",
4629         "scif4_clk_b",
4630         "scif4_ctrl_b",
4631         "scif4_data_c",
4632         "scif4_clk_c",
4633         "scif4_ctrl_c",
4634 };
4635
4636 static const char * const scif5_groups[] = {
4637         "scif5_data_a",
4638         "scif5_clk_a",
4639         "scif5_data_b",
4640         "scif5_clk_b",
4641 };
4642
4643 static const char * const scif_clk_groups[] = {
4644         "scif_clk_a",
4645         "scif_clk_b",
4646 };
4647
4648 static const char * const sdhi0_groups[] = {
4649         "sdhi0_data1",
4650         "sdhi0_data4",
4651         "sdhi0_ctrl",
4652         "sdhi0_cd",
4653         "sdhi0_wp",
4654 };
4655
4656 static const char * const sdhi1_groups[] = {
4657         "sdhi1_data1",
4658         "sdhi1_data4",
4659         "sdhi1_ctrl",
4660         "sdhi1_cd",
4661         "sdhi1_wp",
4662 };
4663
4664 static const char * const sdhi2_groups[] = {
4665         "sdhi2_data1",
4666         "sdhi2_data4",
4667         "sdhi2_data8",
4668         "sdhi2_ctrl",
4669         "sdhi2_cd_a",
4670         "sdhi2_wp_a",
4671         "sdhi2_cd_b",
4672         "sdhi2_wp_b",
4673         "sdhi2_ds",
4674 };
4675
4676 static const char * const sdhi3_groups[] = {
4677         "sdhi3_data1",
4678         "sdhi3_data4",
4679         "sdhi3_data8",
4680         "sdhi3_ctrl",
4681         "sdhi3_cd",
4682         "sdhi3_wp",
4683         "sdhi3_ds",
4684 };
4685
4686 static const char * const ssi_groups[] = {
4687         "ssi0_data",
4688         "ssi01239_ctrl",
4689         "ssi1_data_a",
4690         "ssi1_data_b",
4691         "ssi1_ctrl_a",
4692         "ssi1_ctrl_b",
4693         "ssi2_data_a",
4694         "ssi2_data_b",
4695         "ssi2_ctrl_a",
4696         "ssi2_ctrl_b",
4697         "ssi3_data",
4698         "ssi349_ctrl",
4699         "ssi4_data",
4700         "ssi4_ctrl",
4701         "ssi5_data",
4702         "ssi5_ctrl",
4703         "ssi6_data",
4704         "ssi6_ctrl",
4705         "ssi7_data",
4706         "ssi78_ctrl",
4707         "ssi8_data",
4708         "ssi9_data_a",
4709         "ssi9_data_b",
4710         "ssi9_ctrl_a",
4711         "ssi9_ctrl_b",
4712 };
4713
4714 static const char * const usb0_groups[] = {
4715         "usb0",
4716 };
4717
4718 static const char * const usb1_groups[] = {
4719         "usb1",
4720 };
4721
4722 static const char * const usb30_groups[] = {
4723         "usb30",
4724 };
4725
4726 static const char * const vin4_groups[] = {
4727         "vin4_data8_a",
4728         "vin4_data10_a",
4729         "vin4_data12_a",
4730         "vin4_data16_a",
4731         "vin4_data18_a",
4732         "vin4_data20_a",
4733         "vin4_data24_a",
4734         "vin4_data8_b",
4735         "vin4_data10_b",
4736         "vin4_data12_b",
4737         "vin4_data16_b",
4738         "vin4_data18_b",
4739         "vin4_data20_b",
4740         "vin4_data24_b",
4741         "vin4_sync",
4742         "vin4_field",
4743         "vin4_clkenb",
4744         "vin4_clk",
4745 };
4746
4747 static const char * const vin5_groups[] = {
4748         "vin5_data8",
4749         "vin5_data10",
4750         "vin5_data12",
4751         "vin5_data16",
4752         "vin5_sync",
4753         "vin5_field",
4754         "vin5_clkenb",
4755         "vin5_clk",
4756 };
4757
4758 static const struct sh_pfc_function pinmux_functions[] = {
4759         SH_PFC_FUNCTION(audio_clk),
4760         SH_PFC_FUNCTION(avb),
4761         SH_PFC_FUNCTION(can0),
4762         SH_PFC_FUNCTION(can1),
4763         SH_PFC_FUNCTION(can_clk),
4764         SH_PFC_FUNCTION(canfd0),
4765         SH_PFC_FUNCTION(canfd1),
4766         SH_PFC_FUNCTION(du),
4767         SH_PFC_FUNCTION(hscif0),
4768         SH_PFC_FUNCTION(hscif1),
4769         SH_PFC_FUNCTION(hscif2),
4770         SH_PFC_FUNCTION(hscif3),
4771         SH_PFC_FUNCTION(hscif4),
4772         SH_PFC_FUNCTION(i2c1),
4773         SH_PFC_FUNCTION(i2c2),
4774         SH_PFC_FUNCTION(i2c6),
4775         SH_PFC_FUNCTION(intc_ex),
4776         SH_PFC_FUNCTION(msiof0),
4777         SH_PFC_FUNCTION(msiof1),
4778         SH_PFC_FUNCTION(msiof2),
4779         SH_PFC_FUNCTION(msiof3),
4780         SH_PFC_FUNCTION(pwm0),
4781         SH_PFC_FUNCTION(pwm1),
4782         SH_PFC_FUNCTION(pwm2),
4783         SH_PFC_FUNCTION(pwm3),
4784         SH_PFC_FUNCTION(pwm4),
4785         SH_PFC_FUNCTION(pwm5),
4786         SH_PFC_FUNCTION(pwm6),
4787         SH_PFC_FUNCTION(sata0),
4788         SH_PFC_FUNCTION(scif0),
4789         SH_PFC_FUNCTION(scif1),
4790         SH_PFC_FUNCTION(scif2),
4791         SH_PFC_FUNCTION(scif3),
4792         SH_PFC_FUNCTION(scif4),
4793         SH_PFC_FUNCTION(scif5),
4794         SH_PFC_FUNCTION(scif_clk),
4795         SH_PFC_FUNCTION(sdhi0),
4796         SH_PFC_FUNCTION(sdhi1),
4797         SH_PFC_FUNCTION(sdhi2),
4798         SH_PFC_FUNCTION(sdhi3),
4799         SH_PFC_FUNCTION(ssi),
4800         SH_PFC_FUNCTION(usb0),
4801         SH_PFC_FUNCTION(usb1),
4802         SH_PFC_FUNCTION(usb30),
4803         SH_PFC_FUNCTION(vin4),
4804         SH_PFC_FUNCTION(vin5),
4805 };
4806
4807 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4808 #define F_(x, y)        FN_##y
4809 #define FM(x)           FN_##x
4810         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4811                 0, 0,
4812                 0, 0,
4813                 0, 0,
4814                 0, 0,
4815                 0, 0,
4816                 0, 0,
4817                 0, 0,
4818                 0, 0,
4819                 0, 0,
4820                 0, 0,
4821                 0, 0,
4822                 0, 0,
4823                 0, 0,
4824                 0, 0,
4825                 0, 0,
4826                 0, 0,
4827                 GP_0_15_FN,     GPSR0_15,
4828                 GP_0_14_FN,     GPSR0_14,
4829                 GP_0_13_FN,     GPSR0_13,
4830                 GP_0_12_FN,     GPSR0_12,
4831                 GP_0_11_FN,     GPSR0_11,
4832                 GP_0_10_FN,     GPSR0_10,
4833                 GP_0_9_FN,      GPSR0_9,
4834                 GP_0_8_FN,      GPSR0_8,
4835                 GP_0_7_FN,      GPSR0_7,
4836                 GP_0_6_FN,      GPSR0_6,
4837                 GP_0_5_FN,      GPSR0_5,
4838                 GP_0_4_FN,      GPSR0_4,
4839                 GP_0_3_FN,      GPSR0_3,
4840                 GP_0_2_FN,      GPSR0_2,
4841                 GP_0_1_FN,      GPSR0_1,
4842                 GP_0_0_FN,      GPSR0_0, }
4843         },
4844         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4845                 0, 0,
4846                 0, 0,
4847                 0, 0,
4848                 GP_1_28_FN,     GPSR1_28,
4849                 GP_1_27_FN,     GPSR1_27,
4850                 GP_1_26_FN,     GPSR1_26,
4851                 GP_1_25_FN,     GPSR1_25,
4852                 GP_1_24_FN,     GPSR1_24,
4853                 GP_1_23_FN,     GPSR1_23,
4854                 GP_1_22_FN,     GPSR1_22,
4855                 GP_1_21_FN,     GPSR1_21,
4856                 GP_1_20_FN,     GPSR1_20,
4857                 GP_1_19_FN,     GPSR1_19,
4858                 GP_1_18_FN,     GPSR1_18,
4859                 GP_1_17_FN,     GPSR1_17,
4860                 GP_1_16_FN,     GPSR1_16,
4861                 GP_1_15_FN,     GPSR1_15,
4862                 GP_1_14_FN,     GPSR1_14,
4863                 GP_1_13_FN,     GPSR1_13,
4864                 GP_1_12_FN,     GPSR1_12,
4865                 GP_1_11_FN,     GPSR1_11,
4866                 GP_1_10_FN,     GPSR1_10,
4867                 GP_1_9_FN,      GPSR1_9,
4868                 GP_1_8_FN,      GPSR1_8,
4869                 GP_1_7_FN,      GPSR1_7,
4870                 GP_1_6_FN,      GPSR1_6,
4871                 GP_1_5_FN,      GPSR1_5,
4872                 GP_1_4_FN,      GPSR1_4,
4873                 GP_1_3_FN,      GPSR1_3,
4874                 GP_1_2_FN,      GPSR1_2,
4875                 GP_1_1_FN,      GPSR1_1,
4876                 GP_1_0_FN,      GPSR1_0, }
4877         },
4878         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4879                 0, 0,
4880                 0, 0,
4881                 0, 0,
4882                 0, 0,
4883                 0, 0,
4884                 0, 0,
4885                 0, 0,
4886                 0, 0,
4887                 0, 0,
4888                 0, 0,
4889                 0, 0,
4890                 0, 0,
4891                 0, 0,
4892                 0, 0,
4893                 0, 0,
4894                 0, 0,
4895                 0, 0,
4896                 GP_2_14_FN,     GPSR2_14,
4897                 GP_2_13_FN,     GPSR2_13,
4898                 GP_2_12_FN,     GPSR2_12,
4899                 GP_2_11_FN,     GPSR2_11,
4900                 GP_2_10_FN,     GPSR2_10,
4901                 GP_2_9_FN,      GPSR2_9,
4902                 GP_2_8_FN,      GPSR2_8,
4903                 GP_2_7_FN,      GPSR2_7,
4904                 GP_2_6_FN,      GPSR2_6,
4905                 GP_2_5_FN,      GPSR2_5,
4906                 GP_2_4_FN,      GPSR2_4,
4907                 GP_2_3_FN,      GPSR2_3,
4908                 GP_2_2_FN,      GPSR2_2,
4909                 GP_2_1_FN,      GPSR2_1,
4910                 GP_2_0_FN,      GPSR2_0, }
4911         },
4912         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4913                 0, 0,
4914                 0, 0,
4915                 0, 0,
4916                 0, 0,
4917                 0, 0,
4918                 0, 0,
4919                 0, 0,
4920                 0, 0,
4921                 0, 0,
4922                 0, 0,
4923                 0, 0,
4924                 0, 0,
4925                 0, 0,
4926                 0, 0,
4927                 0, 0,
4928                 0, 0,
4929                 GP_3_15_FN,     GPSR3_15,
4930                 GP_3_14_FN,     GPSR3_14,
4931                 GP_3_13_FN,     GPSR3_13,
4932                 GP_3_12_FN,     GPSR3_12,
4933                 GP_3_11_FN,     GPSR3_11,
4934                 GP_3_10_FN,     GPSR3_10,
4935                 GP_3_9_FN,      GPSR3_9,
4936                 GP_3_8_FN,      GPSR3_8,
4937                 GP_3_7_FN,      GPSR3_7,
4938                 GP_3_6_FN,      GPSR3_6,
4939                 GP_3_5_FN,      GPSR3_5,
4940                 GP_3_4_FN,      GPSR3_4,
4941                 GP_3_3_FN,      GPSR3_3,
4942                 GP_3_2_FN,      GPSR3_2,
4943                 GP_3_1_FN,      GPSR3_1,
4944                 GP_3_0_FN,      GPSR3_0, }
4945         },
4946         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4947                 0, 0,
4948                 0, 0,
4949                 0, 0,
4950                 0, 0,
4951                 0, 0,
4952                 0, 0,
4953                 0, 0,
4954                 0, 0,
4955                 0, 0,
4956                 0, 0,
4957                 0, 0,
4958                 0, 0,
4959                 0, 0,
4960                 0, 0,
4961                 GP_4_17_FN,     GPSR4_17,
4962                 GP_4_16_FN,     GPSR4_16,
4963                 GP_4_15_FN,     GPSR4_15,
4964                 GP_4_14_FN,     GPSR4_14,
4965                 GP_4_13_FN,     GPSR4_13,
4966                 GP_4_12_FN,     GPSR4_12,
4967                 GP_4_11_FN,     GPSR4_11,
4968                 GP_4_10_FN,     GPSR4_10,
4969                 GP_4_9_FN,      GPSR4_9,
4970                 GP_4_8_FN,      GPSR4_8,
4971                 GP_4_7_FN,      GPSR4_7,
4972                 GP_4_6_FN,      GPSR4_6,
4973                 GP_4_5_FN,      GPSR4_5,
4974                 GP_4_4_FN,      GPSR4_4,
4975                 GP_4_3_FN,      GPSR4_3,
4976                 GP_4_2_FN,      GPSR4_2,
4977                 GP_4_1_FN,      GPSR4_1,
4978                 GP_4_0_FN,      GPSR4_0, }
4979         },
4980         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4981                 0, 0,
4982                 0, 0,
4983                 0, 0,
4984                 0, 0,
4985                 0, 0,
4986                 0, 0,
4987                 GP_5_25_FN,     GPSR5_25,
4988                 GP_5_24_FN,     GPSR5_24,
4989                 GP_5_23_FN,     GPSR5_23,
4990                 GP_5_22_FN,     GPSR5_22,
4991                 GP_5_21_FN,     GPSR5_21,
4992                 GP_5_20_FN,     GPSR5_20,
4993                 GP_5_19_FN,     GPSR5_19,
4994                 GP_5_18_FN,     GPSR5_18,
4995                 GP_5_17_FN,     GPSR5_17,
4996                 GP_5_16_FN,     GPSR5_16,
4997                 GP_5_15_FN,     GPSR5_15,
4998                 GP_5_14_FN,     GPSR5_14,
4999                 GP_5_13_FN,     GPSR5_13,
5000                 GP_5_12_FN,     GPSR5_12,
5001                 GP_5_11_FN,     GPSR5_11,
5002                 GP_5_10_FN,     GPSR5_10,
5003                 GP_5_9_FN,      GPSR5_9,
5004                 GP_5_8_FN,      GPSR5_8,
5005                 GP_5_7_FN,      GPSR5_7,
5006                 GP_5_6_FN,      GPSR5_6,
5007                 GP_5_5_FN,      GPSR5_5,
5008                 GP_5_4_FN,      GPSR5_4,
5009                 GP_5_3_FN,      GPSR5_3,
5010                 GP_5_2_FN,      GPSR5_2,
5011                 GP_5_1_FN,      GPSR5_1,
5012                 GP_5_0_FN,      GPSR5_0, }
5013         },
5014         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5015                 GP_6_31_FN,     GPSR6_31,
5016                 GP_6_30_FN,     GPSR6_30,
5017                 GP_6_29_FN,     GPSR6_29,
5018                 GP_6_28_FN,     GPSR6_28,
5019                 GP_6_27_FN,     GPSR6_27,
5020                 GP_6_26_FN,     GPSR6_26,
5021                 GP_6_25_FN,     GPSR6_25,
5022                 GP_6_24_FN,     GPSR6_24,
5023                 GP_6_23_FN,     GPSR6_23,
5024                 GP_6_22_FN,     GPSR6_22,
5025                 GP_6_21_FN,     GPSR6_21,
5026                 GP_6_20_FN,     GPSR6_20,
5027                 GP_6_19_FN,     GPSR6_19,
5028                 GP_6_18_FN,     GPSR6_18,
5029                 GP_6_17_FN,     GPSR6_17,
5030                 GP_6_16_FN,     GPSR6_16,
5031                 GP_6_15_FN,     GPSR6_15,
5032                 GP_6_14_FN,     GPSR6_14,
5033                 GP_6_13_FN,     GPSR6_13,
5034                 GP_6_12_FN,     GPSR6_12,
5035                 GP_6_11_FN,     GPSR6_11,
5036                 GP_6_10_FN,     GPSR6_10,
5037                 GP_6_9_FN,      GPSR6_9,
5038                 GP_6_8_FN,      GPSR6_8,
5039                 GP_6_7_FN,      GPSR6_7,
5040                 GP_6_6_FN,      GPSR6_6,
5041                 GP_6_5_FN,      GPSR6_5,
5042                 GP_6_4_FN,      GPSR6_4,
5043                 GP_6_3_FN,      GPSR6_3,
5044                 GP_6_2_FN,      GPSR6_2,
5045                 GP_6_1_FN,      GPSR6_1,
5046                 GP_6_0_FN,      GPSR6_0, }
5047         },
5048         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5049                 0, 0,
5050                 0, 0,
5051                 0, 0,
5052                 0, 0,
5053                 0, 0,
5054                 0, 0,
5055                 0, 0,
5056                 0, 0,
5057                 0, 0,
5058                 0, 0,
5059                 0, 0,
5060                 0, 0,
5061                 0, 0,
5062                 0, 0,
5063                 0, 0,
5064                 0, 0,
5065                 0, 0,
5066                 0, 0,
5067                 0, 0,
5068                 0, 0,
5069                 0, 0,
5070                 0, 0,
5071                 0, 0,
5072                 0, 0,
5073                 0, 0,
5074                 0, 0,
5075                 0, 0,
5076                 0, 0,
5077                 GP_7_3_FN, GPSR7_3,
5078                 GP_7_2_FN, GPSR7_2,
5079                 GP_7_1_FN, GPSR7_1,
5080                 GP_7_0_FN, GPSR7_0, }
5081         },
5082 #undef F_
5083 #undef FM
5084
5085 #define F_(x, y)        x,
5086 #define FM(x)           FN_##x,
5087         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5088                 IP0_31_28
5089                 IP0_27_24
5090                 IP0_23_20
5091                 IP0_19_16
5092                 IP0_15_12
5093                 IP0_11_8
5094                 IP0_7_4
5095                 IP0_3_0 }
5096         },
5097         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5098                 IP1_31_28
5099                 IP1_27_24
5100                 IP1_23_20
5101                 IP1_19_16
5102                 IP1_15_12
5103                 IP1_11_8
5104                 IP1_7_4
5105                 IP1_3_0 }
5106         },
5107         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5108                 IP2_31_28
5109                 IP2_27_24
5110                 IP2_23_20
5111                 IP2_19_16
5112                 IP2_15_12
5113                 IP2_11_8
5114                 IP2_7_4
5115                 IP2_3_0 }
5116         },
5117         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5118                 IP3_31_28
5119                 IP3_27_24
5120                 IP3_23_20
5121                 IP3_19_16
5122                 IP3_15_12
5123                 IP3_11_8
5124                 IP3_7_4
5125                 IP3_3_0 }
5126         },
5127         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5128                 IP4_31_28
5129                 IP4_27_24
5130                 IP4_23_20
5131                 IP4_19_16
5132                 IP4_15_12
5133                 IP4_11_8
5134                 IP4_7_4
5135                 IP4_3_0 }
5136         },
5137         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5138                 IP5_31_28
5139                 IP5_27_24
5140                 IP5_23_20
5141                 IP5_19_16
5142                 IP5_15_12
5143                 IP5_11_8
5144                 IP5_7_4
5145                 IP5_3_0 }
5146         },
5147         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5148                 IP6_31_28
5149                 IP6_27_24
5150                 IP6_23_20
5151                 IP6_19_16
5152                 IP6_15_12
5153                 IP6_11_8
5154                 IP6_7_4
5155                 IP6_3_0 }
5156         },
5157         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5158                 IP7_31_28
5159                 IP7_27_24
5160                 IP7_23_20
5161                 IP7_19_16
5162                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5163                 IP7_11_8
5164                 IP7_7_4
5165                 IP7_3_0 }
5166         },
5167         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5168                 IP8_31_28
5169                 IP8_27_24
5170                 IP8_23_20
5171                 IP8_19_16
5172                 IP8_15_12
5173                 IP8_11_8
5174                 IP8_7_4
5175                 IP8_3_0 }
5176         },
5177         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5178                 IP9_31_28
5179                 IP9_27_24
5180                 IP9_23_20
5181                 IP9_19_16
5182                 IP9_15_12
5183                 IP9_11_8
5184                 IP9_7_4
5185                 IP9_3_0 }
5186         },
5187         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5188                 IP10_31_28
5189                 IP10_27_24
5190                 IP10_23_20
5191                 IP10_19_16
5192                 IP10_15_12
5193                 IP10_11_8
5194                 IP10_7_4
5195                 IP10_3_0 }
5196         },
5197         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5198                 IP11_31_28
5199                 IP11_27_24
5200                 IP11_23_20
5201                 IP11_19_16
5202                 IP11_15_12
5203                 IP11_11_8
5204                 IP11_7_4
5205                 IP11_3_0 }
5206         },
5207         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5208                 IP12_31_28
5209                 IP12_27_24
5210                 IP12_23_20
5211                 IP12_19_16
5212                 IP12_15_12
5213                 IP12_11_8
5214                 IP12_7_4
5215                 IP12_3_0 }
5216         },
5217         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5218                 IP13_31_28
5219                 IP13_27_24
5220                 IP13_23_20
5221                 IP13_19_16
5222                 IP13_15_12
5223                 IP13_11_8
5224                 IP13_7_4
5225                 IP13_3_0 }
5226         },
5227         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5228                 IP14_31_28
5229                 IP14_27_24
5230                 IP14_23_20
5231                 IP14_19_16
5232                 IP14_15_12
5233                 IP14_11_8
5234                 IP14_7_4
5235                 IP14_3_0 }
5236         },
5237         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5238                 IP15_31_28
5239                 IP15_27_24
5240                 IP15_23_20
5241                 IP15_19_16
5242                 IP15_15_12
5243                 IP15_11_8
5244                 IP15_7_4
5245                 IP15_3_0 }
5246         },
5247         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5248                 IP16_31_28
5249                 IP16_27_24
5250                 IP16_23_20
5251                 IP16_19_16
5252                 IP16_15_12
5253                 IP16_11_8
5254                 IP16_7_4
5255                 IP16_3_0 }
5256         },
5257         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5258                 IP17_31_28
5259                 IP17_27_24
5260                 IP17_23_20
5261                 IP17_19_16
5262                 IP17_15_12
5263                 IP17_11_8
5264                 IP17_7_4
5265                 IP17_3_0 }
5266         },
5267         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5268                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5269                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5270                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5271                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5272                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5273                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5274                 IP18_7_4
5275                 IP18_3_0 }
5276         },
5277 #undef F_
5278 #undef FM
5279
5280 #define F_(x, y)        x,
5281 #define FM(x)           FN_##x,
5282         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5283                              3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5284                              1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5285                 MOD_SEL0_31_30_29
5286                 MOD_SEL0_28_27
5287                 MOD_SEL0_26_25_24
5288                 MOD_SEL0_23
5289                 MOD_SEL0_22
5290                 MOD_SEL0_21
5291                 MOD_SEL0_20
5292                 MOD_SEL0_19
5293                 MOD_SEL0_18_17
5294                 MOD_SEL0_16
5295                 0, 0, /* RESERVED 15 */
5296                 MOD_SEL0_14_13
5297                 MOD_SEL0_12
5298                 MOD_SEL0_11
5299                 MOD_SEL0_10
5300                 MOD_SEL0_9_8
5301                 MOD_SEL0_7_6
5302                 MOD_SEL0_5
5303                 MOD_SEL0_4_3
5304                 /* RESERVED 2, 1, 0 */
5305                 0, 0, 0, 0, 0, 0, 0, 0 }
5306         },
5307         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5308                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5309                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5310                 MOD_SEL1_31_30
5311                 MOD_SEL1_29_28_27
5312                 MOD_SEL1_26
5313                 MOD_SEL1_25_24
5314                 MOD_SEL1_23_22_21
5315                 MOD_SEL1_20
5316                 MOD_SEL1_19
5317                 MOD_SEL1_18_17
5318                 MOD_SEL1_16
5319                 MOD_SEL1_15_14
5320                 MOD_SEL1_13
5321                 MOD_SEL1_12
5322                 MOD_SEL1_11
5323                 MOD_SEL1_10
5324                 MOD_SEL1_9
5325                 0, 0, 0, 0, /* RESERVED 8, 7 */
5326                 MOD_SEL1_6
5327                 MOD_SEL1_5
5328                 MOD_SEL1_4
5329                 MOD_SEL1_3
5330                 MOD_SEL1_2
5331                 MOD_SEL1_1
5332                 MOD_SEL1_0 }
5333         },
5334         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5335                              1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5336                              4, 4, 4, 3, 1) {
5337                 MOD_SEL2_31
5338                 MOD_SEL2_30
5339                 MOD_SEL2_29
5340                 MOD_SEL2_28_27
5341                 MOD_SEL2_26
5342                 MOD_SEL2_25_24_23
5343                 MOD_SEL2_22
5344                 MOD_SEL2_21
5345                 MOD_SEL2_20
5346                 MOD_SEL2_19
5347                 MOD_SEL2_18
5348                 MOD_SEL2_17
5349                 /* RESERVED 16 */
5350                 0, 0,
5351                 /* RESERVED 15, 14, 13, 12 */
5352                 0, 0, 0, 0, 0, 0, 0, 0,
5353                 0, 0, 0, 0, 0, 0, 0, 0,
5354                 /* RESERVED 11, 10, 9, 8 */
5355                 0, 0, 0, 0, 0, 0, 0, 0,
5356                 0, 0, 0, 0, 0, 0, 0, 0,
5357                 /* RESERVED 7, 6, 5, 4 */
5358                 0, 0, 0, 0, 0, 0, 0, 0,
5359                 0, 0, 0, 0, 0, 0, 0, 0,
5360                 /* RESERVED 3, 2, 1 */
5361                 0, 0, 0, 0, 0, 0, 0, 0,
5362                 MOD_SEL2_0 }
5363         },
5364         { },
5365 };
5366
5367 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5368         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5369                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5370                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5371                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5372                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5373                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5374                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5375                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5376                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5377         } },
5378         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5379                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5380                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5381                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5382                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5383                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5384                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5385                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5386                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5387         } },
5388         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5389                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5390                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5391                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5392                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5393                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5394                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5395                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5396                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5397         } },
5398         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5399                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5400                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5401                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5402                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5403                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5404                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5405                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5406                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5407         } },
5408         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5409                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5410                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5411                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5412                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5413                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5414                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5415                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5416                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5417         } },
5418         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5419                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5420                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5421                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5422                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5423                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5424                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5425                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5426                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5427         } },
5428         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5429                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5430                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5431                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5432                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5433                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5434                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5435                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5436                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5437         } },
5438         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5439                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5440                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5441                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5442                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5443                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5444                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5445                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5446                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5447         } },
5448         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5449                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5450                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5451                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5452                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5453                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5454                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5455                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5456                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5457         } },
5458         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5459                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5460                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5461                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5462                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5463                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5464                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5465                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5466                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5467         } },
5468         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5469                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5470                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5471                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5472                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5473                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5474                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5475                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5476                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5477         } },
5478         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5479                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5480                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5481                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5482                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5483                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5484                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5485                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5486                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5487         } },
5488         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5489                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN3 */
5490                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5491                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5492         } },
5493         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5494                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5495                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5496                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5497                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5498                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5499                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5500                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5501                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5502         } },
5503         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5504                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5505                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5506                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5507                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5508                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5509                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5510                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5511                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5512         } },
5513         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5514                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5515                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5516                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5517                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5518                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5519                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5520                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5521                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5522         } },
5523         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5524                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5525                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5526                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5527                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5528                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5529                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5530                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5531                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5532         } },
5533         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5534                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5535                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5536                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5537                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5538                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5539                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5540                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5541                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5542         } },
5543         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5544                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5545                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5546                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5547                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5548                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5549                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5550                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5551                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5552         } },
5553         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5554                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5555                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5556                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5557                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5558                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5559                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5560                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5561                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5562         } },
5563         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5564                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5565                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5566                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5567                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5568                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5569                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5570                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5571                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5572         } },
5573         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5574                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5575                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5576                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5577                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5578                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5579                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5580                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5581                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5582         } },
5583         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5584                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5585                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5586                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5587                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5588                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5589                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5590                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5591                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5592         } },
5593         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5594                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5595                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5596                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5597                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5598                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5599                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5600                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5601                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5602         } },
5603         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5604                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5605                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5606                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5607                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5608                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5609                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5610                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5611         } },
5612         { },
5613 };
5614
5615 enum ioctrl_regs {
5616         POCCTRL,
5617 };
5618
5619 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5620         [POCCTRL] = { 0xe6060380, },
5621         { /* sentinel */ },
5622 };
5623
5624 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5625 {
5626         int bit = -EINVAL;
5627
5628         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5629
5630         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5631                 bit = pin & 0x1f;
5632
5633         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5634                 bit = (pin & 0x1f) + 12;
5635
5636         return bit;
5637 }
5638
5639 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5640         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5641                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5642                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5643                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5644                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5645                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5646                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5647                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5648                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5649                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5650                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5651                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5652                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5653                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5654                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5655                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5656                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5657                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5658                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5659                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5660                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5661                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5662                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5663                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5664                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5665                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5666                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5667                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5668                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5669                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5670                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5671                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5672                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5673         } },
5674         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5675                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5676                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5677                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5678                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5679                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5680                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5681                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5682                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5683                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5684                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5685                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5686                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5687                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5688                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5689                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5690                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5691                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5692                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5693                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5694                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5695                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5696                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5697                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5698                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5699                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5700                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5701                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5702                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5703                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5704                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5705                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5706                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5707         } },
5708         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5709                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5710                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5711                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5712                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5713                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5714                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5715                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5716                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5717                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5718                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5719                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5720                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5721                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5722                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5723                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5724                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5725                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5726                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5727                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5728                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5729                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5730                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5731                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5732                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5733                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5734                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5735                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5736                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5737                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
5738                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
5739                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5740                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5741         } },
5742         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5743                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN2 */
5744                 [ 1] = PIN_NONE,
5745                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
5746                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5747                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5748                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5749                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5750                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5751                 [ 8] = PIN_NONE,
5752                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5753                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5754                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5755                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5756                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5757                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5758                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5759                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5760                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5761                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5762                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5763                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5764                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5765                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5766                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5767                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5768                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5769                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5770                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5771                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5772                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5773                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5774                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5775         } },
5776         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5777                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5778                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5779                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5780                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5781                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5782                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5783                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5784                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5785                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5786                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5787                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5788                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5789                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
5790                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
5791                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
5792                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
5793                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
5794                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
5795                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
5796                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
5797                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
5798                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
5799                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
5800                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
5801                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
5802                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
5803                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
5804                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
5805                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
5806                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
5807                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
5808                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
5809         } },
5810         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5811                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
5812                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
5813                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
5814                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
5815                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
5816                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
5817                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
5818                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
5819                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
5820                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
5821                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
5822                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
5823                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
5824                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
5825                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
5826                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
5827                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
5828                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
5829                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
5830                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
5831                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
5832                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
5833                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
5834                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
5835                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
5836                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
5837                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
5838                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
5839                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
5840                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
5841                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
5842                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
5843         } },
5844         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5845                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
5846                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
5847                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
5848                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
5849                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
5850                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
5851                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
5852                 [ 7] = PIN_NONE,
5853                 [ 8] = PIN_NONE,
5854                 [ 9] = PIN_NONE,
5855                 [10] = PIN_NONE,
5856                 [11] = PIN_NONE,
5857                 [12] = PIN_NONE,
5858                 [13] = PIN_NONE,
5859                 [14] = PIN_NONE,
5860                 [15] = PIN_NONE,
5861                 [16] = PIN_NONE,
5862                 [17] = PIN_NONE,
5863                 [18] = PIN_NONE,
5864                 [19] = PIN_NONE,
5865                 [20] = PIN_NONE,
5866                 [21] = PIN_NONE,
5867                 [22] = PIN_NONE,
5868                 [23] = PIN_NONE,
5869                 [24] = PIN_NONE,
5870                 [25] = PIN_NONE,
5871                 [26] = PIN_NONE,
5872                 [27] = PIN_NONE,
5873                 [28] = PIN_NONE,
5874                 [29] = PIN_NONE,
5875                 [30] = PIN_NONE,
5876                 [31] = PIN_NONE,
5877         } },
5878         { /* sentinel */ },
5879 };
5880
5881 static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
5882                                             unsigned int pin)
5883 {
5884         const struct pinmux_bias_reg *reg;
5885         unsigned int bit;
5886
5887         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5888         if (!reg)
5889                 return PIN_CONFIG_BIAS_DISABLE;
5890
5891         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5892                 return PIN_CONFIG_BIAS_DISABLE;
5893         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5894                 return PIN_CONFIG_BIAS_PULL_UP;
5895         else
5896                 return PIN_CONFIG_BIAS_PULL_DOWN;
5897 }
5898
5899 static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5900                                    unsigned int bias)
5901 {
5902         const struct pinmux_bias_reg *reg;
5903         u32 enable, updown;
5904         unsigned int bit;
5905
5906         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5907         if (!reg)
5908                 return;
5909
5910         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5911         if (bias != PIN_CONFIG_BIAS_DISABLE)
5912                 enable |= BIT(bit);
5913
5914         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5915         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5916                 updown |= BIT(bit);
5917
5918         sh_pfc_write(pfc, reg->pud, updown);
5919         sh_pfc_write(pfc, reg->puen, enable);
5920 }
5921
5922 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
5923         .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
5924         .get_bias = r8a77965_pinmux_get_bias,
5925         .set_bias = r8a77965_pinmux_set_bias,
5926 };
5927
5928 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
5929         .name = "r8a77965_pfc",
5930         .ops = &r8a77965_pinmux_ops,
5931         .unlock_reg = 0xe6060000, /* PMMR */
5932
5933         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5934
5935         .pins = pinmux_pins,
5936         .nr_pins = ARRAY_SIZE(pinmux_pins),
5937         .groups = pinmux_groups,
5938         .nr_groups = ARRAY_SIZE(pinmux_groups),
5939         .functions = pinmux_functions,
5940         .nr_functions = ARRAY_SIZE(pinmux_functions),
5941
5942         .cfg_regs = pinmux_config_regs,
5943         .drive_regs = pinmux_drive_regs,
5944         .bias_regs = pinmux_bias_regs,
5945         .ioctrl_regs = pinmux_ioctrl_regs,
5946
5947         .pinmux_data = pinmux_data,
5948         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5949 };