drivers/pinctrl/freescale/pinctrl-imx.c

   1 /*
   2  * Core driver for the imx pin controller
   3  *
   4  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   5  * Copyright (C) 2012 Linaro Ltd.
   6  *
   7  * Author: Dong Aisheng <dong.aisheng@linaro.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_address.h>
  23 #include <linux/pinctrl/machine.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinmux.h>
  27 #include <linux/slab.h>
  28 #include <linux/regmap.h>
  29
  30 #include "../core.h"
  31 #include "pinctrl-imx.h"
  32
  33 /* The bits in CONFIG cell defined in binding doc*/
  34 #define IMX_NO_PAD_CTL  0x80000000      /* no pin config need */
  35 #define IMX_PAD_SION 0x40000000         /* set SION */
  36
  37 /**
  38  * @dev: a pointer back to containing device
  39  * @base: the offset to the controller in virtual memory
  40  */
  41 struct imx_pinctrl {
  42         struct device *dev;
  43         struct pinctrl_dev *pctl;
  44         void __iomem *base;
  45         void __iomem *input_sel_base;
  46         const struct imx_pinctrl_soc_info *info;
  47 };
  48
  49 static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
  50                                 const struct imx_pinctrl_soc_info *info,
  51                                 const char *name)
  52 {
  53         const struct imx_pin_group *grp = NULL;
  54         int i;
  55
  56         for (i = 0; i < info->ngroups; i++) {
  57                 if (!strcmp(info->groups[i].name, name)) {
  58                         grp = &info->groups[i];
  59                         break;
  60                 }
  61         }
  62
  63         return grp;
  64 }
  65
  66 static int imx_get_groups_count(struct pinctrl_dev *pctldev)
  67 {
  68         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  69         const struct imx_pinctrl_soc_info *info = ipctl->info;
  70
  71         return info->ngroups;
  72 }
  73
  74 static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
  75                                        unsigned selector)
  76 {
  77         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  78         const struct imx_pinctrl_soc_info *info = ipctl->info;
  79
  80         return info->groups[selector].name;
  81 }
  82
  83 static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  84                                const unsigned **pins,
  85                                unsigned *npins)
  86 {
  87         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  88         const struct imx_pinctrl_soc_info *info = ipctl->info;
  89
  90         if (selector >= info->ngroups)
  91                 return -EINVAL;
  92
  93         *pins = info->groups[selector].pin_ids;
  94         *npins = info->groups[selector].npins;
  95
  96         return 0;
  97 }
  98
  99 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 100                    unsigned offset)
 101 {
 102         seq_printf(s, "%s", dev_name(pctldev->dev));
 103 }
 104
 105 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
 106                         struct device_node *np,
 107                         struct pinctrl_map **map, unsigned *num_maps)
 108 {
 109         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 110         const struct imx_pinctrl_soc_info *info = ipctl->info;
 111         const struct imx_pin_group *grp;
 112         struct pinctrl_map *new_map;
 113         struct device_node *parent;
 114         int map_num = 1;
 115         int i, j;
 116
 117         /*
 118          * first find the group of this node and check if we need create
 119          * config maps for pins
 120          */
 121         grp = imx_pinctrl_find_group_by_name(info, np->name);
 122         if (!grp) {
 123                 dev_err(info->dev, "unable to find group for node %s\n",
 124                         np->name);
 125                 return -EINVAL;
 126         }
 127
 128         for (i = 0; i < grp->npins; i++) {
 129                 if (!(grp->pins[i].config & IMX_NO_PAD_CTL))
 130                         map_num++;
 131         }
 132
 133         new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
 134         if (!new_map)
 135                 return -ENOMEM;
 136
 137         *map = new_map;
 138         *num_maps = map_num;
 139
 140         /* create mux map */
 141         parent = of_get_parent(np);
 142         if (!parent) {
 143                 kfree(new_map);
 144                 return -EINVAL;
 145         }
 146         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 147         new_map[0].data.mux.function = parent->name;
 148         new_map[0].data.mux.group = np->name;
 149         of_node_put(parent);
 150
 151         /* create config map */
 152         new_map++;
 153         for (i = j = 0; i < grp->npins; i++) {
 154                 if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) {
 155                         new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
 156                         new_map[j].data.configs.group_or_pin =
 157                                         pin_get_name(pctldev, grp->pins[i].pin);
 158                         new_map[j].data.configs.configs = &grp->pins[i].config;
 159                         new_map[j].data.configs.num_configs = 1;
 160                         j++;
 161                 }
 162         }
 163
 164         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 165                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 166
 167         return 0;
 168 }
 169
 170 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
 171                                 struct pinctrl_map *map, unsigned num_maps)
 172 {
 173         kfree(map);
 174 }
 175
 176 static const struct pinctrl_ops imx_pctrl_ops = {
 177         .get_groups_count = imx_get_groups_count,
 178         .get_group_name = imx_get_group_name,
 179         .get_group_pins = imx_get_group_pins,
 180         .pin_dbg_show = imx_pin_dbg_show,
 181         .dt_node_to_map = imx_dt_node_to_map,
 182         .dt_free_map = imx_dt_free_map,
 183
 184 };
 185
 186 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 187                        unsigned group)
 188 {
 189         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 190         const struct imx_pinctrl_soc_info *info = ipctl->info;
 191         const struct imx_pin_reg *pin_reg;
 192         unsigned int npins, pin_id;
 193         int i;
 194         struct imx_pin_group *grp;
 195
 196         /*
 197          * Configure the mux mode for each pin in the group for a specific
 198          * function.
 199          */
 200         grp = &info->groups[group];
 201         npins = grp->npins;
 202
 203         dev_dbg(ipctl->dev, "enable function %s group %s\n",
 204                 info->functions[selector].name, grp->name);
 205
 206         for (i = 0; i < npins; i++) {
 207                 struct imx_pin *pin = &grp->pins[i];
 208                 pin_id = pin->pin;
 209                 pin_reg = &info->pin_regs[pin_id];
 210
 211                 if (pin_reg->mux_reg == -1) {
 212                         dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
 213                                 info->pins[pin_id].name);
 214                         return -EINVAL;
 215                 }
 216
 217                 if (info->flags & SHARE_MUX_CONF_REG) {
 218                         u32 reg;
 219                         reg = readl(ipctl->base + pin_reg->mux_reg);
 220                         reg &= ~(0x7 << 20);
 221                         reg |= (pin->mux_mode << 20);
 222                         writel(reg, ipctl->base + pin_reg->mux_reg);
 223                 } else {
 224                         writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
 225                 }
 226                 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 227                         pin_reg->mux_reg, pin->mux_mode);
 228
 229                 /*
 230                  * If the select input value begins with 0xff, it's a quirky
 231                  * select input and the value should be interpreted as below.
 232                  *     31     23      15      7        0
 233                  *     | 0xff | shift | width | select |
 234                  * It's used to work around the problem that the select
 235                  * input for some pin is not implemented in the select
 236                  * input register but in some general purpose register.
 237                  * We encode the select input value, width and shift of
 238                  * the bit field into input_val cell of pin function ID
 239                  * in device tree, and then decode them here for setting
 240                  * up the select input bits in general purpose register.
 241                  */
 242                 if (pin->input_val >> 24 == 0xff) {
 243                         u32 val = pin->input_val;
 244                         u8 select = val & 0xff;
 245                         u8 width = (val >> 8) & 0xff;
 246                         u8 shift = (val >> 16) & 0xff;
 247                         u32 mask = ((1 << width) - 1) << shift;
 248                         /*
 249                          * The input_reg[i] here is actually some IOMUXC general
 250                          * purpose register, not regular select input register.
 251                          */
 252                         val = readl(ipctl->base + pin->input_reg);
 253                         val &= ~mask;
 254                         val |= select << shift;
 255                         writel(val, ipctl->base + pin->input_reg);
 256                 } else if (pin->input_reg) {
 257                         /*
 258                          * Regular select input register can never be at offset
 259                          * 0, and we only print register value for regular case.
 260                          */
 261                         if (ipctl->input_sel_base)
 262                                 writel(pin->input_val, ipctl->input_sel_base +
 263                                                 pin->input_reg);
 264                         else
 265                                 writel(pin->input_val, ipctl->base +
 266                                                 pin->input_reg);
 267                         dev_dbg(ipctl->dev,
 268                                 "==>select_input: offset 0x%x val 0x%x\n",
 269                                 pin->input_reg, pin->input_val);
 270                 }
 271         }
 272
 273         return 0;
 274 }
 275
 276 static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 277 {
 278         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 279         const struct imx_pinctrl_soc_info *info = ipctl->info;
 280
 281         return info->nfunctions;
 282 }
 283
 284 static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
 285                                           unsigned selector)
 286 {
 287         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 288         const struct imx_pinctrl_soc_info *info = ipctl->info;
 289
 290         return info->functions[selector].name;
 291 }
 292
 293 static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 294                                const char * const **groups,
 295                                unsigned * const num_groups)
 296 {
 297         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 298         const struct imx_pinctrl_soc_info *info = ipctl->info;
 299
 300         *groups = info->functions[selector].groups;
 301         *num_groups = info->functions[selector].num_groups;
 302
 303         return 0;
 304 }
 305
 306 static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
 307                         struct pinctrl_gpio_range *range, unsigned offset)
 308 {
 309         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 310         const struct imx_pinctrl_soc_info *info = ipctl->info;
 311         const struct imx_pin_reg *pin_reg;
 312         struct imx_pin_group *grp;
 313         struct imx_pin *imx_pin;
 314         unsigned int pin, group;
 315         u32 reg;
 316
 317         /* Currently implementation only for shared mux/conf register */
 318         if (!(info->flags & SHARE_MUX_CONF_REG))
 319                 return -EINVAL;
 320
 321         pin_reg = &info->pin_regs[offset];
 322         if (pin_reg->mux_reg == -1)
 323                 return -EINVAL;
 324
 325         /* Find the pinctrl config with GPIO mux mode for the requested pin */
 326         for (group = 0; group < info->ngroups; group++) {
 327                 grp = &info->groups[group];
 328                 for (pin = 0; pin < grp->npins; pin++) {
 329                         imx_pin = &grp->pins[pin];
 330                         if (imx_pin->pin == offset && !imx_pin->mux_mode)
 331                                 goto mux_pin;
 332                 }
 333         }
 334
 335         return -EINVAL;
 336
 337 mux_pin:
 338         reg = readl(ipctl->base + pin_reg->mux_reg);
 339         reg &= ~(0x7 << 20);
 340         reg |= imx_pin->config;
 341         writel(reg, ipctl->base + pin_reg->mux_reg);
 342
 343         return 0;
 344 }
 345
 346 static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
 347                         struct pinctrl_gpio_range *range, unsigned offset)
 348 {
 349         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 350         const struct imx_pinctrl_soc_info *info = ipctl->info;
 351         const struct imx_pin_reg *pin_reg;
 352         u32 reg;
 353
 354         /*
 355          * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
 356          * They are part of the shared mux/conf register.
 357          */
 358         if (!(info->flags & SHARE_MUX_CONF_REG))
 359                 return;
 360
 361         pin_reg = &info->pin_regs[offset];
 362         if (pin_reg->mux_reg == -1)
 363                 return;
 364
 365         /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
 366         reg = readl(ipctl->base + pin_reg->mux_reg);
 367         reg &= ~0x7;
 368         writel(reg, ipctl->base + pin_reg->mux_reg);
 369 }
 370
 371 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 372            struct pinctrl_gpio_range *range, unsigned offset, bool input)
 373 {
 374         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 375         const struct imx_pinctrl_soc_info *info = ipctl->info;
 376         const struct imx_pin_reg *pin_reg;
 377         u32 reg;
 378
 379         /*
 380          * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
 381          * They are part of the shared mux/conf register.
 382          */
 383         if (!(info->flags & SHARE_MUX_CONF_REG))
 384                 return -EINVAL;
 385
 386         pin_reg = &info->pin_regs[offset];
 387         if (pin_reg->mux_reg == -1)
 388                 return -EINVAL;
 389
 390         /* IBE always enabled allows us to read the value "on the wire" */
 391         reg = readl(ipctl->base + pin_reg->mux_reg);
 392         if (input)
 393                 reg &= ~0x2;
 394         else
 395                 reg |= 0x2;
 396         writel(reg, ipctl->base + pin_reg->mux_reg);
 397
 398         return 0;
 399 }
 400
 401 static const struct pinmux_ops imx_pmx_ops = {
 402         .get_functions_count = imx_pmx_get_funcs_count,
 403         .get_function_name = imx_pmx_get_func_name,
 404         .get_function_groups = imx_pmx_get_groups,
 405         .set_mux = imx_pmx_set,
 406         .gpio_request_enable = imx_pmx_gpio_request_enable,
 407         .gpio_disable_free = imx_pmx_gpio_disable_free,
 408         .gpio_set_direction = imx_pmx_gpio_set_direction,
 409 };
 410
 411 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 412                              unsigned pin_id, unsigned long *config)
 413 {
 414         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 415         const struct imx_pinctrl_soc_info *info = ipctl->info;
 416         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 417
 418         if (pin_reg->conf_reg == -1) {
 419                 dev_err(info->dev, "Pin(%s) does not support config function\n",
 420                         info->pins[pin_id].name);
 421                 return -EINVAL;
 422         }
 423
 424         *config = readl(ipctl->base + pin_reg->conf_reg);
 425
 426         if (info->flags & SHARE_MUX_CONF_REG)
 427                 *config &= 0xffff;
 428
 429         return 0;
 430 }
 431
 432 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 433                              unsigned pin_id, unsigned long *configs,
 434                              unsigned num_configs)
 435 {
 436         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 437         const struct imx_pinctrl_soc_info *info = ipctl->info;
 438         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 439         int i;
 440
 441         if (pin_reg->conf_reg == -1) {
 442                 dev_err(info->dev, "Pin(%s) does not support config function\n",
 443                         info->pins[pin_id].name);
 444                 return -EINVAL;
 445         }
 446
 447         dev_dbg(ipctl->dev, "pinconf set pin %s\n",
 448                 info->pins[pin_id].name);
 449
 450         for (i = 0; i < num_configs; i++) {
 451                 if (info->flags & SHARE_MUX_CONF_REG) {
 452                         u32 reg;
 453                         reg = readl(ipctl->base + pin_reg->conf_reg);
 454                         reg &= ~0xffff;
 455                         reg |= configs[i];
 456                         writel(reg, ipctl->base + pin_reg->conf_reg);
 457                 } else {
 458                         writel(configs[i], ipctl->base + pin_reg->conf_reg);
 459                 }
 460                 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 461                         pin_reg->conf_reg, configs[i]);
 462         } /* for each config */
 463
 464         return 0;
 465 }
 466
 467 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 468                                    struct seq_file *s, unsigned pin_id)
 469 {
 470         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 471         const struct imx_pinctrl_soc_info *info = ipctl->info;
 472         const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
 473         unsigned long config;
 474
 475         if (!pin_reg || pin_reg->conf_reg == -1) {
 476                 seq_printf(s, "N/A");
 477                 return;
 478         }
 479
 480         config = readl(ipctl->base + pin_reg->conf_reg);
 481         seq_printf(s, "0x%lx", config);
 482 }
 483
 484 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 485                                          struct seq_file *s, unsigned group)
 486 {
 487         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 488         const struct imx_pinctrl_soc_info *info = ipctl->info;
 489         struct imx_pin_group *grp;
 490         unsigned long config;
 491         const char *name;
 492         int i, ret;
 493
 494         if (group > info->ngroups)
 495                 return;
 496
 497         seq_printf(s, "\n");
 498         grp = &info->groups[group];
 499         for (i = 0; i < grp->npins; i++) {
 500                 struct imx_pin *pin = &grp->pins[i];
 501                 name = pin_get_name(pctldev, pin->pin);
 502                 ret = imx_pinconf_get(pctldev, pin->pin, &config);
 503                 if (ret)
 504                         return;
 505                 seq_printf(s, "%s: 0x%lx", name, config);
 506         }
 507 }
 508
 509 static const struct pinconf_ops imx_pinconf_ops = {
 510         .pin_config_get = imx_pinconf_get,
 511         .pin_config_set = imx_pinconf_set,
 512         .pin_config_dbg_show = imx_pinconf_dbg_show,
 513         .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
 514 };
 515
 516 /*
 517  * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
 518  * 1 u32 CONFIG, so 24 types in total for each pin.
 519  */
 520 #define FSL_PIN_SIZE 24
 521 #define SHARE_FSL_PIN_SIZE 20
 522
 523 static int imx_pinctrl_parse_groups(struct device_node *np,
 524                                     struct imx_pin_group *grp,
 525                                     struct imx_pinctrl_soc_info *info,
 526                                     u32 index)
 527 {
 528         int size, pin_size;
 529         const __be32 *list;
 530         int i;
 531         u32 config;
 532
 533         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 534
 535         if (info->flags & SHARE_MUX_CONF_REG)
 536                 pin_size = SHARE_FSL_PIN_SIZE;
 537         else
 538                 pin_size = FSL_PIN_SIZE;
 539         /* Initialise group */
 540         grp->name = np->name;
 541
 542         /*
 543          * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
 544          * do sanity check and calculate pins number
 545          */
 546         list = of_get_property(np, "fsl,pins", &size);
 547         if (!list) {
 548                 dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
 549                 return -EINVAL;
 550         }
 551
 552         /* we do not check return since it's safe node passed down */
 553         if (!size || size % pin_size) {
 554                 dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
 555                 return -EINVAL;
 556         }
 557
 558         grp->npins = size / pin_size;
 559         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin),
 560                                 GFP_KERNEL);
 561         grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 562                                 GFP_KERNEL);
 563         if (!grp->pins || ! grp->pin_ids)
 564                 return -ENOMEM;
 565
 566         for (i = 0; i < grp->npins; i++) {
 567                 u32 mux_reg = be32_to_cpu(*list++);
 568                 u32 conf_reg;
 569                 unsigned int pin_id;
 570                 struct imx_pin_reg *pin_reg;
 571                 struct imx_pin *pin = &grp->pins[i];
 572
 573                 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
 574                         mux_reg = -1;
 575
 576                 if (info->flags & SHARE_MUX_CONF_REG) {
 577                         conf_reg = mux_reg;
 578                 } else {
 579                         conf_reg = be32_to_cpu(*list++);
 580                         if (!conf_reg)
 581                                 conf_reg = -1;
 582                 }
 583
 584                 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
 585                 pin_reg = &info->pin_regs[pin_id];
 586                 pin->pin = pin_id;
 587                 grp->pin_ids[i] = pin_id;
 588                 pin_reg->mux_reg = mux_reg;
 589                 pin_reg->conf_reg = conf_reg;
 590                 pin->input_reg = be32_to_cpu(*list++);
 591                 pin->mux_mode = be32_to_cpu(*list++);
 592                 pin->input_val = be32_to_cpu(*list++);
 593
 594                 /* SION bit is in mux register */
 595                 config = be32_to_cpu(*list++);
 596                 if (config & IMX_PAD_SION)
 597                         pin->mux_mode |= IOMUXC_CONFIG_SION;
 598                 pin->config = config & ~IMX_PAD_SION;
 599
 600                 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
 601                                 pin->mux_mode, pin->config);
 602         }
 603
 604         return 0;
 605 }
 606
 607 static int imx_pinctrl_parse_functions(struct device_node *np,
 608                                        struct imx_pinctrl_soc_info *info,
 609                                        u32 index)
 610 {
 611         struct device_node *child;
 612         struct imx_pmx_func *func;
 613         struct imx_pin_group *grp;
 614         u32 i = 0;
 615
 616         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 617
 618         func = &info->functions[index];
 619
 620         /* Initialise function */
 621         func->name = np->name;
 622         func->num_groups = of_get_child_count(np);
 623         if (func->num_groups == 0) {
 624                 dev_err(info->dev, "no groups defined in %s\n", np->full_name);
 625                 return -EINVAL;
 626         }
 627         func->groups = devm_kzalloc(info->dev,
 628                         func->num_groups * sizeof(char *), GFP_KERNEL);
 629
 630         for_each_child_of_node(np, child) {
 631                 func->groups[i] = child->name;
 632                 grp = &info->groups[info->group_index++];
 633                 imx_pinctrl_parse_groups(child, grp, info, i++);
 634         }
 635
 636         return 0;
 637 }
 638
 639 /*
 640  * Check if the DT contains pins in the direct child nodes. This indicates the
 641  * newer DT format to store pins. This function returns true if the first found
 642  * fsl,pins property is in a child of np. Otherwise false is returned.
 643  */
 644 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
 645 {
 646         struct device_node *function_np;
 647         struct device_node *pinctrl_np;
 648
 649         for_each_child_of_node(np, function_np) {
 650                 if (of_property_read_bool(function_np, "fsl,pins"))
 651                         return true;
 652
 653                 for_each_child_of_node(function_np, pinctrl_np) {
 654                         if (of_property_read_bool(pinctrl_np, "fsl,pins"))
 655                                 return false;
 656                 }
 657         }
 658
 659         return true;
 660 }
 661
 662 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
 663                                 struct imx_pinctrl_soc_info *info)
 664 {
 665         struct device_node *np = pdev->dev.of_node;
 666         struct device_node *child;
 667         u32 nfuncs = 0;
 668         u32 i = 0;
 669         bool flat_funcs;
 670
 671         if (!np)
 672                 return -ENODEV;
 673
 674         flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
 675         if (flat_funcs) {
 676                 nfuncs = 1;
 677         } else {
 678                 nfuncs = of_get_child_count(np);
 679                 if (nfuncs <= 0) {
 680                         dev_err(&pdev->dev, "no functions defined\n");
 681                         return -EINVAL;
 682                 }
 683         }
 684
 685         info->nfunctions = nfuncs;
 686         info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
 687                                         GFP_KERNEL);
 688         if (!info->functions)
 689                 return -ENOMEM;
 690
 691         if (flat_funcs) {
 692                 info->ngroups = of_get_child_count(np);
 693         } else {
 694                 info->ngroups = 0;
 695                 for_each_child_of_node(np, child)
 696                         info->ngroups += of_get_child_count(child);
 697         }
 698         info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
 699                                         GFP_KERNEL);
 700         if (!info->groups)
 701                 return -ENOMEM;
 702
 703         if (flat_funcs) {
 704                 imx_pinctrl_parse_functions(np, info, 0);
 705         } else {
 706                 for_each_child_of_node(np, child)
 707                         imx_pinctrl_parse_functions(child, info, i++);
 708         }
 709
 710         return 0;
 711 }
 712
 713 int imx_pinctrl_probe(struct platform_device *pdev,
 714                       struct imx_pinctrl_soc_info *info)
 715 {
 716         struct regmap_config config = { .name = "gpr" };
 717         struct device_node *dev_np = pdev->dev.of_node;
 718         struct pinctrl_desc *imx_pinctrl_desc;
 719         struct device_node *np;
 720         struct imx_pinctrl *ipctl;
 721         struct resource *res;
 722         struct regmap *gpr;
 723         int ret, i;
 724
 725         if (!info || !info->pins || !info->npins) {
 726                 dev_err(&pdev->dev, "wrong pinctrl info\n");
 727                 return -EINVAL;
 728         }
 729         info->dev = &pdev->dev;
 730
 731         if (info->gpr_compatible) {
 732                 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
 733                 if (!IS_ERR(gpr))
 734                         regmap_attach_dev(&pdev->dev, gpr, &config);
 735         }
 736
 737         /* Create state holders etc for this driver */
 738         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
 739         if (!ipctl)
 740                 return -ENOMEM;
 741
 742         info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
 743                                       info->npins, GFP_KERNEL);
 744         if (!info->pin_regs)
 745                 return -ENOMEM;
 746
 747         for (i = 0; i < info->npins; i++) {
 748                 info->pin_regs[i].mux_reg = -1;
 749                 info->pin_regs[i].conf_reg = -1;
 750         }
 751
 752         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 753         ipctl->base = devm_ioremap_resource(&pdev->dev, res);
 754         if (IS_ERR(ipctl->base))
 755                 return PTR_ERR(ipctl->base);
 756
 757         if (of_property_read_bool(dev_np, "fsl,input-sel")) {
 758                 np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
 759                 if (!np) {
 760                         dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
 761                         return -EINVAL;
 762                 }
 763
 764                 ipctl->input_sel_base = of_iomap(np, 0);
 765                 of_node_put(np);
 766                 if (!ipctl->input_sel_base) {
 767                         dev_err(&pdev->dev,
 768                                 "iomuxc input select base address not found\n");
 769                         return -ENOMEM;
 770                 }
 771         }
 772
 773         imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
 774                                         GFP_KERNEL);
 775         if (!imx_pinctrl_desc)
 776                 return -ENOMEM;
 777
 778         imx_pinctrl_desc->name = dev_name(&pdev->dev);
 779         imx_pinctrl_desc->pins = info->pins;
 780         imx_pinctrl_desc->npins = info->npins;
 781         imx_pinctrl_desc->pctlops = &imx_pctrl_ops,
 782         imx_pinctrl_desc->pmxops = &imx_pmx_ops,
 783         imx_pinctrl_desc->confops = &imx_pinconf_ops,
 784         imx_pinctrl_desc->owner = THIS_MODULE,
 785
 786         ret = imx_pinctrl_probe_dt(pdev, info);
 787         if (ret) {
 788                 dev_err(&pdev->dev, "fail to probe dt properties\n");
 789                 return ret;
 790         }
 791
 792         ipctl->info = info;
 793         ipctl->dev = info->dev;
 794         platform_set_drvdata(pdev, ipctl);
 795         ipctl->pctl = devm_pinctrl_register(&pdev->dev,
 796                                             imx_pinctrl_desc, ipctl);
 797         if (IS_ERR(ipctl->pctl)) {
 798                 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
 799                 return PTR_ERR(ipctl->pctl);
 800         }
 801
 802         dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
 803
 804         return 0;
 805 }