2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
26 #include "pcie-designware.h"
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
34 #define PORT_LINK_MODE_8_LANES (0xf << 16)
36 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
37 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
38 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
39 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
41 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
42 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
44 #define PCIE_MSI_ADDR_LO 0x820
45 #define PCIE_MSI_ADDR_HI 0x824
46 #define PCIE_MSI_INTR0_ENABLE 0x828
47 #define PCIE_MSI_INTR0_MASK 0x82C
48 #define PCIE_MSI_INTR0_STATUS 0x830
50 #define PCIE_ATU_VIEWPORT 0x900
51 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
52 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
53 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
54 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
55 #define PCIE_ATU_CR1 0x904
56 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
57 #define PCIE_ATU_TYPE_IO (0x2 << 0)
58 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
59 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
60 #define PCIE_ATU_CR2 0x908
61 #define PCIE_ATU_ENABLE (0x1 << 31)
62 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
63 #define PCIE_ATU_LOWER_BASE 0x90C
64 #define PCIE_ATU_UPPER_BASE 0x910
65 #define PCIE_ATU_LIMIT 0x914
66 #define PCIE_ATU_LOWER_TARGET 0x918
67 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
68 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
69 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
70 #define PCIE_ATU_UPPER_TARGET 0x91C
72 static struct hw_pci dw_pci;
74 static unsigned long global_io_offset;
76 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
78 BUG_ON(!sys->private_data);
80 return sys->private_data;
83 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
88 *val = (*val >> (8 * (where & 3))) & 0xff;
90 *val = (*val >> (8 * (where & 3))) & 0xffff;
92 return PCIBIOS_BAD_REGISTER_NUMBER;
94 return PCIBIOS_SUCCESSFUL;
97 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
102 writew(val, addr + (where & 2));
104 writeb(val, addr + (where & 3));
106 return PCIBIOS_BAD_REGISTER_NUMBER;
108 return PCIBIOS_SUCCESSFUL;
111 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
113 if (pp->ops->readl_rc)
114 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
116 *val = readl(pp->dbi_base + reg);
119 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
121 if (pp->ops->writel_rc)
122 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
124 writel(val, pp->dbi_base + reg);
127 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
132 if (pp->ops->rd_own_conf)
133 ret = pp->ops->rd_own_conf(pp, where, size, val);
135 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
141 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
146 if (pp->ops->wr_own_conf)
147 ret = pp->ops->wr_own_conf(pp, where, size, val);
149 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
155 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
156 int type, u64 cpu_addr, u64 pci_addr, u32 size)
158 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
160 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
161 dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
162 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
164 dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
165 dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
166 dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
167 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
170 static struct irq_chip dw_msi_irq_chip = {
172 .irq_enable = pci_msi_unmask_irq,
173 .irq_disable = pci_msi_mask_irq,
174 .irq_mask = pci_msi_mask_irq,
175 .irq_unmask = pci_msi_unmask_irq,
178 /* MSI int handler */
179 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
183 irqreturn_t ret = IRQ_NONE;
185 for (i = 0; i < MAX_MSI_CTRLS; i++) {
186 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
191 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
192 irq = irq_find_mapping(pp->irq_domain,
194 dw_pcie_wr_own_conf(pp,
195 PCIE_MSI_INTR0_STATUS + i * 12,
197 generic_handle_irq(irq);
206 void dw_pcie_msi_init(struct pcie_port *pp)
208 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
210 /* program the msi_data */
211 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
212 virt_to_phys((void *)pp->msi_data));
213 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
216 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
218 unsigned int res, bit, val;
220 res = (irq / 32) * 12;
222 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
224 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
227 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
228 unsigned int nvec, unsigned int pos)
232 for (i = 0; i < nvec; i++) {
233 irq_set_msi_desc_off(irq_base, i, NULL);
234 /* Disable corresponding interrupt on MSI controller */
235 if (pp->ops->msi_clear_irq)
236 pp->ops->msi_clear_irq(pp, pos + i);
238 dw_pcie_msi_clear_irq(pp, pos + i);
241 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
244 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
246 unsigned int res, bit, val;
248 res = (irq / 32) * 12;
250 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
252 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
255 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
258 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
260 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
261 order_base_2(no_irqs));
265 irq = irq_find_mapping(pp->irq_domain, pos0);
270 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
271 * descs so there is no need to allocate descs here. We can therefore
272 * assume that if irq_find_mapping above returns non-zero, then the
273 * descs are also successfully allocated.
276 for (i = 0; i < no_irqs; i++) {
277 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
278 clear_irq_range(pp, irq, i, pos0);
281 /*Enable corresponding interrupt in MSI interrupt controller */
282 if (pp->ops->msi_set_irq)
283 pp->ops->msi_set_irq(pp, pos0 + i);
285 dw_pcie_msi_set_irq(pp, pos0 + i);
296 static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
297 struct msi_desc *desc)
301 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
303 if (desc->msi_attrib.is_msix)
306 irq = assign_irq(1, desc, &pos);
310 if (pp->ops->get_msi_addr)
311 msg.address_lo = pp->ops->get_msi_addr(pp);
313 msg.address_lo = virt_to_phys((void *)pp->msi_data);
314 msg.address_hi = 0x0;
316 if (pp->ops->get_msi_data)
317 msg.data = pp->ops->get_msi_data(pp, pos);
321 pci_write_msi_msg(irq, &msg);
326 static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
328 struct irq_data *data = irq_get_irq_data(irq);
329 struct msi_desc *msi = irq_data_get_msi(data);
330 struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata);
332 clear_irq_range(pp, irq, 1, data->hwirq);
335 static struct msi_controller dw_pcie_msi_chip = {
336 .setup_irq = dw_msi_setup_irq,
337 .teardown_irq = dw_msi_teardown_irq,
340 int dw_pcie_link_up(struct pcie_port *pp)
342 if (pp->ops->link_up)
343 return pp->ops->link_up(pp);
348 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
349 irq_hw_number_t hwirq)
351 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
352 irq_set_chip_data(irq, domain->host_data);
353 set_irq_flags(irq, IRQF_VALID);
358 static const struct irq_domain_ops msi_domain_ops = {
359 .map = dw_pcie_msi_map,
362 int dw_pcie_host_init(struct pcie_port *pp)
364 struct device_node *np = pp->dev->of_node;
365 struct platform_device *pdev = to_platform_device(pp->dev);
366 struct of_pci_range range;
367 struct of_pci_range_parser parser;
368 struct resource *cfg_res;
373 /* Find the address cell size and the number of cells in order to get
374 * the untranslated address.
376 of_property_read_u32(np, "#address-cells", &na);
377 ns = of_n_size_cells(np);
379 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
381 pp->cfg0_size = resource_size(cfg_res)/2;
382 pp->cfg1_size = resource_size(cfg_res)/2;
383 pp->cfg0_base = cfg_res->start;
384 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
386 /* Find the untranslated configuration space address */
387 index = of_property_match_string(np, "reg-names", "config");
388 addrp = of_get_address(np, index, NULL, NULL);
389 pp->cfg0_mod_base = of_read_number(addrp, ns);
390 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
392 dev_err(pp->dev, "missing *config* reg space\n");
395 if (of_pci_range_parser_init(&parser, np)) {
396 dev_err(pp->dev, "missing ranges property\n");
400 /* Get the I/O and memory ranges from DT */
401 for_each_of_pci_range(&parser, &range) {
402 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
404 if (restype == IORESOURCE_IO) {
405 of_pci_range_to_resource(&range, np, &pp->io);
407 pp->io.start = max_t(resource_size_t,
409 range.pci_addr + global_io_offset);
410 pp->io.end = min_t(resource_size_t,
412 range.pci_addr + range.size
413 + global_io_offset - 1);
414 pp->io_size = resource_size(&pp->io);
415 pp->io_bus_addr = range.pci_addr;
416 pp->io_base = range.cpu_addr;
418 /* Find the untranslated IO space address */
419 pp->io_mod_base = of_read_number(parser.range -
422 if (restype == IORESOURCE_MEM) {
423 of_pci_range_to_resource(&range, np, &pp->mem);
424 pp->mem.name = "MEM";
425 pp->mem_size = resource_size(&pp->mem);
426 pp->mem_bus_addr = range.pci_addr;
428 /* Find the untranslated MEM space address */
429 pp->mem_mod_base = of_read_number(parser.range -
433 of_pci_range_to_resource(&range, np, &pp->cfg);
434 pp->cfg0_size = resource_size(&pp->cfg)/2;
435 pp->cfg1_size = resource_size(&pp->cfg)/2;
436 pp->cfg0_base = pp->cfg.start;
437 pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
439 /* Find the untranslated configuration space address */
440 pp->cfg0_mod_base = of_read_number(parser.range -
442 pp->cfg1_mod_base = pp->cfg0_mod_base +
447 ret = of_pci_parse_bus_range(np, &pp->busn);
449 pp->busn.name = np->name;
452 pp->busn.flags = IORESOURCE_BUS;
453 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
458 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
459 resource_size(&pp->cfg));
461 dev_err(pp->dev, "error with ioremap\n");
466 pp->mem_base = pp->mem.start;
468 if (!pp->va_cfg0_base) {
469 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
471 if (!pp->va_cfg0_base) {
472 dev_err(pp->dev, "error with ioremap in function\n");
477 if (!pp->va_cfg1_base) {
478 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
480 if (!pp->va_cfg1_base) {
481 dev_err(pp->dev, "error with ioremap\n");
486 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
487 dev_err(pp->dev, "Failed to parse the number of lanes\n");
491 if (IS_ENABLED(CONFIG_PCI_MSI)) {
492 if (!pp->ops->msi_host_init) {
493 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
494 MAX_MSI_IRQS, &msi_domain_ops,
496 if (!pp->irq_domain) {
497 dev_err(pp->dev, "irq domain init failed\n");
501 for (i = 0; i < MAX_MSI_IRQS; i++)
502 irq_create_mapping(pp->irq_domain, i);
504 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
510 if (pp->ops->host_init)
511 pp->ops->host_init(pp);
513 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
515 /* program correct class for RC */
516 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
518 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
519 val |= PORT_LOGIC_SPEED_CHANGE;
520 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
522 #ifdef CONFIG_PCI_MSI
523 dw_pcie_msi_chip.dev = pp->dev;
524 dw_pci.msi_ctrl = &dw_pcie_msi_chip;
527 dw_pci.nr_controllers = 1;
528 dw_pci.private_data = (void **)&pp;
530 pci_common_init_dev(pp->dev, &dw_pci);
535 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
536 u32 devfn, int where, int size, u32 *val)
538 int ret = PCIBIOS_SUCCESSFUL;
541 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
542 PCIE_ATU_FUNC(PCI_FUNC(devfn));
543 address = where & ~0x3;
545 if (bus->parent->number == pp->root_bus_nr) {
546 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
547 PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
548 busdev, pp->cfg0_size);
549 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
551 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
552 PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
553 pp->mem_bus_addr, pp->mem_size);
555 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
556 PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
557 busdev, pp->cfg1_size);
558 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
560 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
561 PCIE_ATU_TYPE_IO, pp->io_mod_base,
562 pp->io_bus_addr, pp->io_size);
568 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
569 u32 devfn, int where, int size, u32 val)
571 int ret = PCIBIOS_SUCCESSFUL;
574 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
575 PCIE_ATU_FUNC(PCI_FUNC(devfn));
576 address = where & ~0x3;
578 if (bus->parent->number == pp->root_bus_nr) {
579 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
580 PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
581 busdev, pp->cfg0_size);
582 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
584 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
585 PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
586 pp->mem_bus_addr, pp->mem_size);
588 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
589 PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
590 busdev, pp->cfg1_size);
591 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
593 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
594 PCIE_ATU_TYPE_IO, pp->io_mod_base,
595 pp->io_bus_addr, pp->io_size);
601 static int dw_pcie_valid_config(struct pcie_port *pp,
602 struct pci_bus *bus, int dev)
604 /* If there is no link, then there is no device */
605 if (bus->number != pp->root_bus_nr) {
606 if (!dw_pcie_link_up(pp))
610 /* access only one slot on each root port */
611 if (bus->number == pp->root_bus_nr && dev > 0)
615 * do not read more than one device on the bus directly attached
616 * to RC's (Virtual Bridge's) DS side.
618 if (bus->primary == pp->root_bus_nr && dev > 0)
624 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
627 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
630 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
632 return PCIBIOS_DEVICE_NOT_FOUND;
635 if (bus->number != pp->root_bus_nr)
636 if (pp->ops->rd_other_conf)
637 ret = pp->ops->rd_other_conf(pp, bus, devfn,
640 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
643 ret = dw_pcie_rd_own_conf(pp, where, size, val);
648 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
649 int where, int size, u32 val)
651 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
654 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
655 return PCIBIOS_DEVICE_NOT_FOUND;
657 if (bus->number != pp->root_bus_nr)
658 if (pp->ops->wr_other_conf)
659 ret = pp->ops->wr_other_conf(pp, bus, devfn,
662 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
665 ret = dw_pcie_wr_own_conf(pp, where, size, val);
670 static struct pci_ops dw_pcie_ops = {
671 .read = dw_pcie_rd_conf,
672 .write = dw_pcie_wr_conf,
675 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
677 struct pcie_port *pp;
679 pp = sys_to_pcie(sys);
681 if (global_io_offset < SZ_1M && pp->io_size > 0) {
682 sys->io_offset = global_io_offset - pp->io_bus_addr;
683 pci_ioremap_io(global_io_offset, pp->io_base);
684 global_io_offset += SZ_64K;
685 pci_add_resource_offset(&sys->resources, &pp->io,
689 sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
690 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
691 pci_add_resource(&sys->resources, &pp->busn);
696 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
699 struct pcie_port *pp = sys_to_pcie(sys);
701 pp->root_bus_nr = sys->busnr;
702 bus = pci_create_root_bus(pp->dev, sys->busnr,
703 &dw_pcie_ops, sys, &sys->resources);
707 pci_scan_child_bus(bus);
709 if (bus && pp->ops->scan_bus)
710 pp->ops->scan_bus(pp);
715 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
717 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
720 irq = of_irq_parse_and_map_pci(dev, slot, pin);
727 static struct hw_pci dw_pci = {
728 .setup = dw_pcie_setup,
729 .scan = dw_pcie_scan_bus,
730 .map_irq = dw_pcie_map_irq,
733 void dw_pcie_setup_rc(struct pcie_port *pp)
739 /* set the number of lanes */
740 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
741 val &= ~PORT_LINK_MODE_MASK;
744 val |= PORT_LINK_MODE_1_LANES;
747 val |= PORT_LINK_MODE_2_LANES;
750 val |= PORT_LINK_MODE_4_LANES;
753 val |= PORT_LINK_MODE_8_LANES;
756 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
758 /* set link width speed control register */
759 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
760 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
763 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
766 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
769 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
772 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
775 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
778 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
779 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
781 /* setup interrupt pins */
782 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
785 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
787 /* setup bus numbers */
788 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
791 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
793 /* setup memory base, memory limit */
794 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
795 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
796 val = memlimit | membase;
797 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
799 /* setup command register */
800 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
802 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
803 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
804 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
807 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
808 MODULE_DESCRIPTION("Designware PCIe host controller driver");
809 MODULE_LICENSE("GPL v2");