2 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_pci.h>
24 #include <linux/pci.h>
25 #include <linux/phy/phy.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/resource.h>
29 #include <linux/types.h>
30 #include <linux/mfd/syscon.h>
31 #include <linux/regmap.h>
33 #include "pcie-designware.h"
35 /* PCIe controller wrapper DRA7XX configuration registers */
37 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
38 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
39 #define ERR_SYS BIT(0)
40 #define ERR_FATAL BIT(1)
41 #define ERR_NONFATAL BIT(2)
42 #define ERR_COR BIT(3)
43 #define ERR_AXI BIT(4)
44 #define ERR_ECRC BIT(5)
45 #define PME_TURN_OFF BIT(8)
46 #define PME_TO_ACK BIT(9)
47 #define PM_PME BIT(10)
48 #define LINK_REQ_RST BIT(11)
49 #define LINK_UP_EVT BIT(12)
50 #define CFG_BME_EVT BIT(13)
51 #define CFG_MSE_EVT BIT(14)
52 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
53 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
54 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
56 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
57 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
63 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
65 #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
66 #define DEVICE_TYPE_EP 0x0
67 #define DEVICE_TYPE_LEG_EP 0x1
68 #define DEVICE_TYPE_RC 0x4
70 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
73 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
74 #define LINK_UP BIT(16)
75 #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
77 #define EXP_CAP_ID_OFFSET 0x70
79 #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
80 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
82 #define PCIECTRL_TI_CONF_MSI_XMT 0x012c
83 #define MSI_REQ_GRANT BIT(0)
84 #define MSI_VECTOR_SHIFT 7
88 void __iomem *base; /* DT ti_conf */
89 int phy_count; /* DT phy-names count */
92 struct irq_domain *irq_domain;
93 enum dw_pcie_device_mode mode;
96 struct dra7xx_pcie_of_data {
97 enum dw_pcie_device_mode mode;
100 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
102 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
104 return readl(pcie->base + offset);
107 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
110 writel(value, pcie->base + offset);
113 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
115 return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
118 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
120 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
121 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
123 return !!(reg & LINK_UP);
126 static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
128 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
131 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
133 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
136 static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
138 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
139 struct device *dev = pci->dev;
141 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
143 if (dw_pcie_link_up(pci)) {
144 dev_err(dev, "link is already up\n");
148 if (dra7xx->link_gen == 1) {
149 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
151 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
152 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
153 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
154 dw_pcie_write(pci->dbi_base + exp_cap_off +
155 PCI_EXP_LNKCAP, 4, reg);
158 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
160 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
161 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
162 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
163 dw_pcie_write(pci->dbi_base + exp_cap_off +
164 PCI_EXP_LNKCTL2, 2, reg);
168 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
170 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
175 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
177 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
178 LEG_EP_INTERRUPTS | MSI);
180 dra7xx_pcie_writel(dra7xx,
181 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
182 MSI | LEG_EP_INTERRUPTS);
185 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
187 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
189 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
193 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
195 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
196 dra7xx_pcie_enable_msi_interrupts(dra7xx);
199 static int dra7xx_pcie_host_init(struct pcie_port *pp)
201 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
202 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
204 dw_pcie_setup_rc(pp);
206 dra7xx_pcie_establish_link(pci);
207 dw_pcie_wait_for_link(pci);
208 dw_pcie_msi_init(pp);
209 dra7xx_pcie_enable_interrupts(dra7xx);
214 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
215 .host_init = dra7xx_pcie_host_init,
218 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
219 irq_hw_number_t hwirq)
221 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
222 irq_set_chip_data(irq, domain->host_data);
227 static const struct irq_domain_ops intx_domain_ops = {
228 .map = dra7xx_pcie_intx_map,
229 .xlate = pci_irqd_intx_xlate,
232 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
235 struct device *dev = pci->dev;
236 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
237 struct device_node *node = dev->of_node;
238 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
240 if (!pcie_intc_node) {
241 dev_err(dev, "No PCIe Intc node found\n");
245 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
246 &intx_domain_ops, pp);
247 if (!dra7xx->irq_domain) {
248 dev_err(dev, "Failed to get a INTx IRQ domain\n");
255 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
257 struct dra7xx_pcie *dra7xx = arg;
258 struct dw_pcie *pci = dra7xx->pci;
259 struct pcie_port *pp = &pci->pp;
262 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
266 dw_handle_msi_irq(pp);
272 generic_handle_irq(irq_find_mapping(dra7xx->irq_domain,
277 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
282 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
284 struct dra7xx_pcie *dra7xx = arg;
285 struct dw_pcie *pci = dra7xx->pci;
286 struct device *dev = pci->dev;
287 struct dw_pcie_ep *ep = &pci->ep;
290 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
293 dev_dbg(dev, "System Error\n");
296 dev_dbg(dev, "Fatal Error\n");
298 if (reg & ERR_NONFATAL)
299 dev_dbg(dev, "Non Fatal Error\n");
302 dev_dbg(dev, "Correctable Error\n");
305 dev_dbg(dev, "AXI tag lookup fatal Error\n");
308 dev_dbg(dev, "ECRC Error\n");
310 if (reg & PME_TURN_OFF)
312 "Power Management Event Turn-Off message received\n");
314 if (reg & PME_TO_ACK)
316 "Power Management Turn-Off Ack message received\n");
319 dev_dbg(dev, "PM Power Management Event message received\n");
321 if (reg & LINK_REQ_RST)
322 dev_dbg(dev, "Link Request Reset\n");
324 if (reg & LINK_UP_EVT) {
325 if (dra7xx->mode == DW_PCIE_EP_TYPE)
326 dw_pcie_ep_linkup(ep);
327 dev_dbg(dev, "Link-up state change\n");
330 if (reg & CFG_BME_EVT)
331 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
333 if (reg & CFG_MSE_EVT)
334 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
336 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
341 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
343 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
344 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
347 for (bar = BAR_0; bar <= BAR_5; bar++)
348 dw_pcie_ep_reset_bar(pci, bar);
350 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
353 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
355 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
357 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
360 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
365 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
366 reg |= MSI_REQ_GRANT;
367 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
370 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep,
371 enum pci_epc_irq_type type, u8 interrupt_num)
373 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
374 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
377 case PCI_EPC_IRQ_LEGACY:
378 dra7xx_pcie_raise_legacy_irq(dra7xx);
380 case PCI_EPC_IRQ_MSI:
381 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
384 dev_err(pci->dev, "UNKNOWN IRQ type\n");
390 static struct dw_pcie_ep_ops pcie_ep_ops = {
391 .ep_init = dra7xx_pcie_ep_init,
392 .raise_irq = dra7xx_pcie_raise_irq,
395 static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
396 struct platform_device *pdev)
399 struct dw_pcie_ep *ep;
400 struct resource *res;
401 struct device *dev = &pdev->dev;
402 struct dw_pcie *pci = dra7xx->pci;
405 ep->ops = &pcie_ep_ops;
407 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
408 pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
412 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
413 pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
417 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
421 ep->phys_base = res->start;
422 ep->addr_size = resource_size(res);
424 ret = dw_pcie_ep_init(ep);
426 dev_err(dev, "failed to initialize endpoint\n");
433 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
434 struct platform_device *pdev)
437 struct dw_pcie *pci = dra7xx->pci;
438 struct pcie_port *pp = &pci->pp;
439 struct device *dev = pci->dev;
440 struct resource *res;
442 pp->irq = platform_get_irq(pdev, 1);
444 dev_err(dev, "missing IRQ resource\n");
448 ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
449 IRQF_SHARED | IRQF_NO_THREAD,
450 "dra7-pcie-msi", dra7xx);
452 dev_err(dev, "failed to request irq\n");
456 ret = dra7xx_pcie_init_irq_domain(pp);
460 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
461 pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
465 pp->ops = &dra7xx_pcie_host_ops;
467 ret = dw_pcie_host_init(pp);
469 dev_err(dev, "failed to initialize host\n");
476 static const struct dw_pcie_ops dw_pcie_ops = {
477 .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
478 .start_link = dra7xx_pcie_establish_link,
479 .stop_link = dra7xx_pcie_stop_link,
480 .link_up = dra7xx_pcie_link_up,
483 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
485 int phy_count = dra7xx->phy_count;
487 while (phy_count--) {
488 phy_power_off(dra7xx->phy[phy_count]);
489 phy_exit(dra7xx->phy[phy_count]);
493 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
495 int phy_count = dra7xx->phy_count;
499 for (i = 0; i < phy_count; i++) {
500 ret = phy_init(dra7xx->phy[i]);
504 ret = phy_power_on(dra7xx->phy[i]);
506 phy_exit(dra7xx->phy[i]);
515 phy_power_off(dra7xx->phy[i]);
516 phy_exit(dra7xx->phy[i]);
522 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
523 .mode = DW_PCIE_RC_TYPE,
526 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
527 .mode = DW_PCIE_EP_TYPE,
530 static const struct of_device_id of_dra7xx_pcie_match[] = {
532 .compatible = "ti,dra7-pcie",
533 .data = &dra7xx_pcie_rc_of_data,
536 .compatible = "ti,dra7-pcie-ep",
537 .data = &dra7xx_pcie_ep_of_data,
543 * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
544 * @dra7xx: the dra7xx device where the workaround should be applied
546 * Access to the PCIe slave port that are not 32-bit aligned will result
547 * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
548 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
551 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
553 static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
556 struct device_node *np = dev->of_node;
557 struct of_phandle_args args;
558 struct regmap *regmap;
560 regmap = syscon_regmap_lookup_by_phandle(np,
561 "ti,syscon-unaligned-access");
562 if (IS_ERR(regmap)) {
563 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
567 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
570 dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
574 ret = regmap_update_bits(regmap, args.args[0], args.args[1],
577 dev_err(dev, "failed to enable unaligned access\n");
579 of_node_put(args.np);
584 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
592 struct device_link **link;
594 struct resource *res;
596 struct dra7xx_pcie *dra7xx;
597 struct device *dev = &pdev->dev;
598 struct device_node *np = dev->of_node;
600 struct gpio_desc *reset;
601 const struct of_device_id *match;
602 const struct dra7xx_pcie_of_data *data;
603 enum dw_pcie_device_mode mode;
605 match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
609 data = (struct dra7xx_pcie_of_data *)match->data;
610 mode = (enum dw_pcie_device_mode)data->mode;
612 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
616 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
621 pci->ops = &dw_pcie_ops;
623 irq = platform_get_irq(pdev, 0);
625 dev_err(dev, "missing IRQ resource: %d\n", irq);
629 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
630 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
634 phy_count = of_property_count_strings(np, "phy-names");
636 dev_err(dev, "unable to find the strings\n");
640 phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
644 link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
648 for (i = 0; i < phy_count; i++) {
649 snprintf(name, sizeof(name), "pcie-phy%d", i);
650 phy[i] = devm_phy_get(dev, name);
652 return PTR_ERR(phy[i]);
654 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
664 dra7xx->phy_count = phy_count;
666 ret = dra7xx_pcie_enable_phy(dra7xx);
668 dev_err(dev, "failed to enable phy\n");
672 platform_set_drvdata(pdev, dra7xx);
674 pm_runtime_enable(dev);
675 ret = pm_runtime_get_sync(dev);
677 dev_err(dev, "pm_runtime_get_sync failed\n");
681 reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
683 ret = PTR_ERR(reset);
684 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
688 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
690 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
692 dra7xx->link_gen = of_pci_get_max_link_speed(np);
693 if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
694 dra7xx->link_gen = 2;
697 case DW_PCIE_RC_TYPE:
698 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
703 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
705 ret = dra7xx_add_pcie_port(dra7xx, pdev);
709 case DW_PCIE_EP_TYPE:
710 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
715 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
718 ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
722 ret = dra7xx_add_pcie_ep(dra7xx, pdev);
727 dev_err(dev, "INVALID device type %d\n", mode);
731 ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
732 IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
734 dev_err(dev, "failed to request irq\n");
744 pm_runtime_disable(dev);
745 dra7xx_pcie_disable_phy(dra7xx);
749 device_link_del(link[i]);
754 #ifdef CONFIG_PM_SLEEP
755 static int dra7xx_pcie_suspend(struct device *dev)
757 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
758 struct dw_pcie *pci = dra7xx->pci;
761 if (dra7xx->mode != DW_PCIE_RC_TYPE)
765 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
766 val &= ~PCI_COMMAND_MEMORY;
767 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
772 static int dra7xx_pcie_resume(struct device *dev)
774 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
775 struct dw_pcie *pci = dra7xx->pci;
778 if (dra7xx->mode != DW_PCIE_RC_TYPE)
782 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
783 val |= PCI_COMMAND_MEMORY;
784 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
789 static int dra7xx_pcie_suspend_noirq(struct device *dev)
791 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
793 dra7xx_pcie_disable_phy(dra7xx);
798 static int dra7xx_pcie_resume_noirq(struct device *dev)
800 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
803 ret = dra7xx_pcie_enable_phy(dra7xx);
805 dev_err(dev, "failed to enable phy\n");
813 static void dra7xx_pcie_shutdown(struct platform_device *pdev)
815 struct device *dev = &pdev->dev;
816 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
819 dra7xx_pcie_stop_link(dra7xx->pci);
821 ret = pm_runtime_put_sync(dev);
823 dev_dbg(dev, "pm_runtime_put_sync failed\n");
825 pm_runtime_disable(dev);
826 dra7xx_pcie_disable_phy(dra7xx);
829 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
830 SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
831 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
832 dra7xx_pcie_resume_noirq)
835 static struct platform_driver dra7xx_pcie_driver = {
838 .of_match_table = of_dra7xx_pcie_match,
839 .suppress_bind_attrs = true,
840 .pm = &dra7xx_pcie_pm_ops,
842 .shutdown = dra7xx_pcie_shutdown,
844 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);